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10#include <linux/platform_device.h>
11#include <linux/init.h>
12#include <linux/serial.h>
13#include <linux/serial_sci.h>
14#include <linux/io.h>
15#include <linux/mm.h>
16#include <linux/sh_dma.h>
17#include <linux/sh_timer.h>
18#include <linux/sh_intc.h>
19#include <asm/mmzone.h>
20#include <cpu/dma-register.h>
21
22static struct plat_sci_port scif0_platform_data = {
23 .scscr = SCSCR_REIE | SCSCR_CKE1,
24 .type = PORT_SCIF,
25 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
26};
27
28static struct resource scif0_resources[] = {
29 DEFINE_RES_MEM(0xffea0000, 0x100),
30 DEFINE_RES_IRQ(evt2irq(0x700)),
31};
32
33static struct platform_device scif0_device = {
34 .name = "sh-sci",
35 .id = 0,
36 .resource = scif0_resources,
37 .num_resources = ARRAY_SIZE(scif0_resources),
38 .dev = {
39 .platform_data = &scif0_platform_data,
40 },
41};
42
43static struct plat_sci_port scif1_platform_data = {
44 .scscr = SCSCR_REIE | SCSCR_CKE1,
45 .type = PORT_SCIF,
46 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
47};
48
49static struct resource scif1_resources[] = {
50 DEFINE_RES_MEM(0xffeb0000, 0x100),
51 DEFINE_RES_IRQ(evt2irq(0x780)),
52};
53
54static struct platform_device scif1_device = {
55 .name = "sh-sci",
56 .id = 1,
57 .resource = scif1_resources,
58 .num_resources = ARRAY_SIZE(scif1_resources),
59 .dev = {
60 .platform_data = &scif1_platform_data,
61 },
62};
63
64static struct plat_sci_port scif2_platform_data = {
65 .scscr = SCSCR_REIE | SCSCR_CKE1,
66 .type = PORT_SCIF,
67 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
68};
69
70static struct resource scif2_resources[] = {
71 DEFINE_RES_MEM(0xffec0000, 0x100),
72 DEFINE_RES_IRQ(evt2irq(0x980)),
73};
74
75static struct platform_device scif2_device = {
76 .name = "sh-sci",
77 .id = 2,
78 .resource = scif2_resources,
79 .num_resources = ARRAY_SIZE(scif2_resources),
80 .dev = {
81 .platform_data = &scif2_platform_data,
82 },
83};
84
85static struct plat_sci_port scif3_platform_data = {
86 .scscr = SCSCR_REIE | SCSCR_CKE1,
87 .type = PORT_SCIF,
88 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
89};
90
91static struct resource scif3_resources[] = {
92 DEFINE_RES_MEM(0xffed0000, 0x100),
93 DEFINE_RES_IRQ(evt2irq(0x9a0)),
94};
95
96static struct platform_device scif3_device = {
97 .name = "sh-sci",
98 .id = 3,
99 .resource = scif3_resources,
100 .num_resources = ARRAY_SIZE(scif3_resources),
101 .dev = {
102 .platform_data = &scif3_platform_data,
103 },
104};
105
106static struct plat_sci_port scif4_platform_data = {
107 .scscr = SCSCR_REIE | SCSCR_CKE1,
108 .type = PORT_SCIF,
109 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
110};
111
112static struct resource scif4_resources[] = {
113 DEFINE_RES_MEM(0xffee0000, 0x100),
114 DEFINE_RES_IRQ(evt2irq(0x9c0)),
115};
116
117static struct platform_device scif4_device = {
118 .name = "sh-sci",
119 .id = 4,
120 .resource = scif4_resources,
121 .num_resources = ARRAY_SIZE(scif4_resources),
122 .dev = {
123 .platform_data = &scif4_platform_data,
124 },
125};
126
127static struct plat_sci_port scif5_platform_data = {
128 .scscr = SCSCR_REIE | SCSCR_CKE1,
129 .type = PORT_SCIF,
130 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
131};
132
133static struct resource scif5_resources[] = {
134 DEFINE_RES_MEM(0xffef0000, 0x100),
135 DEFINE_RES_IRQ(evt2irq(0x9e0)),
136};
137
138static struct platform_device scif5_device = {
139 .name = "sh-sci",
140 .id = 5,
141 .resource = scif5_resources,
142 .num_resources = ARRAY_SIZE(scif5_resources),
143 .dev = {
144 .platform_data = &scif5_platform_data,
145 },
146};
147
148static struct sh_timer_config tmu0_platform_data = {
149 .channels_mask = 7,
150};
151
152static struct resource tmu0_resources[] = {
153 DEFINE_RES_MEM(0xffd80000, 0x30),
154 DEFINE_RES_IRQ(evt2irq(0x580)),
155 DEFINE_RES_IRQ(evt2irq(0x5a0)),
156 DEFINE_RES_IRQ(evt2irq(0x5c0)),
157};
158
159static struct platform_device tmu0_device = {
160 .name = "sh-tmu",
161 .id = 0,
162 .dev = {
163 .platform_data = &tmu0_platform_data,
164 },
165 .resource = tmu0_resources,
166 .num_resources = ARRAY_SIZE(tmu0_resources),
167};
168
169static struct sh_timer_config tmu1_platform_data = {
170 .channels_mask = 7,
171};
172
173static struct resource tmu1_resources[] = {
174 DEFINE_RES_MEM(0xffdc0000, 0x2c),
175 DEFINE_RES_IRQ(evt2irq(0xe00)),
176 DEFINE_RES_IRQ(evt2irq(0xe20)),
177 DEFINE_RES_IRQ(evt2irq(0xe40)),
178};
179
180static struct platform_device tmu1_device = {
181 .name = "sh-tmu",
182 .id = 1,
183 .dev = {
184 .platform_data = &tmu1_platform_data,
185 },
186 .resource = tmu1_resources,
187 .num_resources = ARRAY_SIZE(tmu1_resources),
188};
189
190
191static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
192 {
193 .offset = 0,
194 .dmars = 0,
195 .dmars_bit = 0,
196 }, {
197 .offset = 0x10,
198 .dmars = 0,
199 .dmars_bit = 8,
200 }, {
201 .offset = 0x20,
202 .dmars = 4,
203 .dmars_bit = 0,
204 }, {
205 .offset = 0x30,
206 .dmars = 4,
207 .dmars_bit = 8,
208 }, {
209 .offset = 0x50,
210 .dmars = 8,
211 .dmars_bit = 0,
212 }, {
213 .offset = 0x60,
214 .dmars = 8,
215 .dmars_bit = 8,
216 }
217};
218
219static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
220 {
221 .offset = 0,
222 }, {
223 .offset = 0x10,
224 }, {
225 .offset = 0x20,
226 }, {
227 .offset = 0x30,
228 }, {
229 .offset = 0x50,
230 }, {
231 .offset = 0x60,
232 }
233};
234
235static const unsigned int ts_shift[] = TS_SHIFT;
236
237static struct sh_dmae_pdata dma0_platform_data = {
238 .channel = sh7785_dmae0_channels,
239 .channel_num = ARRAY_SIZE(sh7785_dmae0_channels),
240 .ts_low_shift = CHCR_TS_LOW_SHIFT,
241 .ts_low_mask = CHCR_TS_LOW_MASK,
242 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
243 .ts_high_mask = CHCR_TS_HIGH_MASK,
244 .ts_shift = ts_shift,
245 .ts_shift_num = ARRAY_SIZE(ts_shift),
246 .dmaor_init = DMAOR_INIT,
247};
248
249static struct sh_dmae_pdata dma1_platform_data = {
250 .channel = sh7785_dmae1_channels,
251 .channel_num = ARRAY_SIZE(sh7785_dmae1_channels),
252 .ts_low_shift = CHCR_TS_LOW_SHIFT,
253 .ts_low_mask = CHCR_TS_LOW_MASK,
254 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
255 .ts_high_mask = CHCR_TS_HIGH_MASK,
256 .ts_shift = ts_shift,
257 .ts_shift_num = ARRAY_SIZE(ts_shift),
258 .dmaor_init = DMAOR_INIT,
259};
260
261static struct resource sh7785_dmae0_resources[] = {
262 [0] = {
263
264 .start = 0xfc808020,
265 .end = 0xfc80808f,
266 .flags = IORESOURCE_MEM,
267 },
268 [1] = {
269
270 .start = 0xfc809000,
271 .end = 0xfc80900b,
272 .flags = IORESOURCE_MEM,
273 },
274 {
275
276
277
278
279 .name = "error_irq",
280 .start = evt2irq(0x620),
281 .end = evt2irq(0x620),
282 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
283 },
284};
285
286static struct resource sh7785_dmae1_resources[] = {
287 [0] = {
288
289 .start = 0xfcc08020,
290 .end = 0xfcc0808f,
291 .flags = IORESOURCE_MEM,
292 },
293
294 {
295
296
297
298
299 .name = "error_irq",
300 .start = evt2irq(0x880),
301 .end = evt2irq(0x880),
302 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
303 },
304};
305
306static struct platform_device dma0_device = {
307 .name = "sh-dma-engine",
308 .id = 0,
309 .resource = sh7785_dmae0_resources,
310 .num_resources = ARRAY_SIZE(sh7785_dmae0_resources),
311 .dev = {
312 .platform_data = &dma0_platform_data,
313 },
314};
315
316static struct platform_device dma1_device = {
317 .name = "sh-dma-engine",
318 .id = 1,
319 .resource = sh7785_dmae1_resources,
320 .num_resources = ARRAY_SIZE(sh7785_dmae1_resources),
321 .dev = {
322 .platform_data = &dma1_platform_data,
323 },
324};
325
326static struct platform_device *sh7785_devices[] __initdata = {
327 &scif0_device,
328 &scif1_device,
329 &scif2_device,
330 &scif3_device,
331 &scif4_device,
332 &scif5_device,
333 &tmu0_device,
334 &tmu1_device,
335 &dma0_device,
336 &dma1_device,
337};
338
339static int __init sh7785_devices_setup(void)
340{
341 return platform_add_devices(sh7785_devices,
342 ARRAY_SIZE(sh7785_devices));
343}
344arch_initcall(sh7785_devices_setup);
345
346static struct platform_device *sh7785_early_devices[] __initdata = {
347 &scif0_device,
348 &scif1_device,
349 &scif2_device,
350 &scif3_device,
351 &scif4_device,
352 &scif5_device,
353 &tmu0_device,
354 &tmu1_device,
355};
356
357void __init plat_early_device_setup(void)
358{
359 early_platform_add_devices(sh7785_early_devices,
360 ARRAY_SIZE(sh7785_early_devices));
361}
362
363enum {
364 UNUSED = 0,
365
366
367
368 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
369 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
370 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
371 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
372
373 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
374 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
375 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
376 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
377
378 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
379 WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
380 HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
381 SCIF2, SCIF3, SCIF4, SCIF5,
382 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
383 SIOF, MMCIF, DU, GDTA,
384 TMU3, TMU4, TMU5,
385 SSI0, SSI1,
386 HAC0, HAC1,
387 FLCTL, GPIO,
388
389
390
391 TMU012, TMU345
392};
393
394static struct intc_vect vectors[] __initdata = {
395 INTC_VECT(WDT, 0x560),
396 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
397 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
398 INTC_VECT(HUDI, 0x600),
399 INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
400 INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
401 INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
402 INTC_VECT(DMAC0, 0x6e0),
403 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
404 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
405 INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
406 INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
407 INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
408 INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
409 INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
410 INTC_VECT(DMAC1, 0x940),
411 INTC_VECT(HSPI, 0x960),
412 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
413 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
414 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
415 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
416 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
417 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
418 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
419 INTC_VECT(SIOF, 0xc00),
420 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
421 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
422 INTC_VECT(DU, 0xd80),
423 INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
424 INTC_VECT(GDTA, 0xde0),
425 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
426 INTC_VECT(TMU5, 0xe40),
427 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
428 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
429 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
430 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
431 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
432 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
433};
434
435static struct intc_group groups[] __initdata = {
436 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
437 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
438};
439
440static struct intc_mask_reg mask_registers[] __initdata = {
441 { 0xffd00044, 0xffd00064, 32,
442 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
443
444 { 0xffd40080, 0xffd40084, 32,
445 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
446 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
447 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
448 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
449 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
450 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
451 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
452 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
453
454 { 0xffd40038, 0xffd4003c, 32,
455 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
456 FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
457 PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
458 SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
459};
460
461static struct intc_prio_reg prio_registers[] __initdata = {
462 { 0xffd00010, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
463 IRQ4, IRQ5, IRQ6, IRQ7 } },
464 { 0xffd40000, 0, 32, 8, { TMU0, TMU1,
465 TMU2, TMU2_TICPI } },
466 { 0xffd40004, 0, 32, 8, { TMU3, TMU4, TMU5, } },
467 { 0xffd40008, 0, 32, 8, { SCIF0, SCIF1,
468 SCIF2, SCIF3 } },
469 { 0xffd4000c, 0, 32, 8, { SCIF4, SCIF5, WDT, } },
470 { 0xffd40010, 0, 32, 8, { HUDI, DMAC0, DMAC1, } },
471 { 0xffd40014, 0, 32, 8, { HAC0, HAC1,
472 PCISERR, PCIINTA } },
473 { 0xffd40018, 0, 32, 8, { PCIINTB, PCIINTC,
474 PCIINTD, PCIC5 } },
475 { 0xffd4001c, 0, 32, 8, { SIOF, HSPI, MMCIF, } },
476 { 0xffd40020, 0, 32, 8, { FLCTL, GPIO, SSI0, SSI1, } },
477 { 0xffd40024, 0, 32, 8, { DU, GDTA, } },
478};
479
480static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
481 mask_registers, prio_registers, NULL);
482
483
484
485static struct intc_vect vectors_irq0123[] __initdata = {
486 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
487 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
488};
489
490static struct intc_vect vectors_irq4567[] __initdata = {
491 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
492 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
493};
494
495static struct intc_sense_reg sense_registers[] __initdata = {
496 { 0xffd0001c, 32, 2, { IRQ0, IRQ1, IRQ2, IRQ3,
497 IRQ4, IRQ5, IRQ6, IRQ7 } },
498};
499
500static struct intc_mask_reg ack_registers[] __initdata = {
501 { 0xffd00024, 0, 32,
502 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
503};
504
505static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
506 vectors_irq0123, NULL, mask_registers,
507 prio_registers, sense_registers, ack_registers);
508
509static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
510 vectors_irq4567, NULL, mask_registers,
511 prio_registers, sense_registers, ack_registers);
512
513
514
515static struct intc_vect vectors_irl0123[] __initdata = {
516 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
517 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
518 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
519 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
520 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
521 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
522 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
523 INTC_VECT(IRL0_HHHL, 0x3c0),
524};
525
526static struct intc_vect vectors_irl4567[] __initdata = {
527 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
528 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
529 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
530 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
531 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
532 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
533 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
534 INTC_VECT(IRL4_HHHL, 0xcc0),
535};
536
537static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
538 NULL, mask_registers, NULL, NULL);
539
540static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
541 NULL, mask_registers, NULL, NULL);
542
543#define INTC_ICR0 0xffd00000
544#define INTC_INTMSK0 0xffd00044
545#define INTC_INTMSK1 0xffd00048
546#define INTC_INTMSK2 0xffd40080
547#define INTC_INTMSKCLR1 0xffd00068
548#define INTC_INTMSKCLR2 0xffd40084
549
550void __init plat_irq_setup(void)
551{
552
553 __raw_writel(0xff000000, INTC_INTMSK0);
554
555
556 __raw_writel(0xc0000000, INTC_INTMSK1);
557 __raw_writel(0xfffefffe, INTC_INTMSK2);
558
559
560 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
561
562
563 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
564
565 register_intc_controller(&intc_desc);
566}
567
568void __init plat_irq_setup_pins(int mode)
569{
570 switch (mode) {
571 case IRQ_MODE_IRQ7654:
572
573 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
574 register_intc_controller(&intc_desc_irq4567);
575 break;
576 case IRQ_MODE_IRQ3210:
577
578 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
579 register_intc_controller(&intc_desc_irq0123);
580 break;
581 case IRQ_MODE_IRL7654:
582
583 __raw_writel(0x40000000, INTC_INTMSKCLR1);
584 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
585 break;
586 case IRQ_MODE_IRL3210:
587
588 __raw_writel(0x80000000, INTC_INTMSKCLR1);
589 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
590 break;
591 case IRQ_MODE_IRL7654_MASK:
592
593 __raw_writel(0x40000000, INTC_INTMSKCLR1);
594 register_intc_controller(&intc_desc_irl4567);
595 break;
596 case IRQ_MODE_IRL3210_MASK:
597
598 __raw_writel(0x80000000, INTC_INTMSKCLR1);
599 register_intc_controller(&intc_desc_irl0123);
600 break;
601 default:
602 BUG();
603 }
604}
605
606void __init plat_mem_setup(void)
607{
608
609 setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
610}
611
