LXR linux/arch/x86/include/asm/intel_pmc

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef _ASM_X86_INTEL_PMC_IPC_H_
   3#define  _ASM_X86_INTEL_PMC_IPC_H_
   4
   5/* Commands */
   6#define PMC_IPC_PMIC_ACCESS             0xFF
   7#define         PMC_IPC_PMIC_ACCESS_READ        0x0
   8#define         PMC_IPC_PMIC_ACCESS_WRITE       0x1
   9#define PMC_IPC_USB_PWR_CTRL            0xF0
  10#define PMC_IPC_PMIC_BLACKLIST_SEL      0xEF
  11#define PMC_IPC_PHY_CONFIG              0xEE
  12#define PMC_IPC_NORTHPEAK_CTRL          0xED
  13#define PMC_IPC_PM_DEBUG                0xEC
  14#define PMC_IPC_PMC_TELEMTRY            0xEB
  15#define PMC_IPC_PMC_FW_MSG_CTRL         0xEA
  16
  17/* IPC return code */
  18#define IPC_ERR_NONE                    0
  19#define IPC_ERR_CMD_NOT_SUPPORTED       1
  20#define IPC_ERR_CMD_NOT_SERVICED        2
  21#define IPC_ERR_UNABLE_TO_SERVICE       3
  22#define IPC_ERR_CMD_INVALID             4
  23#define IPC_ERR_CMD_FAILED              5
  24#define IPC_ERR_EMSECURITY              6
  25#define IPC_ERR_UNSIGNEDKERNEL          7
  26
  27/* GCR reg offsets from gcr base*/
  28#define PMC_GCR_PMC_CFG_REG             0x08
  29#define PMC_GCR_TELEM_DEEP_S0IX_REG     0x78
  30#define PMC_GCR_TELEM_SHLW_S0IX_REG     0x80
  31
  32#if IS_ENABLED(CONFIG_INTEL_PMC_IPC)
  33
  34int intel_pmc_ipc_simple_command(int cmd, int sub);
  35int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
  36                u32 *out, u32 outlen, u32 dptr, u32 sptr);
  37int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
  38                u32 *out, u32 outlen);
  39int intel_pmc_s0ix_counter_read(u64 *data);
  40int intel_pmc_gcr_read(u32 offset, u32 *data);
  41int intel_pmc_gcr_write(u32 offset, u32 data);
  42int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val);
  43
  44#else
  45
  46static inline int intel_pmc_ipc_simple_command(int cmd, int sub)
  47{
  48        return -EINVAL;
  49}
  50
  51static inline int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
  52                u32 *out, u32 outlen, u32 dptr, u32 sptr)
  53{
  54        return -EINVAL;
  55}
  56
  57static inline int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
  58                u32 *out, u32 outlen)
  59{
  60        return -EINVAL;
  61}
  62
  63static inline int intel_pmc_s0ix_counter_read(u64 *data)
  64{
  65        return -EINVAL;
  66}
  67
  68static inline int intel_pmc_gcr_read(u32 offset, u32 *data)
  69{
  70        return -EINVAL;
  71}
  72
  73static inline int intel_pmc_gcr_write(u32 offset, u32 data)
  74{
  75        return -EINVAL;
  76}
  77
  78static inline int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)
  79{
  80        return -EINVAL;
  81}
  82
  83#endif /*CONFIG_INTEL_PMC_IPC*/
  84
  85#endif
  86