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11#include <linux/bug.h>
12#include <linux/clk.h>
13#include <linux/clk-provider.h>
14#include <linux/device.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/slab.h>
19
20#include "renesas-cpg-mssr.h"
21#include "rcar-gen2-cpg.h"
22
23#define CPG_FRQCRB 0x0004
24#define CPG_FRQCRB_KICK BIT(31)
25#define CPG_SDCKCR 0x0074
26#define CPG_PLL0CR 0x00d8
27#define CPG_PLL0CR_STC_SHIFT 24
28#define CPG_PLL0CR_STC_MASK (0x7f << CPG_PLL0CR_STC_SHIFT)
29#define CPG_FRQCRC 0x00e0
30#define CPG_FRQCRC_ZFC_SHIFT 8
31#define CPG_FRQCRC_ZFC_MASK (0x1f << CPG_FRQCRC_ZFC_SHIFT)
32#define CPG_ADSPCKCR 0x025c
33#define CPG_RCANCKCR 0x0270
34
35static spinlock_t cpg_lock;
36
37
38
39
40
41
42
43
44
45
46
47struct cpg_z_clk {
48 struct clk_hw hw;
49 void __iomem *reg;
50 void __iomem *kick_reg;
51};
52
53#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
54
55static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
56 unsigned long parent_rate)
57{
58 struct cpg_z_clk *zclk = to_z_clk(hw);
59 unsigned int mult;
60 unsigned int val;
61
62 val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT;
63 mult = 32 - val;
64
65 return div_u64((u64)parent_rate * mult, 32);
66}
67
68static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
69 unsigned long *parent_rate)
70{
71 unsigned long prate = *parent_rate;
72 unsigned int mult;
73
74 if (!prate)
75 prate = 1;
76
77 mult = div_u64((u64)rate * 32, prate);
78 mult = clamp(mult, 1U, 32U);
79
80 return *parent_rate / 32 * mult;
81}
82
83static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
84 unsigned long parent_rate)
85{
86 struct cpg_z_clk *zclk = to_z_clk(hw);
87 unsigned int mult;
88 u32 val, kick;
89 unsigned int i;
90
91 mult = div_u64((u64)rate * 32, parent_rate);
92 mult = clamp(mult, 1U, 32U);
93
94 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
95 return -EBUSY;
96
97 val = readl(zclk->reg);
98 val &= ~CPG_FRQCRC_ZFC_MASK;
99 val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
100 writel(val, zclk->reg);
101
102
103
104
105
106 kick = readl(zclk->kick_reg);
107 kick |= CPG_FRQCRB_KICK;
108 writel(kick, zclk->kick_reg);
109
110
111
112
113
114
115
116
117
118
119 for (i = 1000; i; i--) {
120 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
121 return 0;
122
123 cpu_relax();
124 }
125
126 return -ETIMEDOUT;
127}
128
129static const struct clk_ops cpg_z_clk_ops = {
130 .recalc_rate = cpg_z_clk_recalc_rate,
131 .round_rate = cpg_z_clk_round_rate,
132 .set_rate = cpg_z_clk_set_rate,
133};
134
135static struct clk * __init cpg_z_clk_register(const char *name,
136 const char *parent_name,
137 void __iomem *base)
138{
139 struct clk_init_data init;
140 struct cpg_z_clk *zclk;
141 struct clk *clk;
142
143 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
144 if (!zclk)
145 return ERR_PTR(-ENOMEM);
146
147 init.name = name;
148 init.ops = &cpg_z_clk_ops;
149 init.flags = 0;
150 init.parent_names = &parent_name;
151 init.num_parents = 1;
152
153 zclk->reg = base + CPG_FRQCRC;
154 zclk->kick_reg = base + CPG_FRQCRB;
155 zclk->hw.init = &init;
156
157 clk = clk_register(NULL, &zclk->hw);
158 if (IS_ERR(clk))
159 kfree(zclk);
160
161 return clk;
162}
163
164static struct clk * __init cpg_rcan_clk_register(const char *name,
165 const char *parent_name,
166 void __iomem *base)
167{
168 struct clk_fixed_factor *fixed;
169 struct clk_gate *gate;
170 struct clk *clk;
171
172 fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
173 if (!fixed)
174 return ERR_PTR(-ENOMEM);
175
176 fixed->mult = 1;
177 fixed->div = 6;
178
179 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
180 if (!gate) {
181 kfree(fixed);
182 return ERR_PTR(-ENOMEM);
183 }
184
185 gate->reg = base + CPG_RCANCKCR;
186 gate->bit_idx = 8;
187 gate->flags = CLK_GATE_SET_TO_DISABLE;
188 gate->lock = &cpg_lock;
189
190 clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
191 &fixed->hw, &clk_fixed_factor_ops,
192 &gate->hw, &clk_gate_ops, 0);
193 if (IS_ERR(clk)) {
194 kfree(gate);
195 kfree(fixed);
196 }
197
198 return clk;
199}
200
201
202static const struct clk_div_table cpg_adsp_div_table[] = {
203 { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 },
204 { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
205 { 10, 36 }, { 11, 48 }, { 0, 0 },
206};
207
208static struct clk * __init cpg_adsp_clk_register(const char *name,
209 const char *parent_name,
210 void __iomem *base)
211{
212 struct clk_divider *div;
213 struct clk_gate *gate;
214 struct clk *clk;
215
216 div = kzalloc(sizeof(*div), GFP_KERNEL);
217 if (!div)
218 return ERR_PTR(-ENOMEM);
219
220 div->reg = base + CPG_ADSPCKCR;
221 div->width = 4;
222 div->table = cpg_adsp_div_table;
223 div->lock = &cpg_lock;
224
225 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
226 if (!gate) {
227 kfree(div);
228 return ERR_PTR(-ENOMEM);
229 }
230
231 gate->reg = base + CPG_ADSPCKCR;
232 gate->bit_idx = 8;
233 gate->flags = CLK_GATE_SET_TO_DISABLE;
234 gate->lock = &cpg_lock;
235
236 clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
237 &div->hw, &clk_divider_ops,
238 &gate->hw, &clk_gate_ops, 0);
239 if (IS_ERR(clk)) {
240 kfree(gate);
241 kfree(div);
242 }
243
244 return clk;
245}
246
247
248static const struct clk_div_table cpg_sdh_div_table[] = {
249 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
250 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
251 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
252};
253
254static const struct clk_div_table cpg_sd01_div_table[] = {
255 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
256 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
257 { 0, 0 },
258};
259
260static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata;
261static unsigned int cpg_pll0_div __initdata;
262static u32 cpg_mode __initdata;
263
264struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
265 const struct cpg_core_clk *core,
266 const struct cpg_mssr_info *info,
267 struct clk **clks,
268 void __iomem *base)
269{
270 const struct clk_div_table *table = NULL;
271 const struct clk *parent;
272 const char *parent_name;
273 unsigned int mult = 1;
274 unsigned int div = 1;
275 unsigned int shift;
276
277 parent = clks[core->parent];
278 if (IS_ERR(parent))
279 return ERR_CAST(parent);
280
281 parent_name = __clk_get_name(parent);
282
283 switch (core->type) {
284
285 case CLK_TYPE_GEN2_MAIN:
286 div = cpg_pll_config->extal_div;
287 break;
288
289 case CLK_TYPE_GEN2_PLL0:
290
291
292
293
294
295
296 mult = cpg_pll_config->pll0_mult;
297 div = cpg_pll0_div;
298 if (!mult) {
299 u32 pll0cr = readl(base + CPG_PLL0CR);
300
301 mult = (((pll0cr & CPG_PLL0CR_STC_MASK) >>
302 CPG_PLL0CR_STC_SHIFT) + 1) * 2;
303 }
304 break;
305
306 case CLK_TYPE_GEN2_PLL1:
307 mult = cpg_pll_config->pll1_mult / 2;
308 break;
309
310 case CLK_TYPE_GEN2_PLL3:
311 mult = cpg_pll_config->pll3_mult;
312 break;
313
314 case CLK_TYPE_GEN2_Z:
315 return cpg_z_clk_register(core->name, parent_name, base);
316
317 case CLK_TYPE_GEN2_LB:
318 div = cpg_mode & BIT(18) ? 36 : 24;
319 break;
320
321 case CLK_TYPE_GEN2_ADSP:
322 return cpg_adsp_clk_register(core->name, parent_name, base);
323
324 case CLK_TYPE_GEN2_SDH:
325 table = cpg_sdh_div_table;
326 shift = 8;
327 break;
328
329 case CLK_TYPE_GEN2_SD0:
330 table = cpg_sd01_div_table;
331 shift = 4;
332 break;
333
334 case CLK_TYPE_GEN2_SD1:
335 table = cpg_sd01_div_table;
336 shift = 0;
337 break;
338
339 case CLK_TYPE_GEN2_QSPI:
340 div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) ?
341 8 : 10;
342 break;
343
344 case CLK_TYPE_GEN2_RCAN:
345 return cpg_rcan_clk_register(core->name, parent_name, base);
346
347 default:
348 return ERR_PTR(-EINVAL);
349 }
350
351 if (!table)
352 return clk_register_fixed_factor(NULL, core->name, parent_name,
353 0, mult, div);
354 else
355 return clk_register_divider_table(NULL, core->name,
356 parent_name, 0,
357 base + CPG_SDCKCR, shift, 4,
358 0, table, &cpg_lock);
359}
360
361int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
362 unsigned int pll0_div, u32 mode)
363{
364 cpg_pll_config = config;
365 cpg_pll0_div = pll0_div;
366 cpg_mode = mode;
367
368 spin_lock_init(&cpg_lock);
369
370 return 0;
371}
372
