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35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/netdevice.h>
38#include <linux/etherdevice.h>
39#include <linux/ip.h>
40#include <linux/tcp.h>
41#include <linux/if_vlan.h>
42
43#include "i40iw.h"
44
45
46
47
48
49u32 i40iw_initialize_hw_resources(struct i40iw_device *iwdev)
50{
51 unsigned long num_pds;
52 u32 resources_size;
53 u32 max_mr;
54 u32 max_qp;
55 u32 max_cq;
56 u32 arp_table_size;
57 u32 mrdrvbits;
58 void *resource_ptr;
59
60 max_qp = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_QP].cnt;
61 max_cq = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt;
62 max_mr = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_MR].cnt;
63 arp_table_size = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_ARP].cnt;
64 iwdev->max_cqe = 0xFFFFF;
65 num_pds = I40IW_MAX_PDS;
66 resources_size = sizeof(struct i40iw_arp_entry) * arp_table_size;
67 resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_qp);
68 resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_mr);
69 resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_cq);
70 resources_size += sizeof(unsigned long) * BITS_TO_LONGS(num_pds);
71 resources_size += sizeof(unsigned long) * BITS_TO_LONGS(arp_table_size);
72 resources_size += sizeof(struct i40iw_qp **) * max_qp;
73 iwdev->mem_resources = kzalloc(resources_size, GFP_KERNEL);
74
75 if (!iwdev->mem_resources)
76 return -ENOMEM;
77
78 iwdev->max_qp = max_qp;
79 iwdev->max_mr = max_mr;
80 iwdev->max_cq = max_cq;
81 iwdev->max_pd = num_pds;
82 iwdev->arp_table_size = arp_table_size;
83 iwdev->arp_table = (struct i40iw_arp_entry *)iwdev->mem_resources;
84 resource_ptr = iwdev->mem_resources + (sizeof(struct i40iw_arp_entry) * arp_table_size);
85
86 iwdev->device_cap_flags = IB_DEVICE_LOCAL_DMA_LKEY |
87 IB_DEVICE_MEM_WINDOW | IB_DEVICE_MEM_MGT_EXTENSIONS;
88
89 iwdev->allocated_qps = resource_ptr;
90 iwdev->allocated_cqs = &iwdev->allocated_qps[BITS_TO_LONGS(max_qp)];
91 iwdev->allocated_mrs = &iwdev->allocated_cqs[BITS_TO_LONGS(max_cq)];
92 iwdev->allocated_pds = &iwdev->allocated_mrs[BITS_TO_LONGS(max_mr)];
93 iwdev->allocated_arps = &iwdev->allocated_pds[BITS_TO_LONGS(num_pds)];
94 iwdev->qp_table = (struct i40iw_qp **)(&iwdev->allocated_arps[BITS_TO_LONGS(arp_table_size)]);
95 set_bit(0, iwdev->allocated_mrs);
96 set_bit(0, iwdev->allocated_qps);
97 set_bit(0, iwdev->allocated_cqs);
98 set_bit(0, iwdev->allocated_pds);
99 set_bit(0, iwdev->allocated_arps);
100
101
102 set_bit(1, iwdev->allocated_qps);
103 set_bit(1, iwdev->allocated_cqs);
104 set_bit(1, iwdev->allocated_pds);
105 set_bit(2, iwdev->allocated_cqs);
106 set_bit(2, iwdev->allocated_pds);
107
108 spin_lock_init(&iwdev->resource_lock);
109 spin_lock_init(&iwdev->qptable_lock);
110
111 mrdrvbits = 24 - max(get_count_order(iwdev->max_mr), 14);
112 iwdev->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits));
113 return 0;
114}
115
116
117
118
119
120
121
122static void i40iw_cqp_ce_handler(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq, bool arm)
123{
124 struct i40iw_cqp_request *cqp_request;
125 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
126 u32 cqe_count = 0;
127 struct i40iw_ccq_cqe_info info;
128 int ret;
129
130 do {
131 memset(&info, 0, sizeof(info));
132 ret = dev->ccq_ops->ccq_get_cqe_info(cq, &info);
133 if (ret)
134 break;
135 cqp_request = (struct i40iw_cqp_request *)(unsigned long)info.scratch;
136 if (info.error)
137 i40iw_pr_err("opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n",
138 info.op_code, info.maj_err_code, info.min_err_code);
139 if (cqp_request) {
140 cqp_request->compl_info.maj_err_code = info.maj_err_code;
141 cqp_request->compl_info.min_err_code = info.min_err_code;
142 cqp_request->compl_info.op_ret_val = info.op_ret_val;
143 cqp_request->compl_info.error = info.error;
144
145 if (cqp_request->waiting) {
146 cqp_request->request_done = true;
147 wake_up(&cqp_request->waitq);
148 i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
149 } else {
150 if (cqp_request->callback_fcn)
151 cqp_request->callback_fcn(cqp_request, 1);
152 i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
153 }
154 }
155
156 cqe_count++;
157 } while (1);
158
159 if (arm && cqe_count) {
160 i40iw_process_bh(dev);
161 dev->ccq_ops->ccq_arm(cq);
162 }
163}
164
165
166
167
168
169
170static void i40iw_iwarp_ce_handler(struct i40iw_device *iwdev,
171 struct i40iw_sc_cq *iwcq)
172{
173 struct i40iw_cq *i40iwcq = iwcq->back_cq;
174
175 if (i40iwcq->ibcq.comp_handler)
176 i40iwcq->ibcq.comp_handler(&i40iwcq->ibcq,
177 i40iwcq->ibcq.cq_context);
178}
179
180
181
182
183
184
185static void i40iw_puda_ce_handler(struct i40iw_device *iwdev,
186 struct i40iw_sc_cq *cq)
187{
188 struct i40iw_sc_dev *dev = (struct i40iw_sc_dev *)&iwdev->sc_dev;
189 enum i40iw_status_code status;
190 u32 compl_error;
191
192 do {
193 status = i40iw_puda_poll_completion(dev, cq, &compl_error);
194 if (status == I40IW_ERR_QUEUE_EMPTY)
195 break;
196 if (status) {
197 i40iw_pr_err("puda status = %d\n", status);
198 break;
199 }
200 if (compl_error) {
201 i40iw_pr_err("puda compl_err =0x%x\n", compl_error);
202 break;
203 }
204 } while (1);
205
206 dev->ccq_ops->ccq_arm(cq);
207}
208
209
210
211
212
213
214void i40iw_process_ceq(struct i40iw_device *iwdev, struct i40iw_ceq *ceq)
215{
216 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
217 struct i40iw_sc_ceq *sc_ceq;
218 struct i40iw_sc_cq *cq;
219 bool arm = true;
220
221 sc_ceq = &ceq->sc_ceq;
222 do {
223 cq = dev->ceq_ops->process_ceq(dev, sc_ceq);
224 if (!cq)
225 break;
226
227 if (cq->cq_type == I40IW_CQ_TYPE_CQP)
228 i40iw_cqp_ce_handler(iwdev, cq, arm);
229 else if (cq->cq_type == I40IW_CQ_TYPE_IWARP)
230 i40iw_iwarp_ce_handler(iwdev, cq);
231 else if ((cq->cq_type == I40IW_CQ_TYPE_ILQ) ||
232 (cq->cq_type == I40IW_CQ_TYPE_IEQ))
233 i40iw_puda_ce_handler(iwdev, cq);
234 } while (1);
235}
236
237
238
239
240
241
242
243
244
245void i40iw_next_iw_state(struct i40iw_qp *iwqp,
246 u8 state,
247 u8 del_hash,
248 u8 term,
249 u8 termlen)
250{
251 struct i40iw_modify_qp_info info;
252
253 memset(&info, 0, sizeof(info));
254 info.next_iwarp_state = state;
255 info.remove_hash_idx = del_hash;
256 info.cq_num_valid = true;
257 info.arp_cache_idx_valid = true;
258 info.dont_send_term = true;
259 info.dont_send_fin = true;
260 info.termlen = termlen;
261
262 if (term & I40IWQP_TERM_SEND_TERM_ONLY)
263 info.dont_send_term = false;
264 if (term & I40IWQP_TERM_SEND_FIN_ONLY)
265 info.dont_send_fin = false;
266 if (iwqp->sc_qp.term_flags && (state == I40IW_QP_STATE_ERROR))
267 info.reset_tcp_conn = true;
268 iwqp->hw_iwarp_state = state;
269 i40iw_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0);
270}
271
272
273
274
275
276void i40iw_process_aeq(struct i40iw_device *iwdev)
277{
278 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
279 struct i40iw_aeq *aeq = &iwdev->aeq;
280 struct i40iw_sc_aeq *sc_aeq = &aeq->sc_aeq;
281 struct i40iw_aeqe_info aeinfo;
282 struct i40iw_aeqe_info *info = &aeinfo;
283 int ret;
284 struct i40iw_qp *iwqp = NULL;
285 struct i40iw_sc_cq *cq = NULL;
286 struct i40iw_cq *iwcq = NULL;
287 struct i40iw_sc_qp *qp = NULL;
288 struct i40iw_qp_host_ctx_info *ctx_info = NULL;
289 unsigned long flags;
290
291 u32 aeqcnt = 0;
292
293 if (!sc_aeq->size)
294 return;
295
296 do {
297 memset(info, 0, sizeof(*info));
298 ret = dev->aeq_ops->get_next_aeqe(sc_aeq, info);
299 if (ret)
300 break;
301
302 aeqcnt++;
303 i40iw_debug(dev, I40IW_DEBUG_AEQ,
304 "%s ae_id = 0x%x bool qp=%d qp_id = %d\n",
305 __func__, info->ae_id, info->qp, info->qp_cq_id);
306 if (info->qp) {
307 spin_lock_irqsave(&iwdev->qptable_lock, flags);
308 iwqp = iwdev->qp_table[info->qp_cq_id];
309 if (!iwqp) {
310 spin_unlock_irqrestore(&iwdev->qptable_lock, flags);
311 i40iw_debug(dev, I40IW_DEBUG_AEQ,
312 "%s qp_id %d is already freed\n",
313 __func__, info->qp_cq_id);
314 continue;
315 }
316 i40iw_add_ref(&iwqp->ibqp);
317 spin_unlock_irqrestore(&iwdev->qptable_lock, flags);
318 qp = &iwqp->sc_qp;
319 spin_lock_irqsave(&iwqp->lock, flags);
320 iwqp->hw_tcp_state = info->tcp_state;
321 iwqp->hw_iwarp_state = info->iwarp_state;
322 iwqp->last_aeq = info->ae_id;
323 spin_unlock_irqrestore(&iwqp->lock, flags);
324 ctx_info = &iwqp->ctx_info;
325 ctx_info->err_rq_idx_valid = true;
326 } else {
327 if (info->ae_id != I40IW_AE_CQ_OPERATION_ERROR)
328 continue;
329 }
330
331 switch (info->ae_id) {
332 case I40IW_AE_LLP_FIN_RECEIVED:
333 if (qp->term_flags)
334 continue;
335 if (atomic_inc_return(&iwqp->close_timer_started) == 1) {
336 iwqp->hw_tcp_state = I40IW_TCP_STATE_CLOSE_WAIT;
337 if ((iwqp->hw_tcp_state == I40IW_TCP_STATE_CLOSE_WAIT) &&
338 (iwqp->ibqp_state == IB_QPS_RTS)) {
339 i40iw_next_iw_state(iwqp,
340 I40IW_QP_STATE_CLOSING, 0, 0, 0);
341 i40iw_cm_disconn(iwqp);
342 }
343 iwqp->cm_id->add_ref(iwqp->cm_id);
344 i40iw_schedule_cm_timer(iwqp->cm_node,
345 (struct i40iw_puda_buf *)iwqp,
346 I40IW_TIMER_TYPE_CLOSE, 1, 0);
347 }
348 break;
349 case I40IW_AE_LLP_CLOSE_COMPLETE:
350 if (qp->term_flags)
351 i40iw_terminate_done(qp, 0);
352 else
353 i40iw_cm_disconn(iwqp);
354 break;
355 case I40IW_AE_RESET_SENT:
356 i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 1, 0, 0);
357 i40iw_cm_disconn(iwqp);
358 break;
359 case I40IW_AE_LLP_CONNECTION_RESET:
360 if (atomic_read(&iwqp->close_timer_started))
361 continue;
362 i40iw_cm_disconn(iwqp);
363 break;
364 case I40IW_AE_QP_SUSPEND_COMPLETE:
365 i40iw_qp_suspend_resume(dev, &iwqp->sc_qp, false);
366 break;
367 case I40IW_AE_TERMINATE_SENT:
368 i40iw_terminate_send_fin(qp);
369 break;
370 case I40IW_AE_LLP_TERMINATE_RECEIVED:
371 i40iw_terminate_received(qp, info);
372 break;
373 case I40IW_AE_CQ_OPERATION_ERROR:
374 i40iw_pr_err("Processing an iWARP related AE for CQ misc = 0x%04X\n",
375 info->ae_id);
376 cq = (struct i40iw_sc_cq *)(unsigned long)info->compl_ctx;
377 iwcq = (struct i40iw_cq *)cq->back_cq;
378
379 if (iwcq->ibcq.event_handler) {
380 struct ib_event ibevent;
381
382 ibevent.device = iwcq->ibcq.device;
383 ibevent.event = IB_EVENT_CQ_ERR;
384 ibevent.element.cq = &iwcq->ibcq;
385 iwcq->ibcq.event_handler(&ibevent, iwcq->ibcq.cq_context);
386 }
387 break;
388 case I40IW_AE_PRIV_OPERATION_DENIED:
389 case I40IW_AE_STAG_ZERO_INVALID:
390 case I40IW_AE_IB_RREQ_AND_Q1_FULL:
391 case I40IW_AE_DDP_UBE_INVALID_DDP_VERSION:
392 case I40IW_AE_DDP_UBE_INVALID_MO:
393 case I40IW_AE_DDP_UBE_INVALID_QN:
394 case I40IW_AE_DDP_NO_L_BIT:
395 case I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
396 case I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
397 case I40IW_AE_ROE_INVALID_RDMA_READ_REQUEST:
398 case I40IW_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
399 case I40IW_AE_INVALID_ARP_ENTRY:
400 case I40IW_AE_INVALID_TCP_OPTION_RCVD:
401 case I40IW_AE_STALE_ARP_ENTRY:
402 case I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR:
403 case I40IW_AE_LLP_SEGMENT_TOO_SMALL:
404 case I40IW_AE_LLP_SYN_RECEIVED:
405 case I40IW_AE_LLP_TOO_MANY_RETRIES:
406 case I40IW_AE_LLP_DOUBT_REACHABILITY:
407 case I40IW_AE_LCE_QP_CATASTROPHIC:
408 case I40IW_AE_LCE_FUNCTION_CATASTROPHIC:
409 case I40IW_AE_LCE_CQ_CATASTROPHIC:
410 case I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG:
411 case I40IW_AE_UDA_XMIT_IPADDR_MISMATCH:
412 ctx_info->err_rq_idx_valid = false;
413 default:
414 if (!info->sq && ctx_info->err_rq_idx_valid) {
415 ctx_info->err_rq_idx = info->wqe_idx;
416 ctx_info->tcp_info_valid = false;
417 ctx_info->iwarp_info_valid = false;
418 ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
419 iwqp->host_ctx.va,
420 ctx_info);
421 }
422 i40iw_terminate_connection(qp, info);
423 break;
424 }
425 if (info->qp)
426 i40iw_rem_ref(&iwqp->ibqp);
427 } while (1);
428
429 if (aeqcnt)
430 dev->aeq_ops->repost_aeq_entries(dev, aeqcnt);
431}
432
433
434
435
436
437
438
439int i40iw_manage_apbvt(struct i40iw_device *iwdev, u16 accel_local_port, bool add_port)
440{
441 struct i40iw_apbvt_info *info;
442 enum i40iw_status_code status;
443 struct i40iw_cqp_request *cqp_request;
444 struct cqp_commands_info *cqp_info;
445
446 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, add_port);
447 if (!cqp_request)
448 return -ENOMEM;
449
450 cqp_info = &cqp_request->info;
451 info = &cqp_info->in.u.manage_apbvt_entry.info;
452
453 memset(info, 0, sizeof(*info));
454 info->add = add_port;
455 info->port = cpu_to_le16(accel_local_port);
456
457 cqp_info->cqp_cmd = OP_MANAGE_APBVT_ENTRY;
458 cqp_info->post_sq = 1;
459 cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->cqp.sc_cqp;
460 cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request;
461 status = i40iw_handle_cqp_op(iwdev, cqp_request);
462 if (status)
463 i40iw_pr_err("CQP-OP Manage APBVT entry fail");
464 return status;
465}
466
467
468
469
470
471
472
473
474void i40iw_manage_arp_cache(struct i40iw_device *iwdev,
475 unsigned char *mac_addr,
476 u32 *ip_addr,
477 bool ipv4,
478 u32 action)
479{
480 struct i40iw_add_arp_cache_entry_info *info;
481 struct i40iw_cqp_request *cqp_request;
482 struct cqp_commands_info *cqp_info;
483 int arp_index;
484
485 arp_index = i40iw_arp_table(iwdev, ip_addr, ipv4, mac_addr, action);
486 if (arp_index == -1)
487 return;
488 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, false);
489 if (!cqp_request)
490 return;
491
492 cqp_info = &cqp_request->info;
493 if (action == I40IW_ARP_ADD) {
494 cqp_info->cqp_cmd = OP_ADD_ARP_CACHE_ENTRY;
495 info = &cqp_info->in.u.add_arp_cache_entry.info;
496 memset(info, 0, sizeof(*info));
497 info->arp_index = cpu_to_le16((u16)arp_index);
498 info->permanent = true;
499 ether_addr_copy(info->mac_addr, mac_addr);
500 cqp_info->in.u.add_arp_cache_entry.scratch = (uintptr_t)cqp_request;
501 cqp_info->in.u.add_arp_cache_entry.cqp = &iwdev->cqp.sc_cqp;
502 } else {
503 cqp_info->cqp_cmd = OP_DELETE_ARP_CACHE_ENTRY;
504 cqp_info->in.u.del_arp_cache_entry.scratch = (uintptr_t)cqp_request;
505 cqp_info->in.u.del_arp_cache_entry.cqp = &iwdev->cqp.sc_cqp;
506 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index;
507 }
508
509 cqp_info->in.u.add_arp_cache_entry.cqp = &iwdev->cqp.sc_cqp;
510 cqp_info->in.u.add_arp_cache_entry.scratch = (uintptr_t)cqp_request;
511 cqp_info->post_sq = 1;
512 if (i40iw_handle_cqp_op(iwdev, cqp_request))
513 i40iw_pr_err("CQP-OP Add/Del Arp Cache entry fail");
514}
515
516
517
518
519
520
521static void i40iw_send_syn_cqp_callback(struct i40iw_cqp_request *cqp_request, u32 send_ack)
522{
523 i40iw_send_syn(cqp_request->param, send_ack);
524}
525
526
527
528
529
530
531
532
533
534
535
536enum i40iw_status_code i40iw_manage_qhash(struct i40iw_device *iwdev,
537 struct i40iw_cm_info *cminfo,
538 enum i40iw_quad_entry_type etype,
539 enum i40iw_quad_hash_manage_type mtype,
540 void *cmnode,
541 bool wait)
542{
543 struct i40iw_qhash_table_info *info;
544 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
545 struct i40iw_sc_vsi *vsi = &iwdev->vsi;
546 enum i40iw_status_code status;
547 struct i40iw_cqp *iwcqp = &iwdev->cqp;
548 struct i40iw_cqp_request *cqp_request;
549 struct cqp_commands_info *cqp_info;
550
551 cqp_request = i40iw_get_cqp_request(iwcqp, wait);
552 if (!cqp_request)
553 return I40IW_ERR_NO_MEMORY;
554 cqp_info = &cqp_request->info;
555 info = &cqp_info->in.u.manage_qhash_table_entry.info;
556 memset(info, 0, sizeof(*info));
557
558 info->vsi = &iwdev->vsi;
559 info->manage = mtype;
560 info->entry_type = etype;
561 if (cminfo->vlan_id != 0xFFFF) {
562 info->vlan_valid = true;
563 info->vlan_id = cpu_to_le16(cminfo->vlan_id);
564 } else {
565 info->vlan_valid = false;
566 }
567
568 info->ipv4_valid = cminfo->ipv4;
569 info->user_pri = cminfo->user_pri;
570 ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr);
571 info->qp_num = cpu_to_le32(vsi->ilq->qp_id);
572 info->dest_port = cpu_to_le16(cminfo->loc_port);
573 info->dest_ip[0] = cpu_to_le32(cminfo->loc_addr[0]);
574 info->dest_ip[1] = cpu_to_le32(cminfo->loc_addr[1]);
575 info->dest_ip[2] = cpu_to_le32(cminfo->loc_addr[2]);
576 info->dest_ip[3] = cpu_to_le32(cminfo->loc_addr[3]);
577 if (etype == I40IW_QHASH_TYPE_TCP_ESTABLISHED) {
578 info->src_port = cpu_to_le16(cminfo->rem_port);
579 info->src_ip[0] = cpu_to_le32(cminfo->rem_addr[0]);
580 info->src_ip[1] = cpu_to_le32(cminfo->rem_addr[1]);
581 info->src_ip[2] = cpu_to_le32(cminfo->rem_addr[2]);
582 info->src_ip[3] = cpu_to_le32(cminfo->rem_addr[3]);
583 }
584 if (cmnode) {
585 cqp_request->callback_fcn = i40iw_send_syn_cqp_callback;
586 cqp_request->param = (void *)cmnode;
587 }
588
589 if (info->ipv4_valid)
590 i40iw_debug(dev, I40IW_DEBUG_CM,
591 "%s:%s IP=%pI4, port=%d, mac=%pM, vlan_id=%d\n",
592 __func__, (!mtype) ? "DELETE" : "ADD",
593 info->dest_ip,
594 info->dest_port, info->mac_addr, cminfo->vlan_id);
595 else
596 i40iw_debug(dev, I40IW_DEBUG_CM,
597 "%s:%s IP=%pI6, port=%d, mac=%pM, vlan_id=%d\n",
598 __func__, (!mtype) ? "DELETE" : "ADD",
599 info->dest_ip,
600 info->dest_port, info->mac_addr, cminfo->vlan_id);
601 cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->cqp.sc_cqp;
602 cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request;
603 cqp_info->cqp_cmd = OP_MANAGE_QHASH_TABLE_ENTRY;
604 cqp_info->post_sq = 1;
605 status = i40iw_handle_cqp_op(iwdev, cqp_request);
606 if (status)
607 i40iw_pr_err("CQP-OP Manage Qhash Entry fail");
608 return status;
609}
610
611
612
613
614
615
616
617
618enum i40iw_status_code i40iw_hw_flush_wqes(struct i40iw_device *iwdev,
619 struct i40iw_sc_qp *qp,
620 struct i40iw_qp_flush_info *info,
621 bool wait)
622{
623 enum i40iw_status_code status;
624 struct i40iw_qp_flush_info *hw_info;
625 struct i40iw_cqp_request *cqp_request;
626 struct cqp_commands_info *cqp_info;
627 struct i40iw_qp *iwqp = (struct i40iw_qp *)qp->back_qp;
628
629 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
630 if (!cqp_request)
631 return I40IW_ERR_NO_MEMORY;
632
633 cqp_info = &cqp_request->info;
634 hw_info = &cqp_request->info.in.u.qp_flush_wqes.info;
635 memcpy(hw_info, info, sizeof(*hw_info));
636
637 cqp_info->cqp_cmd = OP_QP_FLUSH_WQES;
638 cqp_info->post_sq = 1;
639 cqp_info->in.u.qp_flush_wqes.qp = qp;
640 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request;
641 status = i40iw_handle_cqp_op(iwdev, cqp_request);
642 if (status) {
643 i40iw_pr_err("CQP-OP Flush WQE's fail");
644 complete(&iwqp->sq_drained);
645 complete(&iwqp->rq_drained);
646 return status;
647 }
648 if (!cqp_request->compl_info.maj_err_code) {
649 switch (cqp_request->compl_info.min_err_code) {
650 case I40IW_CQP_COMPL_RQ_WQE_FLUSHED:
651 complete(&iwqp->sq_drained);
652 break;
653 case I40IW_CQP_COMPL_SQ_WQE_FLUSHED:
654 complete(&iwqp->rq_drained);
655 break;
656 case I40IW_CQP_COMPL_RQ_SQ_WQE_FLUSHED:
657 break;
658 default:
659 complete(&iwqp->sq_drained);
660 complete(&iwqp->rq_drained);
661 break;
662 }
663 }
664
665 return 0;
666}
667
668
669
670
671
672
673
674enum i40iw_status_code i40iw_hw_manage_vf_pble_bp(struct i40iw_device *iwdev,
675 struct i40iw_manage_vf_pble_info *info,
676 bool wait)
677{
678 enum i40iw_status_code status;
679 struct i40iw_manage_vf_pble_info *hw_info;
680 struct i40iw_cqp_request *cqp_request;
681 struct cqp_commands_info *cqp_info;
682
683 if ((iwdev->init_state < CCQ_CREATED) && wait)
684 wait = false;
685
686 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
687 if (!cqp_request)
688 return I40IW_ERR_NO_MEMORY;
689
690 cqp_info = &cqp_request->info;
691 hw_info = &cqp_request->info.in.u.manage_vf_pble_bp.info;
692 memcpy(hw_info, info, sizeof(*hw_info));
693
694 cqp_info->cqp_cmd = OP_MANAGE_VF_PBLE_BP;
695 cqp_info->post_sq = 1;
696 cqp_info->in.u.manage_vf_pble_bp.cqp = &iwdev->cqp.sc_cqp;
697 cqp_info->in.u.manage_vf_pble_bp.scratch = (uintptr_t)cqp_request;
698 status = i40iw_handle_cqp_op(iwdev, cqp_request);
699 if (status)
700 i40iw_pr_err("CQP-OP Manage VF pble_bp fail");
701 return status;
702}
703
704
705
706
707
708static enum ib_wc_status i40iw_get_ib_wc(enum i40iw_flush_opcode opcode)
709{
710 switch (opcode) {
711 case FLUSH_PROT_ERR:
712 return IB_WC_LOC_PROT_ERR;
713 case FLUSH_REM_ACCESS_ERR:
714 return IB_WC_REM_ACCESS_ERR;
715 case FLUSH_LOC_QP_OP_ERR:
716 return IB_WC_LOC_QP_OP_ERR;
717 case FLUSH_REM_OP_ERR:
718 return IB_WC_REM_OP_ERR;
719 case FLUSH_LOC_LEN_ERR:
720 return IB_WC_LOC_LEN_ERR;
721 case FLUSH_GENERAL_ERR:
722 return IB_WC_GENERAL_ERR;
723 case FLUSH_FATAL_ERR:
724 default:
725 return IB_WC_FATAL_ERR;
726 }
727}
728
729
730
731
732
733
734
735
736static void i40iw_set_flush_info(struct i40iw_qp_flush_info *pinfo,
737 u16 *min,
738 u16 *maj,
739 enum i40iw_flush_opcode opcode)
740{
741 *min = (u16)i40iw_get_ib_wc(opcode);
742 *maj = CQE_MAJOR_DRV;
743 pinfo->userflushcode = true;
744}
745
746
747
748
749
750
751void i40iw_flush_wqes(struct i40iw_device *iwdev, struct i40iw_qp *iwqp)
752{
753 struct i40iw_qp_flush_info info;
754 struct i40iw_qp_flush_info *pinfo = &info;
755
756 struct i40iw_sc_qp *qp = &iwqp->sc_qp;
757
758 memset(pinfo, 0, sizeof(*pinfo));
759 info.sq = true;
760 info.rq = true;
761 if (qp->term_flags) {
762 i40iw_set_flush_info(pinfo, &pinfo->sq_minor_code,
763 &pinfo->sq_major_code, qp->flush_code);
764 i40iw_set_flush_info(pinfo, &pinfo->rq_minor_code,
765 &pinfo->rq_major_code, qp->flush_code);
766 }
767 (void)i40iw_hw_flush_wqes(iwdev, &iwqp->sc_qp, &info, true);
768}
769
