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33#include <linux/debugfs.h>
34#include <linux/highmem.h>
35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
44#include <linux/sched.h>
45#include <linux/sched/mm.h>
46#include <linux/sched/task.h>
47#include <linux/delay.h>
48#include <rdma/ib_user_verbs.h>
49#include <rdma/ib_addr.h>
50#include <rdma/ib_cache.h>
51#include <linux/mlx5/port.h>
52#include <linux/mlx5/vport.h>
53#include <linux/list.h>
54#include <rdma/ib_smi.h>
55#include <rdma/ib_umem.h>
56#include <linux/in.h>
57#include <linux/etherdevice.h>
58#include <linux/mlx5/fs.h>
59#include <linux/mlx5/vport.h>
60#include "mlx5_ib.h"
61#include "cmd.h"
62#include <linux/mlx5/vport.h>
63
64#define DRIVER_NAME "mlx5_ib"
65#define DRIVER_VERSION "5.0-0"
66
67MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
68MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
69MODULE_LICENSE("Dual BSD/GPL");
70
71static char mlx5_version[] =
72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
73 DRIVER_VERSION "\n";
74
75enum {
76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
77};
78
79static enum rdma_link_layer
80mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
81{
82 switch (port_type_cap) {
83 case MLX5_CAP_PORT_TYPE_IB:
84 return IB_LINK_LAYER_INFINIBAND;
85 case MLX5_CAP_PORT_TYPE_ETH:
86 return IB_LINK_LAYER_ETHERNET;
87 default:
88 return IB_LINK_LAYER_UNSPECIFIED;
89 }
90}
91
92static enum rdma_link_layer
93mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
94{
95 struct mlx5_ib_dev *dev = to_mdev(device);
96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
97
98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
99}
100
101static int get_port_state(struct ib_device *ibdev,
102 u8 port_num,
103 enum ib_port_state *state)
104{
105 struct ib_port_attr attr;
106 int ret;
107
108 memset(&attr, 0, sizeof(attr));
109 ret = mlx5_ib_query_port(ibdev, port_num, &attr);
110 if (!ret)
111 *state = attr.state;
112 return ret;
113}
114
115static int mlx5_netdev_event(struct notifier_block *this,
116 unsigned long event, void *ptr)
117{
118 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
119 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
120 roce.nb);
121
122 switch (event) {
123 case NETDEV_REGISTER:
124 case NETDEV_UNREGISTER:
125 write_lock(&ibdev->roce.netdev_lock);
126 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
127 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
128 NULL : ndev;
129 write_unlock(&ibdev->roce.netdev_lock);
130 break;
131
132 case NETDEV_CHANGE:
133 case NETDEV_UP:
134 case NETDEV_DOWN: {
135 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
136 struct net_device *upper = NULL;
137
138 if (lag_ndev) {
139 upper = netdev_master_upper_dev_get(lag_ndev);
140 dev_put(lag_ndev);
141 }
142
143 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
144 && ibdev->ib_active) {
145 struct ib_event ibev = { };
146 enum ib_port_state port_state;
147
148 if (get_port_state(&ibdev->ib_dev, 1, &port_state))
149 return NOTIFY_DONE;
150
151 if (ibdev->roce.last_port_state == port_state)
152 return NOTIFY_DONE;
153
154 ibdev->roce.last_port_state = port_state;
155 ibev.device = &ibdev->ib_dev;
156 if (port_state == IB_PORT_DOWN)
157 ibev.event = IB_EVENT_PORT_ERR;
158 else if (port_state == IB_PORT_ACTIVE)
159 ibev.event = IB_EVENT_PORT_ACTIVE;
160 else
161 return NOTIFY_DONE;
162
163 ibev.element.port_num = 1;
164 ib_dispatch_event(&ibev);
165 }
166 break;
167 }
168
169 default:
170 break;
171 }
172
173 return NOTIFY_DONE;
174}
175
176static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
177 u8 port_num)
178{
179 struct mlx5_ib_dev *ibdev = to_mdev(device);
180 struct net_device *ndev;
181
182 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
183 if (ndev)
184 return ndev;
185
186
187
188 read_lock(&ibdev->roce.netdev_lock);
189 ndev = ibdev->roce.netdev;
190 if (ndev)
191 dev_hold(ndev);
192 read_unlock(&ibdev->roce.netdev_lock);
193
194 return ndev;
195}
196
197static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
198 u8 *active_width)
199{
200 switch (eth_proto_oper) {
201 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
202 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
203 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
204 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
205 *active_width = IB_WIDTH_1X;
206 *active_speed = IB_SPEED_SDR;
207 break;
208 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
209 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
210 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
211 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
212 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
213 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
214 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
215 *active_width = IB_WIDTH_1X;
216 *active_speed = IB_SPEED_QDR;
217 break;
218 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
219 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
220 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
221 *active_width = IB_WIDTH_1X;
222 *active_speed = IB_SPEED_EDR;
223 break;
224 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
225 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
226 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
227 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
228 *active_width = IB_WIDTH_4X;
229 *active_speed = IB_SPEED_QDR;
230 break;
231 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
232 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
233 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
234 *active_width = IB_WIDTH_1X;
235 *active_speed = IB_SPEED_HDR;
236 break;
237 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
238 *active_width = IB_WIDTH_4X;
239 *active_speed = IB_SPEED_FDR;
240 break;
241 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
242 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
243 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
244 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
245 *active_width = IB_WIDTH_4X;
246 *active_speed = IB_SPEED_EDR;
247 break;
248 default:
249 return -EINVAL;
250 }
251
252 return 0;
253}
254
255static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
256 struct ib_port_attr *props)
257{
258 struct mlx5_ib_dev *dev = to_mdev(device);
259 struct mlx5_core_dev *mdev = dev->mdev;
260 struct net_device *ndev, *upper;
261 enum ib_mtu ndev_ib_mtu;
262 u16 qkey_viol_cntr;
263 u32 eth_prot_oper;
264 int err;
265
266
267
268
269 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, port_num);
270 if (err)
271 return err;
272
273 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
274 &props->active_width);
275
276 props->port_cap_flags |= IB_PORT_CM_SUP;
277 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
278
279 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
280 roce_address_table_size);
281 props->max_mtu = IB_MTU_4096;
282 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
283 props->pkey_tbl_len = 1;
284 props->state = IB_PORT_DOWN;
285 props->phys_state = 3;
286
287 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
288 props->qkey_viol_cntr = qkey_viol_cntr;
289
290 ndev = mlx5_ib_get_netdev(device, port_num);
291 if (!ndev)
292 return 0;
293
294 if (mlx5_lag_is_active(dev->mdev)) {
295 rcu_read_lock();
296 upper = netdev_master_upper_dev_get_rcu(ndev);
297 if (upper) {
298 dev_put(ndev);
299 ndev = upper;
300 dev_hold(ndev);
301 }
302 rcu_read_unlock();
303 }
304
305 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
306 props->state = IB_PORT_ACTIVE;
307 props->phys_state = 5;
308 }
309
310 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
311
312 dev_put(ndev);
313
314 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
315 return 0;
316}
317
318static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
319 unsigned int index, const union ib_gid *gid,
320 const struct ib_gid_attr *attr)
321{
322 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
323 u8 roce_version = 0;
324 u8 roce_l3_type = 0;
325 bool vlan = false;
326 u8 mac[ETH_ALEN];
327 u16 vlan_id = 0;
328
329 if (gid) {
330 gid_type = attr->gid_type;
331 ether_addr_copy(mac, attr->ndev->dev_addr);
332
333 if (is_vlan_dev(attr->ndev)) {
334 vlan = true;
335 vlan_id = vlan_dev_vlan_id(attr->ndev);
336 }
337 }
338
339 switch (gid_type) {
340 case IB_GID_TYPE_IB:
341 roce_version = MLX5_ROCE_VERSION_1;
342 break;
343 case IB_GID_TYPE_ROCE_UDP_ENCAP:
344 roce_version = MLX5_ROCE_VERSION_2;
345 if (ipv6_addr_v4mapped((void *)gid))
346 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
347 else
348 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
349 break;
350
351 default:
352 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
353 }
354
355 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
356 roce_l3_type, gid->raw, mac, vlan,
357 vlan_id);
358}
359
360static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
361 unsigned int index, const union ib_gid *gid,
362 const struct ib_gid_attr *attr,
363 __always_unused void **context)
364{
365 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
366}
367
368static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
369 unsigned int index, __always_unused void **context)
370{
371 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
372}
373
374__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
375 int index)
376{
377 struct ib_gid_attr attr;
378 union ib_gid gid;
379
380 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
381 return 0;
382
383 if (!attr.ndev)
384 return 0;
385
386 dev_put(attr.ndev);
387
388 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
389 return 0;
390
391 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
392}
393
394int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
395 int index, enum ib_gid_type *gid_type)
396{
397 struct ib_gid_attr attr;
398 union ib_gid gid;
399 int ret;
400
401 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
402 if (ret)
403 return ret;
404
405 if (!attr.ndev)
406 return -ENODEV;
407
408 dev_put(attr.ndev);
409
410 *gid_type = attr.gid_type;
411
412 return 0;
413}
414
415static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
416{
417 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
418 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
419 return 0;
420}
421
422enum {
423 MLX5_VPORT_ACCESS_METHOD_MAD,
424 MLX5_VPORT_ACCESS_METHOD_HCA,
425 MLX5_VPORT_ACCESS_METHOD_NIC,
426};
427
428static int mlx5_get_vport_access_method(struct ib_device *ibdev)
429{
430 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
431 return MLX5_VPORT_ACCESS_METHOD_MAD;
432
433 if (mlx5_ib_port_link_layer(ibdev, 1) ==
434 IB_LINK_LAYER_ETHERNET)
435 return MLX5_VPORT_ACCESS_METHOD_NIC;
436
437 return MLX5_VPORT_ACCESS_METHOD_HCA;
438}
439
440static void get_atomic_caps(struct mlx5_ib_dev *dev,
441 struct ib_device_attr *props)
442{
443 u8 tmp;
444 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
445 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
446 u8 atomic_req_8B_endianness_mode =
447 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
448
449
450
451
452 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
453 if (((atomic_operations & tmp) == tmp) &&
454 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
455 (atomic_req_8B_endianness_mode)) {
456 props->atomic_cap = IB_ATOMIC_HCA;
457 } else {
458 props->atomic_cap = IB_ATOMIC_NONE;
459 }
460}
461
462static int mlx5_query_system_image_guid(struct ib_device *ibdev,
463 __be64 *sys_image_guid)
464{
465 struct mlx5_ib_dev *dev = to_mdev(ibdev);
466 struct mlx5_core_dev *mdev = dev->mdev;
467 u64 tmp;
468 int err;
469
470 switch (mlx5_get_vport_access_method(ibdev)) {
471 case MLX5_VPORT_ACCESS_METHOD_MAD:
472 return mlx5_query_mad_ifc_system_image_guid(ibdev,
473 sys_image_guid);
474
475 case MLX5_VPORT_ACCESS_METHOD_HCA:
476 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
477 break;
478
479 case MLX5_VPORT_ACCESS_METHOD_NIC:
480 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
481 break;
482
483 default:
484 return -EINVAL;
485 }
486
487 if (!err)
488 *sys_image_guid = cpu_to_be64(tmp);
489
490 return err;
491
492}
493
494static int mlx5_query_max_pkeys(struct ib_device *ibdev,
495 u16 *max_pkeys)
496{
497 struct mlx5_ib_dev *dev = to_mdev(ibdev);
498 struct mlx5_core_dev *mdev = dev->mdev;
499
500 switch (mlx5_get_vport_access_method(ibdev)) {
501 case MLX5_VPORT_ACCESS_METHOD_MAD:
502 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
503
504 case MLX5_VPORT_ACCESS_METHOD_HCA:
505 case MLX5_VPORT_ACCESS_METHOD_NIC:
506 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
507 pkey_table_size));
508 return 0;
509
510 default:
511 return -EINVAL;
512 }
513}
514
515static int mlx5_query_vendor_id(struct ib_device *ibdev,
516 u32 *vendor_id)
517{
518 struct mlx5_ib_dev *dev = to_mdev(ibdev);
519
520 switch (mlx5_get_vport_access_method(ibdev)) {
521 case MLX5_VPORT_ACCESS_METHOD_MAD:
522 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
523
524 case MLX5_VPORT_ACCESS_METHOD_HCA:
525 case MLX5_VPORT_ACCESS_METHOD_NIC:
526 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
527
528 default:
529 return -EINVAL;
530 }
531}
532
533static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
534 __be64 *node_guid)
535{
536 u64 tmp;
537 int err;
538
539 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
540 case MLX5_VPORT_ACCESS_METHOD_MAD:
541 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
542
543 case MLX5_VPORT_ACCESS_METHOD_HCA:
544 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
545 break;
546
547 case MLX5_VPORT_ACCESS_METHOD_NIC:
548 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
549 break;
550
551 default:
552 return -EINVAL;
553 }
554
555 if (!err)
556 *node_guid = cpu_to_be64(tmp);
557
558 return err;
559}
560
561struct mlx5_reg_node_desc {
562 u8 desc[IB_DEVICE_NODE_DESC_MAX];
563};
564
565static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
566{
567 struct mlx5_reg_node_desc in;
568
569 if (mlx5_use_mad_ifc(dev))
570 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
571
572 memset(&in, 0, sizeof(in));
573
574 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
575 sizeof(struct mlx5_reg_node_desc),
576 MLX5_REG_NODE_DESC, 0, 0);
577}
578
579static int mlx5_ib_query_device(struct ib_device *ibdev,
580 struct ib_device_attr *props,
581 struct ib_udata *uhw)
582{
583 struct mlx5_ib_dev *dev = to_mdev(ibdev);
584 struct mlx5_core_dev *mdev = dev->mdev;
585 int err = -ENOMEM;
586 int max_sq_desc;
587 int max_rq_sg;
588 int max_sq_sg;
589 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
590 struct mlx5_ib_query_device_resp resp = {};
591 size_t resp_len;
592 u64 max_tso;
593
594 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
595 if (uhw->outlen && uhw->outlen < resp_len)
596 return -EINVAL;
597 else
598 resp.response_length = resp_len;
599
600 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
601 return -EINVAL;
602
603 memset(props, 0, sizeof(*props));
604 err = mlx5_query_system_image_guid(ibdev,
605 &props->sys_image_guid);
606 if (err)
607 return err;
608
609 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
610 if (err)
611 return err;
612
613 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
614 if (err)
615 return err;
616
617 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
618 (fw_rev_min(dev->mdev) << 16) |
619 fw_rev_sub(dev->mdev);
620 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
621 IB_DEVICE_PORT_ACTIVE_EVENT |
622 IB_DEVICE_SYS_IMAGE_GUID |
623 IB_DEVICE_RC_RNR_NAK_GEN;
624
625 if (MLX5_CAP_GEN(mdev, pkv))
626 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
627 if (MLX5_CAP_GEN(mdev, qkv))
628 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
629 if (MLX5_CAP_GEN(mdev, apm))
630 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
631 if (MLX5_CAP_GEN(mdev, xrc))
632 props->device_cap_flags |= IB_DEVICE_XRC;
633 if (MLX5_CAP_GEN(mdev, imaicl)) {
634 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
635 IB_DEVICE_MEM_WINDOW_TYPE_2B;
636 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
637
638 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
639 }
640 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
641 if (MLX5_CAP_GEN(mdev, sho)) {
642 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
643
644 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
645 IB_PROT_T10DIF_TYPE_2 |
646 IB_PROT_T10DIF_TYPE_3;
647 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
648 IB_GUARD_T10DIF_CSUM;
649 }
650 if (MLX5_CAP_GEN(mdev, block_lb_mc))
651 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
652
653 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
654 if (MLX5_CAP_ETH(mdev, csum_cap)) {
655
656 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
657 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
658 }
659
660 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
661 props->raw_packet_caps |=
662 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
663
664 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
665 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
666 if (max_tso) {
667 resp.tso_caps.max_tso = 1 << max_tso;
668 resp.tso_caps.supported_qpts |=
669 1 << IB_QPT_RAW_PACKET;
670 resp.response_length += sizeof(resp.tso_caps);
671 }
672 }
673
674 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
675 resp.rss_caps.rx_hash_function =
676 MLX5_RX_HASH_FUNC_TOEPLITZ;
677 resp.rss_caps.rx_hash_fields_mask =
678 MLX5_RX_HASH_SRC_IPV4 |
679 MLX5_RX_HASH_DST_IPV4 |
680 MLX5_RX_HASH_SRC_IPV6 |
681 MLX5_RX_HASH_DST_IPV6 |
682 MLX5_RX_HASH_SRC_PORT_TCP |
683 MLX5_RX_HASH_DST_PORT_TCP |
684 MLX5_RX_HASH_SRC_PORT_UDP |
685 MLX5_RX_HASH_DST_PORT_UDP;
686 resp.response_length += sizeof(resp.rss_caps);
687 }
688 } else {
689 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
690 resp.response_length += sizeof(resp.tso_caps);
691 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
692 resp.response_length += sizeof(resp.rss_caps);
693 }
694
695 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
696 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
697 props->device_cap_flags |= IB_DEVICE_UD_TSO;
698 }
699
700 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
701 MLX5_CAP_GEN(dev->mdev, general_notification_event))
702 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
703
704 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
705 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
706 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
707
708 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
709 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
710
711 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
712 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
713 }
714
715 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
716 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
717
718 props->vendor_part_id = mdev->pdev->device;
719 props->hw_ver = mdev->pdev->revision;
720
721 props->max_mr_size = ~0ull;
722 props->page_size_cap = ~(min_page_size - 1);
723 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
724 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
725 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
726 sizeof(struct mlx5_wqe_data_seg);
727 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
728 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
729 sizeof(struct mlx5_wqe_raddr_seg)) /
730 sizeof(struct mlx5_wqe_data_seg);
731 props->max_sge = min(max_rq_sg, max_sq_sg);
732 props->max_sge_rd = MLX5_MAX_SGE_RD;
733 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
734 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
735 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
736 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
737 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
738 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
739 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
740 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
741 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
742 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
743 props->max_srq_sge = max_rq_sg - 1;
744 props->max_fast_reg_page_list_len =
745 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
746 get_atomic_caps(dev, props);
747 props->masked_atomic_cap = IB_ATOMIC_NONE;
748 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
749 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
750 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
751 props->max_mcast_grp;
752 props->max_map_per_fmr = INT_MAX;
753 props->max_ah = INT_MAX;
754 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
755 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
756
757#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
758 if (MLX5_CAP_GEN(mdev, pg))
759 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
760 props->odp_caps = dev->odp_caps;
761#endif
762
763 if (MLX5_CAP_GEN(mdev, cd))
764 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
765
766 if (!mlx5_core_is_pf(mdev))
767 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
768
769 if (mlx5_ib_port_link_layer(ibdev, 1) ==
770 IB_LINK_LAYER_ETHERNET) {
771 props->rss_caps.max_rwq_indirection_tables =
772 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
773 props->rss_caps.max_rwq_indirection_table_size =
774 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
775 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
776 props->max_wq_type_rq =
777 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
778 }
779
780 if (MLX5_CAP_GEN(mdev, tag_matching)) {
781 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
782 props->tm_caps.max_num_tags =
783 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
784 props->tm_caps.flags = IB_TM_CAP_RC;
785 props->tm_caps.max_ops =
786 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
787 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
788 }
789
790 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
791 resp.cqe_comp_caps.max_num =
792 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
793 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
794 resp.cqe_comp_caps.supported_format =
795 MLX5_IB_CQE_RES_FORMAT_HASH |
796 MLX5_IB_CQE_RES_FORMAT_CSUM;
797 resp.response_length += sizeof(resp.cqe_comp_caps);
798 }
799
800 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
801 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
802 MLX5_CAP_GEN(mdev, qos)) {
803 resp.packet_pacing_caps.qp_rate_limit_max =
804 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
805 resp.packet_pacing_caps.qp_rate_limit_min =
806 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
807 resp.packet_pacing_caps.supported_qpts |=
808 1 << IB_QPT_RAW_PACKET;
809 }
810 resp.response_length += sizeof(resp.packet_pacing_caps);
811 }
812
813 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
814 uhw->outlen)) {
815 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
816 resp.mlx5_ib_support_multi_pkt_send_wqes =
817 MLX5_IB_ALLOW_MPW;
818
819 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
820 resp.mlx5_ib_support_multi_pkt_send_wqes |=
821 MLX5_IB_SUPPORT_EMPW;
822
823 resp.response_length +=
824 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
825 }
826
827 if (field_avail(typeof(resp), reserved, uhw->outlen))
828 resp.response_length += sizeof(resp.reserved);
829
830 if (field_avail(typeof(resp), sw_parsing_caps,
831 uhw->outlen)) {
832 resp.response_length += sizeof(resp.sw_parsing_caps);
833 if (MLX5_CAP_ETH(mdev, swp)) {
834 resp.sw_parsing_caps.sw_parsing_offloads |=
835 MLX5_IB_SW_PARSING;
836
837 if (MLX5_CAP_ETH(mdev, swp_csum))
838 resp.sw_parsing_caps.sw_parsing_offloads |=
839 MLX5_IB_SW_PARSING_CSUM;
840
841 if (MLX5_CAP_ETH(mdev, swp_lso))
842 resp.sw_parsing_caps.sw_parsing_offloads |=
843 MLX5_IB_SW_PARSING_LSO;
844
845 if (resp.sw_parsing_caps.sw_parsing_offloads)
846 resp.sw_parsing_caps.supported_qpts =
847 BIT(IB_QPT_RAW_PACKET);
848 }
849 }
850
851 if (uhw->outlen) {
852 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
853
854 if (err)
855 return err;
856 }
857
858 return 0;
859}
860
861enum mlx5_ib_width {
862 MLX5_IB_WIDTH_1X = 1 << 0,
863 MLX5_IB_WIDTH_2X = 1 << 1,
864 MLX5_IB_WIDTH_4X = 1 << 2,
865 MLX5_IB_WIDTH_8X = 1 << 3,
866 MLX5_IB_WIDTH_12X = 1 << 4
867};
868
869static int translate_active_width(struct ib_device *ibdev, u8 active_width,
870 u8 *ib_width)
871{
872 struct mlx5_ib_dev *dev = to_mdev(ibdev);
873 int err = 0;
874
875 if (active_width & MLX5_IB_WIDTH_1X) {
876 *ib_width = IB_WIDTH_1X;
877 } else if (active_width & MLX5_IB_WIDTH_2X) {
878 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
879 (int)active_width);
880 err = -EINVAL;
881 } else if (active_width & MLX5_IB_WIDTH_4X) {
882 *ib_width = IB_WIDTH_4X;
883 } else if (active_width & MLX5_IB_WIDTH_8X) {
884 *ib_width = IB_WIDTH_8X;
885 } else if (active_width & MLX5_IB_WIDTH_12X) {
886 *ib_width = IB_WIDTH_12X;
887 } else {
888 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
889 (int)active_width);
890 err = -EINVAL;
891 }
892
893 return err;
894}
895
896static int mlx5_mtu_to_ib_mtu(int mtu)
897{
898 switch (mtu) {
899 case 256: return 1;
900 case 512: return 2;
901 case 1024: return 3;
902 case 2048: return 4;
903 case 4096: return 5;
904 default:
905 pr_warn("invalid mtu\n");
906 return -1;
907 }
908}
909
910enum ib_max_vl_num {
911 __IB_MAX_VL_0 = 1,
912 __IB_MAX_VL_0_1 = 2,
913 __IB_MAX_VL_0_3 = 3,
914 __IB_MAX_VL_0_7 = 4,
915 __IB_MAX_VL_0_14 = 5,
916};
917
918enum mlx5_vl_hw_cap {
919 MLX5_VL_HW_0 = 1,
920 MLX5_VL_HW_0_1 = 2,
921 MLX5_VL_HW_0_2 = 3,
922 MLX5_VL_HW_0_3 = 4,
923 MLX5_VL_HW_0_4 = 5,
924 MLX5_VL_HW_0_5 = 6,
925 MLX5_VL_HW_0_6 = 7,
926 MLX5_VL_HW_0_7 = 8,
927 MLX5_VL_HW_0_14 = 15
928};
929
930static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
931 u8 *max_vl_num)
932{
933 switch (vl_hw_cap) {
934 case MLX5_VL_HW_0:
935 *max_vl_num = __IB_MAX_VL_0;
936 break;
937 case MLX5_VL_HW_0_1:
938 *max_vl_num = __IB_MAX_VL_0_1;
939 break;
940 case MLX5_VL_HW_0_3:
941 *max_vl_num = __IB_MAX_VL_0_3;
942 break;
943 case MLX5_VL_HW_0_7:
944 *max_vl_num = __IB_MAX_VL_0_7;
945 break;
946 case MLX5_VL_HW_0_14:
947 *max_vl_num = __IB_MAX_VL_0_14;
948 break;
949
950 default:
951 return -EINVAL;
952 }
953
954 return 0;
955}
956
957static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
958 struct ib_port_attr *props)
959{
960 struct mlx5_ib_dev *dev = to_mdev(ibdev);
961 struct mlx5_core_dev *mdev = dev->mdev;
962 struct mlx5_hca_vport_context *rep;
963 u16 max_mtu;
964 u16 oper_mtu;
965 int err;
966 u8 ib_link_width_oper;
967 u8 vl_hw_cap;
968
969 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
970 if (!rep) {
971 err = -ENOMEM;
972 goto out;
973 }
974
975
976
977 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
978 if (err)
979 goto out;
980
981 props->lid = rep->lid;
982 props->lmc = rep->lmc;
983 props->sm_lid = rep->sm_lid;
984 props->sm_sl = rep->sm_sl;
985 props->state = rep->vport_state;
986 props->phys_state = rep->port_physical_state;
987 props->port_cap_flags = rep->cap_mask1;
988 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
989 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
990 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
991 props->bad_pkey_cntr = rep->pkey_violation_counter;
992 props->qkey_viol_cntr = rep->qkey_violation_counter;
993 props->subnet_timeout = rep->subnet_timeout;
994 props->init_type_reply = rep->init_type_reply;
995 props->grh_required = rep->grh_required;
996
997 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
998 if (err)
999 goto out;
1000
1001 err = translate_active_width(ibdev, ib_link_width_oper,
1002 &props->active_width);
1003 if (err)
1004 goto out;
1005 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1006 if (err)
1007 goto out;
1008
1009 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1010
1011 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1012
1013 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1014
1015 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1016
1017 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1018 if (err)
1019 goto out;
1020
1021 err = translate_max_vl_num(ibdev, vl_hw_cap,
1022 &props->max_vl_num);
1023out:
1024 kfree(rep);
1025 return err;
1026}
1027
1028int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1029 struct ib_port_attr *props)
1030{
1031 unsigned int count;
1032 int ret;
1033
1034 switch (mlx5_get_vport_access_method(ibdev)) {
1035 case MLX5_VPORT_ACCESS_METHOD_MAD:
1036 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1037 break;
1038
1039 case MLX5_VPORT_ACCESS_METHOD_HCA:
1040 ret = mlx5_query_hca_port(ibdev, port, props);
1041 break;
1042
1043 case MLX5_VPORT_ACCESS_METHOD_NIC:
1044 ret = mlx5_query_port_roce(ibdev, port, props);
1045 break;
1046
1047 default:
1048 ret = -EINVAL;
1049 }
1050
1051 if (!ret && props) {
1052 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
1053 props->gid_tbl_len -= count;
1054 }
1055 return ret;
1056}
1057
1058static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1059 union ib_gid *gid)
1060{
1061 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1062 struct mlx5_core_dev *mdev = dev->mdev;
1063
1064 switch (mlx5_get_vport_access_method(ibdev)) {
1065 case MLX5_VPORT_ACCESS_METHOD_MAD:
1066 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1067
1068 case MLX5_VPORT_ACCESS_METHOD_HCA:
1069 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1070
1071 default:
1072 return -EINVAL;
1073 }
1074
1075}
1076
1077static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1078 u16 *pkey)
1079{
1080 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1081 struct mlx5_core_dev *mdev = dev->mdev;
1082
1083 switch (mlx5_get_vport_access_method(ibdev)) {
1084 case MLX5_VPORT_ACCESS_METHOD_MAD:
1085 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1086
1087 case MLX5_VPORT_ACCESS_METHOD_HCA:
1088 case MLX5_VPORT_ACCESS_METHOD_NIC:
1089 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
1090 pkey);
1091 default:
1092 return -EINVAL;
1093 }
1094}
1095
1096static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1097 struct ib_device_modify *props)
1098{
1099 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1100 struct mlx5_reg_node_desc in;
1101 struct mlx5_reg_node_desc out;
1102 int err;
1103
1104 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1105 return -EOPNOTSUPP;
1106
1107 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1108 return 0;
1109
1110
1111
1112
1113
1114 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1115 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1116 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1117 if (err)
1118 return err;
1119
1120 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1121
1122 return err;
1123}
1124
1125static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1126 u32 value)
1127{
1128 struct mlx5_hca_vport_context ctx = {};
1129 int err;
1130
1131 err = mlx5_query_hca_vport_context(dev->mdev, 0,
1132 port_num, 0, &ctx);
1133 if (err)
1134 return err;
1135
1136 if (~ctx.cap_mask1_perm & mask) {
1137 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1138 mask, ctx.cap_mask1_perm);
1139 return -EINVAL;
1140 }
1141
1142 ctx.cap_mask1 = value;
1143 ctx.cap_mask1_perm = mask;
1144 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1145 port_num, 0, &ctx);
1146
1147 return err;
1148}
1149
1150static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1151 struct ib_port_modify *props)
1152{
1153 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1154 struct ib_port_attr attr;
1155 u32 tmp;
1156 int err;
1157 u32 change_mask;
1158 u32 value;
1159 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1160 IB_LINK_LAYER_INFINIBAND);
1161
1162
1163
1164
1165 if (!is_ib)
1166 return 0;
1167
1168 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1169 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1170 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1171 return set_port_caps_atomic(dev, port, change_mask, value);
1172 }
1173
1174 mutex_lock(&dev->cap_mask_mutex);
1175
1176 err = ib_query_port(ibdev, port, &attr);
1177 if (err)
1178 goto out;
1179
1180 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1181 ~props->clr_port_cap_mask;
1182
1183 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1184
1185out:
1186 mutex_unlock(&dev->cap_mask_mutex);
1187 return err;
1188}
1189
1190static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1191{
1192 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1193 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1194}
1195
1196static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1197 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1198 u32 *num_sys_pages)
1199{
1200 int uars_per_sys_page;
1201 int bfregs_per_sys_page;
1202 int ref_bfregs = req->total_num_bfregs;
1203
1204 if (req->total_num_bfregs == 0)
1205 return -EINVAL;
1206
1207 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1208 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1209
1210 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1211 return -ENOMEM;
1212
1213 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1214 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1215 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1216 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1217
1218 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1219 return -EINVAL;
1220
1221 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, using %d sys pages\n",
1222 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1223 lib_uar_4k ? "yes" : "no", ref_bfregs,
1224 req->total_num_bfregs, *num_sys_pages);
1225
1226 return 0;
1227}
1228
1229static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1230{
1231 struct mlx5_bfreg_info *bfregi;
1232 int err;
1233 int i;
1234
1235 bfregi = &context->bfregi;
1236 for (i = 0; i < bfregi->num_sys_pages; i++) {
1237 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1238 if (err)
1239 goto error;
1240
1241 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1242 }
1243 return 0;
1244
1245error:
1246 for (--i; i >= 0; i--)
1247 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1248 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1249
1250 return err;
1251}
1252
1253static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1254{
1255 struct mlx5_bfreg_info *bfregi;
1256 int err;
1257 int i;
1258
1259 bfregi = &context->bfregi;
1260 for (i = 0; i < bfregi->num_sys_pages; i++) {
1261 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1262 if (err) {
1263 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1264 return err;
1265 }
1266 }
1267 return 0;
1268}
1269
1270static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1271{
1272 int err;
1273
1274 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1275 if (err)
1276 return err;
1277
1278 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1279 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1280 return err;
1281
1282 mutex_lock(&dev->lb_mutex);
1283 dev->user_td++;
1284
1285 if (dev->user_td == 2)
1286 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1287
1288 mutex_unlock(&dev->lb_mutex);
1289 return err;
1290}
1291
1292static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1293{
1294 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1295
1296 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1297 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1298 return;
1299
1300 mutex_lock(&dev->lb_mutex);
1301 dev->user_td--;
1302
1303 if (dev->user_td < 2)
1304 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1305
1306 mutex_unlock(&dev->lb_mutex);
1307}
1308
1309static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1310 struct ib_udata *udata)
1311{
1312 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1313 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1314 struct mlx5_ib_alloc_ucontext_resp resp = {};
1315 struct mlx5_ib_ucontext *context;
1316 struct mlx5_bfreg_info *bfregi;
1317 int ver;
1318 int err;
1319 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1320 max_cqe_version);
1321 bool lib_uar_4k;
1322
1323 if (!dev->ib_active)
1324 return ERR_PTR(-EAGAIN);
1325
1326 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1327 ver = 0;
1328 else if (udata->inlen >= min_req_v2)
1329 ver = 2;
1330 else
1331 return ERR_PTR(-EINVAL);
1332
1333 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1334 if (err)
1335 return ERR_PTR(err);
1336
1337 if (req.flags)
1338 return ERR_PTR(-EINVAL);
1339
1340 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1341 return ERR_PTR(-EOPNOTSUPP);
1342
1343 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1344 MLX5_NON_FP_BFREGS_PER_UAR);
1345 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1346 return ERR_PTR(-EINVAL);
1347
1348 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1349 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1350 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1351 resp.cache_line_size = cache_line_size();
1352 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1353 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1354 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1355 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1356 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1357 resp.cqe_version = min_t(__u8,
1358 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1359 req.max_cqe_version);
1360 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1361 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1362 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1363 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1364 resp.response_length = min(offsetof(typeof(resp), response_length) +
1365 sizeof(resp.response_length), udata->outlen);
1366
1367 context = kzalloc(sizeof(*context), GFP_KERNEL);
1368 if (!context)
1369 return ERR_PTR(-ENOMEM);
1370
1371 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1372 bfregi = &context->bfregi;
1373
1374
1375 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1376 if (err)
1377 goto out_ctx;
1378
1379 mutex_init(&bfregi->lock);
1380 bfregi->lib_uar_4k = lib_uar_4k;
1381 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
1382 GFP_KERNEL);
1383 if (!bfregi->count) {
1384 err = -ENOMEM;
1385 goto out_ctx;
1386 }
1387
1388 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1389 sizeof(*bfregi->sys_pages),
1390 GFP_KERNEL);
1391 if (!bfregi->sys_pages) {
1392 err = -ENOMEM;
1393 goto out_count;
1394 }
1395
1396 err = allocate_uars(dev, context);
1397 if (err)
1398 goto out_sys_pages;
1399
1400#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1401 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1402#endif
1403
1404 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1405 if (!context->upd_xlt_page) {
1406 err = -ENOMEM;
1407 goto out_uars;
1408 }
1409 mutex_init(&context->upd_xlt_page_mutex);
1410
1411 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1412 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1413 if (err)
1414 goto out_page;
1415 }
1416
1417 INIT_LIST_HEAD(&context->vma_private_list);
1418 INIT_LIST_HEAD(&context->db_page_list);
1419 mutex_init(&context->db_page_mutex);
1420
1421 resp.tot_bfregs = req.total_num_bfregs;
1422 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1423
1424 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1425 resp.response_length += sizeof(resp.cqe_version);
1426
1427 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1428 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1429 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1430 resp.response_length += sizeof(resp.cmds_supp_uhw);
1431 }
1432
1433 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1434 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1435 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1436 resp.eth_min_inline++;
1437 }
1438 resp.response_length += sizeof(resp.eth_min_inline);
1439 }
1440
1441
1442
1443
1444
1445
1446
1447 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1448 if (PAGE_SIZE <= 4096) {
1449 resp.comp_mask |=
1450 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1451 resp.hca_core_clock_offset =
1452 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1453 }
1454 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1455 sizeof(resp.reserved2);
1456 }
1457
1458 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1459 resp.response_length += sizeof(resp.log_uar_size);
1460
1461 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1462 resp.response_length += sizeof(resp.num_uars_per_page);
1463
1464 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1465 if (err)
1466 goto out_td;
1467
1468 bfregi->ver = ver;
1469 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1470 context->cqe_version = resp.cqe_version;
1471 context->lib_caps = req.lib_caps;
1472 print_lib_caps(dev, context->lib_caps);
1473
1474 return &context->ibucontext;
1475
1476out_td:
1477 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1478 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1479
1480out_page:
1481 free_page(context->upd_xlt_page);
1482
1483out_uars:
1484 deallocate_uars(dev, context);
1485
1486out_sys_pages:
1487 kfree(bfregi->sys_pages);
1488
1489out_count:
1490 kfree(bfregi->count);
1491
1492out_ctx:
1493 kfree(context);
1494
1495 return ERR_PTR(err);
1496}
1497
1498static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1499{
1500 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1501 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1502 struct mlx5_bfreg_info *bfregi;
1503
1504 bfregi = &context->bfregi;
1505 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1506 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1507
1508 free_page(context->upd_xlt_page);
1509 deallocate_uars(dev, context);
1510 kfree(bfregi->sys_pages);
1511 kfree(bfregi->count);
1512 kfree(context);
1513
1514 return 0;
1515}
1516
1517static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1518 struct mlx5_bfreg_info *bfregi,
1519 int idx)
1520{
1521 int fw_uars_per_page;
1522
1523 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1524
1525 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1526 bfregi->sys_pages[idx] / fw_uars_per_page;
1527}
1528
1529static int get_command(unsigned long offset)
1530{
1531 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1532}
1533
1534static int get_arg(unsigned long offset)
1535{
1536 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1537}
1538
1539static int get_index(unsigned long offset)
1540{
1541 return get_arg(offset);
1542}
1543
1544static void mlx5_ib_vma_open(struct vm_area_struct *area)
1545{
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555 area->vm_ops = NULL;
1556}
1557
1558static void mlx5_ib_vma_close(struct vm_area_struct *area)
1559{
1560 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1573
1574
1575
1576
1577
1578 mlx5_ib_vma_priv_data->vma = NULL;
1579 list_del(&mlx5_ib_vma_priv_data->list);
1580 kfree(mlx5_ib_vma_priv_data);
1581}
1582
1583static const struct vm_operations_struct mlx5_ib_vm_ops = {
1584 .open = mlx5_ib_vma_open,
1585 .close = mlx5_ib_vma_close
1586};
1587
1588static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1589 struct mlx5_ib_ucontext *ctx)
1590{
1591 struct mlx5_ib_vma_private_data *vma_prv;
1592 struct list_head *vma_head = &ctx->vma_private_list;
1593
1594 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1595 if (!vma_prv)
1596 return -ENOMEM;
1597
1598 vma_prv->vma = vma;
1599 vma->vm_private_data = vma_prv;
1600 vma->vm_ops = &mlx5_ib_vm_ops;
1601
1602 list_add(&vma_prv->list, vma_head);
1603
1604 return 0;
1605}
1606
1607static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1608{
1609 int ret;
1610 struct vm_area_struct *vma;
1611 struct mlx5_ib_vma_private_data *vma_private, *n;
1612 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1613 struct task_struct *owning_process = NULL;
1614 struct mm_struct *owning_mm = NULL;
1615
1616 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1617 if (!owning_process)
1618 return;
1619
1620 owning_mm = get_task_mm(owning_process);
1621 if (!owning_mm) {
1622 pr_info("no mm, disassociate ucontext is pending task termination\n");
1623 while (1) {
1624 put_task_struct(owning_process);
1625 usleep_range(1000, 2000);
1626 owning_process = get_pid_task(ibcontext->tgid,
1627 PIDTYPE_PID);
1628 if (!owning_process ||
1629 owning_process->state == TASK_DEAD) {
1630 pr_info("disassociate ucontext done, task was terminated\n");
1631
1632
1633
1634 if (owning_process)
1635 put_task_struct(owning_process);
1636 return;
1637 }
1638 }
1639 }
1640
1641
1642
1643
1644 down_write(&owning_mm->mmap_sem);
1645 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1646 list) {
1647 vma = vma_private->vma;
1648 ret = zap_vma_ptes(vma, vma->vm_start,
1649 PAGE_SIZE);
1650 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1651
1652
1653
1654 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1655 vma->vm_ops = NULL;
1656 list_del(&vma_private->list);
1657 kfree(vma_private);
1658 }
1659 up_write(&owning_mm->mmap_sem);
1660 mmput(owning_mm);
1661 put_task_struct(owning_process);
1662}
1663
1664static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1665{
1666 switch (cmd) {
1667 case MLX5_IB_MMAP_WC_PAGE:
1668 return "WC";
1669 case MLX5_IB_MMAP_REGULAR_PAGE:
1670 return "best effort WC";
1671 case MLX5_IB_MMAP_NC_PAGE:
1672 return "NC";
1673 default:
1674 return NULL;
1675 }
1676}
1677
1678static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1679 struct vm_area_struct *vma,
1680 struct mlx5_ib_ucontext *context)
1681{
1682 struct mlx5_bfreg_info *bfregi = &context->bfregi;
1683 int err;
1684 unsigned long idx;
1685 phys_addr_t pfn, pa;
1686 pgprot_t prot;
1687 int uars_per_page;
1688
1689 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1690 return -EINVAL;
1691
1692 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1693 idx = get_index(vma->vm_pgoff);
1694 if (idx % uars_per_page ||
1695 idx * uars_per_page >= bfregi->num_sys_pages) {
1696 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1697 return -EINVAL;
1698 }
1699
1700 switch (cmd) {
1701 case MLX5_IB_MMAP_WC_PAGE:
1702
1703#if defined(CONFIG_X86)
1704 if (!pat_enabled())
1705 return -EPERM;
1706#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1707 return -EPERM;
1708#endif
1709
1710 case MLX5_IB_MMAP_REGULAR_PAGE:
1711
1712 prot = pgprot_writecombine(vma->vm_page_prot);
1713 break;
1714 case MLX5_IB_MMAP_NC_PAGE:
1715 prot = pgprot_noncached(vma->vm_page_prot);
1716 break;
1717 default:
1718 return -EINVAL;
1719 }
1720
1721 pfn = uar_index2pfn(dev, bfregi, idx);
1722 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1723
1724 vma->vm_page_prot = prot;
1725 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1726 PAGE_SIZE, vma->vm_page_prot);
1727 if (err) {
1728 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1729 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1730 return -EAGAIN;
1731 }
1732
1733 pa = pfn << PAGE_SHIFT;
1734 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1735 vma->vm_start, &pa);
1736
1737 return mlx5_ib_set_vma_data(vma, context);
1738}
1739
1740static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1741{
1742 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1743 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1744 unsigned long command;
1745 phys_addr_t pfn;
1746
1747 command = get_command(vma->vm_pgoff);
1748 switch (command) {
1749 case MLX5_IB_MMAP_WC_PAGE:
1750 case MLX5_IB_MMAP_NC_PAGE:
1751 case MLX5_IB_MMAP_REGULAR_PAGE:
1752 return uar_mmap(dev, command, vma, context);
1753
1754 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1755 return -ENOSYS;
1756
1757 case MLX5_IB_MMAP_CORE_CLOCK:
1758 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1759 return -EINVAL;
1760
1761 if (vma->vm_flags & VM_WRITE)
1762 return -EPERM;
1763
1764
1765 if (PAGE_SIZE > 4096)
1766 return -EOPNOTSUPP;
1767
1768 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1769 pfn = (dev->mdev->iseg_base +
1770 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1771 PAGE_SHIFT;
1772 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1773 PAGE_SIZE, vma->vm_page_prot))
1774 return -EAGAIN;
1775
1776 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1777 vma->vm_start,
1778 (unsigned long long)pfn << PAGE_SHIFT);
1779 break;
1780
1781 default:
1782 return -EINVAL;
1783 }
1784
1785 return 0;
1786}
1787
1788static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1789 struct ib_ucontext *context,
1790 struct ib_udata *udata)
1791{
1792 struct mlx5_ib_alloc_pd_resp resp;
1793 struct mlx5_ib_pd *pd;
1794 int err;
1795
1796 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1797 if (!pd)
1798 return ERR_PTR(-ENOMEM);
1799
1800 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1801 if (err) {
1802 kfree(pd);
1803 return ERR_PTR(err);
1804 }
1805
1806 if (context) {
1807 resp.pdn = pd->pdn;
1808 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1809 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1810 kfree(pd);
1811 return ERR_PTR(-EFAULT);
1812 }
1813 }
1814
1815 return &pd->ibpd;
1816}
1817
1818static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1819{
1820 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1821 struct mlx5_ib_pd *mpd = to_mpd(pd);
1822
1823 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1824 kfree(mpd);
1825
1826 return 0;
1827}
1828
1829enum {
1830 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1831 MATCH_CRITERIA_ENABLE_MISC_BIT,
1832 MATCH_CRITERIA_ENABLE_INNER_BIT
1833};
1834
1835#define HEADER_IS_ZERO(match_criteria, headers) \
1836 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1837 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1838
1839static u8 get_match_criteria_enable(u32 *match_criteria)
1840{
1841 u8 match_criteria_enable;
1842
1843 match_criteria_enable =
1844 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1845 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1846 match_criteria_enable |=
1847 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1848 MATCH_CRITERIA_ENABLE_MISC_BIT;
1849 match_criteria_enable |=
1850 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1851 MATCH_CRITERIA_ENABLE_INNER_BIT;
1852
1853 return match_criteria_enable;
1854}
1855
1856static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1857{
1858 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1859 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1860}
1861
1862static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1863 bool inner)
1864{
1865 if (inner) {
1866 MLX5_SET(fte_match_set_misc,
1867 misc_c, inner_ipv6_flow_label, mask);
1868 MLX5_SET(fte_match_set_misc,
1869 misc_v, inner_ipv6_flow_label, val);
1870 } else {
1871 MLX5_SET(fte_match_set_misc,
1872 misc_c, outer_ipv6_flow_label, mask);
1873 MLX5_SET(fte_match_set_misc,
1874 misc_v, outer_ipv6_flow_label, val);
1875 }
1876}
1877
1878static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1879{
1880 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1881 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1882 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1883 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1884}
1885
1886#define LAST_ETH_FIELD vlan_tag
1887#define LAST_IB_FIELD sl
1888#define LAST_IPV4_FIELD tos
1889#define LAST_IPV6_FIELD traffic_class
1890#define LAST_TCP_UDP_FIELD src_port
1891#define LAST_TUNNEL_FIELD tunnel_id
1892#define LAST_FLOW_TAG_FIELD tag_id
1893#define LAST_DROP_FIELD size
1894
1895
1896#define FIELDS_NOT_SUPPORTED(filter, field)\
1897 memchr_inv((void *)&filter.field +\
1898 sizeof(filter.field), 0,\
1899 sizeof(filter) -\
1900 offsetof(typeof(filter), field) -\
1901 sizeof(filter.field))
1902
1903#define IPV4_VERSION 4
1904#define IPV6_VERSION 6
1905static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
1906 u32 *match_v, const union ib_flow_spec *ib_spec,
1907 u32 *tag_id, bool *is_drop)
1908{
1909 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1910 misc_parameters);
1911 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1912 misc_parameters);
1913 void *headers_c;
1914 void *headers_v;
1915 int match_ipv;
1916
1917 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1918 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1919 inner_headers);
1920 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1921 inner_headers);
1922 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1923 ft_field_support.inner_ip_version);
1924 } else {
1925 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1926 outer_headers);
1927 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1928 outer_headers);
1929 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1930 ft_field_support.outer_ip_version);
1931 }
1932
1933 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
1934 case IB_FLOW_SPEC_ETH:
1935 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1936 return -EOPNOTSUPP;
1937
1938 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1939 dmac_47_16),
1940 ib_spec->eth.mask.dst_mac);
1941 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1942 dmac_47_16),
1943 ib_spec->eth.val.dst_mac);
1944
1945 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1946 smac_47_16),
1947 ib_spec->eth.mask.src_mac);
1948 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1949 smac_47_16),
1950 ib_spec->eth.val.src_mac);
1951
1952 if (ib_spec->eth.mask.vlan_tag) {
1953 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1954 cvlan_tag, 1);
1955 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1956 cvlan_tag, 1);
1957
1958 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1959 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1960 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1961 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1962
1963 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1964 first_cfi,
1965 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1966 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1967 first_cfi,
1968 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1969
1970 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1971 first_prio,
1972 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1973 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1974 first_prio,
1975 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1976 }
1977 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1978 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1979 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1980 ethertype, ntohs(ib_spec->eth.val.ether_type));
1981 break;
1982 case IB_FLOW_SPEC_IPV4:
1983 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1984 return -EOPNOTSUPP;
1985
1986 if (match_ipv) {
1987 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1988 ip_version, 0xf);
1989 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1990 ip_version, IPV4_VERSION);
1991 } else {
1992 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1993 ethertype, 0xffff);
1994 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1995 ethertype, ETH_P_IP);
1996 }
1997
1998 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1999 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2000 &ib_spec->ipv4.mask.src_ip,
2001 sizeof(ib_spec->ipv4.mask.src_ip));
2002 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2003 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2004 &ib_spec->ipv4.val.src_ip,
2005 sizeof(ib_spec->ipv4.val.src_ip));
2006 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2007 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2008 &ib_spec->ipv4.mask.dst_ip,
2009 sizeof(ib_spec->ipv4.mask.dst_ip));
2010 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2011 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2012 &ib_spec->ipv4.val.dst_ip,
2013 sizeof(ib_spec->ipv4.val.dst_ip));
2014
2015 set_tos(headers_c, headers_v,
2016 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2017
2018 set_proto(headers_c, headers_v,
2019 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2020 break;
2021 case IB_FLOW_SPEC_IPV6:
2022 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2023 return -EOPNOTSUPP;
2024
2025 if (match_ipv) {
2026 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2027 ip_version, 0xf);
2028 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2029 ip_version, IPV6_VERSION);
2030 } else {
2031 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2032 ethertype, 0xffff);
2033 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2034 ethertype, ETH_P_IPV6);
2035 }
2036
2037 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2038 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2039 &ib_spec->ipv6.mask.src_ip,
2040 sizeof(ib_spec->ipv6.mask.src_ip));
2041 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2042 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2043 &ib_spec->ipv6.val.src_ip,
2044 sizeof(ib_spec->ipv6.val.src_ip));
2045 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2046 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2047 &ib_spec->ipv6.mask.dst_ip,
2048 sizeof(ib_spec->ipv6.mask.dst_ip));
2049 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2050 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2051 &ib_spec->ipv6.val.dst_ip,
2052 sizeof(ib_spec->ipv6.val.dst_ip));
2053
2054 set_tos(headers_c, headers_v,
2055 ib_spec->ipv6.mask.traffic_class,
2056 ib_spec->ipv6.val.traffic_class);
2057
2058 set_proto(headers_c, headers_v,
2059 ib_spec->ipv6.mask.next_hdr,
2060 ib_spec->ipv6.val.next_hdr);
2061
2062 set_flow_label(misc_params_c, misc_params_v,
2063 ntohl(ib_spec->ipv6.mask.flow_label),
2064 ntohl(ib_spec->ipv6.val.flow_label),
2065 ib_spec->type & IB_FLOW_SPEC_INNER);
2066
2067 break;
2068 case IB_FLOW_SPEC_TCP:
2069 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2070 LAST_TCP_UDP_FIELD))
2071 return -EOPNOTSUPP;
2072
2073 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2074 0xff);
2075 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2076 IPPROTO_TCP);
2077
2078 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2079 ntohs(ib_spec->tcp_udp.mask.src_port));
2080 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2081 ntohs(ib_spec->tcp_udp.val.src_port));
2082
2083 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2084 ntohs(ib_spec->tcp_udp.mask.dst_port));
2085 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2086 ntohs(ib_spec->tcp_udp.val.dst_port));
2087 break;
2088 case IB_FLOW_SPEC_UDP:
2089 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2090 LAST_TCP_UDP_FIELD))
2091 return -EOPNOTSUPP;
2092
2093 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2094 0xff);
2095 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2096 IPPROTO_UDP);
2097
2098 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2099 ntohs(ib_spec->tcp_udp.mask.src_port));
2100 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2101 ntohs(ib_spec->tcp_udp.val.src_port));
2102
2103 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2104 ntohs(ib_spec->tcp_udp.mask.dst_port));
2105 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2106 ntohs(ib_spec->tcp_udp.val.dst_port));
2107 break;
2108 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2109 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2110 LAST_TUNNEL_FIELD))
2111 return -EOPNOTSUPP;
2112
2113 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2114 ntohl(ib_spec->tunnel.mask.tunnel_id));
2115 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2116 ntohl(ib_spec->tunnel.val.tunnel_id));
2117 break;
2118 case IB_FLOW_SPEC_ACTION_TAG:
2119 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2120 LAST_FLOW_TAG_FIELD))
2121 return -EOPNOTSUPP;
2122 if (ib_spec->flow_tag.tag_id >= BIT(24))
2123 return -EINVAL;
2124
2125 *tag_id = ib_spec->flow_tag.tag_id;
2126 break;
2127 case IB_FLOW_SPEC_ACTION_DROP:
2128 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2129 LAST_DROP_FIELD))
2130 return -EOPNOTSUPP;
2131 *is_drop = true;
2132 break;
2133 default:
2134 return -EINVAL;
2135 }
2136
2137 return 0;
2138}
2139
2140
2141
2142
2143
2144static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2145{
2146 union ib_flow_spec *flow_spec;
2147
2148 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2149 ib_attr->num_of_specs < 1)
2150 return false;
2151
2152 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2153 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2154 struct ib_flow_spec_ipv4 *ipv4_spec;
2155
2156 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2157 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2158 return true;
2159
2160 return false;
2161 }
2162
2163 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2164 struct ib_flow_spec_eth *eth_spec;
2165
2166 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2167 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2168 is_multicast_ether_addr(eth_spec->val.dst_mac);
2169 }
2170
2171 return false;
2172}
2173
2174static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2175 const struct ib_flow_attr *flow_attr,
2176 bool check_inner)
2177{
2178 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2179 int match_ipv = check_inner ?
2180 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2181 ft_field_support.inner_ip_version) :
2182 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2183 ft_field_support.outer_ip_version);
2184 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2185 bool ipv4_spec_valid, ipv6_spec_valid;
2186 unsigned int ip_spec_type = 0;
2187 bool has_ethertype = false;
2188 unsigned int spec_index;
2189 bool mask_valid = true;
2190 u16 eth_type = 0;
2191 bool type_valid;
2192
2193
2194 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2195 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2196 ib_spec->eth.mask.ether_type) {
2197 mask_valid = (ib_spec->eth.mask.ether_type ==
2198 htons(0xffff));
2199 has_ethertype = true;
2200 eth_type = ntohs(ib_spec->eth.val.ether_type);
2201 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2202 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2203 ip_spec_type = ib_spec->type;
2204 }
2205 ib_spec = (void *)ib_spec + ib_spec->size;
2206 }
2207
2208 type_valid = (!has_ethertype) || (!ip_spec_type);
2209 if (!type_valid && mask_valid) {
2210 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2211 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2212 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2213 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2214
2215 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2216 (((eth_type == ETH_P_MPLS_UC) ||
2217 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2218 }
2219
2220 return type_valid;
2221}
2222
2223static bool is_valid_attr(struct mlx5_core_dev *mdev,
2224 const struct ib_flow_attr *flow_attr)
2225{
2226 return is_valid_ethertype(mdev, flow_attr, false) &&
2227 is_valid_ethertype(mdev, flow_attr, true);
2228}
2229
2230static void put_flow_table(struct mlx5_ib_dev *dev,
2231 struct mlx5_ib_flow_prio *prio, bool ft_added)
2232{
2233 prio->refcount -= !!ft_added;
2234 if (!prio->refcount) {
2235 mlx5_destroy_flow_table(prio->flow_table);
2236 prio->flow_table = NULL;
2237 }
2238}
2239
2240static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2241{
2242 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2243 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2244 struct mlx5_ib_flow_handler,
2245 ibflow);
2246 struct mlx5_ib_flow_handler *iter, *tmp;
2247
2248 mutex_lock(&dev->flow_db.lock);
2249
2250 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2251 mlx5_del_flow_rules(iter->rule);
2252 put_flow_table(dev, iter->prio, true);
2253 list_del(&iter->list);
2254 kfree(iter);
2255 }
2256
2257 mlx5_del_flow_rules(handler->rule);
2258 put_flow_table(dev, handler->prio, true);
2259 mutex_unlock(&dev->flow_db.lock);
2260
2261 kfree(handler);
2262
2263 return 0;
2264}
2265
2266static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2267{
2268 priority *= 2;
2269 if (!dont_trap)
2270 priority++;
2271 return priority;
2272}
2273
2274enum flow_table_type {
2275 MLX5_IB_FT_RX,
2276 MLX5_IB_FT_TX
2277};
2278
2279#define MLX5_FS_MAX_TYPES 6
2280#define MLX5_FS_MAX_ENTRIES BIT(16)
2281static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2282 struct ib_flow_attr *flow_attr,
2283 enum flow_table_type ft_type)
2284{
2285 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2286 struct mlx5_flow_namespace *ns = NULL;
2287 struct mlx5_ib_flow_prio *prio;
2288 struct mlx5_flow_table *ft;
2289 int max_table_size;
2290 int num_entries;
2291 int num_groups;
2292 int priority;
2293 int err = 0;
2294
2295 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2296 log_max_ft_size));
2297 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2298 if (flow_is_multicast_only(flow_attr) &&
2299 !dont_trap)
2300 priority = MLX5_IB_FLOW_MCAST_PRIO;
2301 else
2302 priority = ib_prio_to_core_prio(flow_attr->priority,
2303 dont_trap);
2304 ns = mlx5_get_flow_namespace(dev->mdev,
2305 MLX5_FLOW_NAMESPACE_BYPASS);
2306 num_entries = MLX5_FS_MAX_ENTRIES;
2307 num_groups = MLX5_FS_MAX_TYPES;
2308 prio = &dev->flow_db.prios[priority];
2309 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2310 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2311 ns = mlx5_get_flow_namespace(dev->mdev,
2312 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2313 build_leftovers_ft_param(&priority,
2314 &num_entries,
2315 &num_groups);
2316 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2317 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2318 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2319 allow_sniffer_and_nic_rx_shared_tir))
2320 return ERR_PTR(-ENOTSUPP);
2321
2322 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2323 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2324 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2325
2326 prio = &dev->flow_db.sniffer[ft_type];
2327 priority = 0;
2328 num_entries = 1;
2329 num_groups = 1;
2330 }
2331
2332 if (!ns)
2333 return ERR_PTR(-ENOTSUPP);
2334
2335 if (num_entries > max_table_size)
2336 return ERR_PTR(-ENOMEM);
2337
2338 ft = prio->flow_table;
2339 if (!ft) {
2340 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2341 num_entries,
2342 num_groups,
2343 0, 0);
2344
2345 if (!IS_ERR(ft)) {
2346 prio->refcount = 0;
2347 prio->flow_table = ft;
2348 } else {
2349 err = PTR_ERR(ft);
2350 }
2351 }
2352
2353 return err ? ERR_PTR(err) : prio;
2354}
2355
2356static void set_underlay_qp(struct mlx5_ib_dev *dev,
2357 struct mlx5_flow_spec *spec,
2358 u32 underlay_qpn)
2359{
2360 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2361 spec->match_criteria,
2362 misc_parameters);
2363 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2364 misc_parameters);
2365
2366 if (underlay_qpn &&
2367 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2368 ft_field_support.bth_dst_qp)) {
2369 MLX5_SET(fte_match_set_misc,
2370 misc_params_v, bth_dst_qp, underlay_qpn);
2371 MLX5_SET(fte_match_set_misc,
2372 misc_params_c, bth_dst_qp, 0xffffff);
2373 }
2374}
2375
2376static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2377 struct mlx5_ib_flow_prio *ft_prio,
2378 const struct ib_flow_attr *flow_attr,
2379 struct mlx5_flow_destination *dst,
2380 u32 underlay_qpn)
2381{
2382 struct mlx5_flow_table *ft = ft_prio->flow_table;
2383 struct mlx5_ib_flow_handler *handler;
2384 struct mlx5_flow_act flow_act = {0};
2385 struct mlx5_flow_spec *spec;
2386 struct mlx5_flow_destination *rule_dst = dst;
2387 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2388 unsigned int spec_index;
2389 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2390 bool is_drop = false;
2391 int err = 0;
2392 int dest_num = 1;
2393
2394 if (!is_valid_attr(dev->mdev, flow_attr))
2395 return ERR_PTR(-EINVAL);
2396
2397 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2398 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2399 if (!handler || !spec) {
2400 err = -ENOMEM;
2401 goto free;
2402 }
2403
2404 INIT_LIST_HEAD(&handler->list);
2405
2406 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2407 err = parse_flow_attr(dev->mdev, spec->match_criteria,
2408 spec->match_value,
2409 ib_flow, &flow_tag, &is_drop);
2410 if (err < 0)
2411 goto free;
2412
2413 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2414 }
2415
2416 if (!flow_is_multicast_only(flow_attr))
2417 set_underlay_qp(dev, spec, underlay_qpn);
2418
2419 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2420 if (is_drop) {
2421 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2422 rule_dst = NULL;
2423 dest_num = 0;
2424 } else {
2425 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2426 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2427 }
2428
2429 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2430 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2431 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2432 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2433 flow_tag, flow_attr->type);
2434 err = -EINVAL;
2435 goto free;
2436 }
2437 flow_act.flow_tag = flow_tag;
2438 handler->rule = mlx5_add_flow_rules(ft, spec,
2439 &flow_act,
2440 rule_dst, dest_num);
2441
2442 if (IS_ERR(handler->rule)) {
2443 err = PTR_ERR(handler->rule);
2444 goto free;
2445 }
2446
2447 ft_prio->refcount++;
2448 handler->prio = ft_prio;
2449
2450 ft_prio->flow_table = ft;
2451free:
2452 if (err)
2453 kfree(handler);
2454 kvfree(spec);
2455 return err ? ERR_PTR(err) : handler;
2456}
2457
2458static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2459 struct mlx5_ib_flow_prio *ft_prio,
2460 const struct ib_flow_attr *flow_attr,
2461 struct mlx5_flow_destination *dst)
2462{
2463 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2464}
2465
2466static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2467 struct mlx5_ib_flow_prio *ft_prio,
2468 struct ib_flow_attr *flow_attr,
2469 struct mlx5_flow_destination *dst)
2470{
2471 struct mlx5_ib_flow_handler *handler_dst = NULL;
2472 struct mlx5_ib_flow_handler *handler = NULL;
2473
2474 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2475 if (!IS_ERR(handler)) {
2476 handler_dst = create_flow_rule(dev, ft_prio,
2477 flow_attr, dst);
2478 if (IS_ERR(handler_dst)) {
2479 mlx5_del_flow_rules(handler->rule);
2480 ft_prio->refcount--;
2481 kfree(handler);
2482 handler = handler_dst;
2483 } else {
2484 list_add(&handler_dst->list, &handler->list);
2485 }
2486 }
2487
2488 return handler;
2489}
2490enum {
2491 LEFTOVERS_MC,
2492 LEFTOVERS_UC,
2493};
2494
2495static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2496 struct mlx5_ib_flow_prio *ft_prio,
2497 struct ib_flow_attr *flow_attr,
2498 struct mlx5_flow_destination *dst)
2499{
2500 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2501 struct mlx5_ib_flow_handler *handler = NULL;
2502
2503 static struct {
2504 struct ib_flow_attr flow_attr;
2505 struct ib_flow_spec_eth eth_flow;
2506 } leftovers_specs[] = {
2507 [LEFTOVERS_MC] = {
2508 .flow_attr = {
2509 .num_of_specs = 1,
2510 .size = sizeof(leftovers_specs[0])
2511 },
2512 .eth_flow = {
2513 .type = IB_FLOW_SPEC_ETH,
2514 .size = sizeof(struct ib_flow_spec_eth),
2515 .mask = {.dst_mac = {0x1} },
2516 .val = {.dst_mac = {0x1} }
2517 }
2518 },
2519 [LEFTOVERS_UC] = {
2520 .flow_attr = {
2521 .num_of_specs = 1,
2522 .size = sizeof(leftovers_specs[0])
2523 },
2524 .eth_flow = {
2525 .type = IB_FLOW_SPEC_ETH,
2526 .size = sizeof(struct ib_flow_spec_eth),
2527 .mask = {.dst_mac = {0x1} },
2528 .val = {.dst_mac = {} }
2529 }
2530 }
2531 };
2532
2533 handler = create_flow_rule(dev, ft_prio,
2534 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2535 dst);
2536 if (!IS_ERR(handler) &&
2537 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2538 handler_ucast = create_flow_rule(dev, ft_prio,
2539 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2540 dst);
2541 if (IS_ERR(handler_ucast)) {
2542 mlx5_del_flow_rules(handler->rule);
2543 ft_prio->refcount--;
2544 kfree(handler);
2545 handler = handler_ucast;
2546 } else {
2547 list_add(&handler_ucast->list, &handler->list);
2548 }
2549 }
2550
2551 return handler;
2552}
2553
2554static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2555 struct mlx5_ib_flow_prio *ft_rx,
2556 struct mlx5_ib_flow_prio *ft_tx,
2557 struct mlx5_flow_destination *dst)
2558{
2559 struct mlx5_ib_flow_handler *handler_rx;
2560 struct mlx5_ib_flow_handler *handler_tx;
2561 int err;
2562 static const struct ib_flow_attr flow_attr = {
2563 .num_of_specs = 0,
2564 .size = sizeof(flow_attr)
2565 };
2566
2567 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2568 if (IS_ERR(handler_rx)) {
2569 err = PTR_ERR(handler_rx);
2570 goto err;
2571 }
2572
2573 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2574 if (IS_ERR(handler_tx)) {
2575 err = PTR_ERR(handler_tx);
2576 goto err_tx;
2577 }
2578
2579 list_add(&handler_tx->list, &handler_rx->list);
2580
2581 return handler_rx;
2582
2583err_tx:
2584 mlx5_del_flow_rules(handler_rx->rule);
2585 ft_rx->refcount--;
2586 kfree(handler_rx);
2587err:
2588 return ERR_PTR(err);
2589}
2590
2591static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2592 struct ib_flow_attr *flow_attr,
2593 int domain)
2594{
2595 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2596 struct mlx5_ib_qp *mqp = to_mqp(qp);
2597 struct mlx5_ib_flow_handler *handler = NULL;
2598 struct mlx5_flow_destination *dst = NULL;
2599 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2600 struct mlx5_ib_flow_prio *ft_prio;
2601 int err;
2602 int underlay_qpn;
2603
2604 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2605 return ERR_PTR(-ENOMEM);
2606
2607 if (domain != IB_FLOW_DOMAIN_USER ||
2608 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2609 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2610 return ERR_PTR(-EINVAL);
2611
2612 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2613 if (!dst)
2614 return ERR_PTR(-ENOMEM);
2615
2616 mutex_lock(&dev->flow_db.lock);
2617
2618 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2619 if (IS_ERR(ft_prio)) {
2620 err = PTR_ERR(ft_prio);
2621 goto unlock;
2622 }
2623 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2624 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2625 if (IS_ERR(ft_prio_tx)) {
2626 err = PTR_ERR(ft_prio_tx);
2627 ft_prio_tx = NULL;
2628 goto destroy_ft;
2629 }
2630 }
2631
2632 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2633 if (mqp->flags & MLX5_IB_QP_RSS)
2634 dst->tir_num = mqp->rss_qp.tirn;
2635 else
2636 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2637
2638 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2639 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2640 handler = create_dont_trap_rule(dev, ft_prio,
2641 flow_attr, dst);
2642 } else {
2643 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
2644 mqp->underlay_qpn : 0;
2645 handler = _create_flow_rule(dev, ft_prio, flow_attr,
2646 dst, underlay_qpn);
2647 }
2648 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2649 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2650 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2651 dst);
2652 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2653 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2654 } else {
2655 err = -EINVAL;
2656 goto destroy_ft;
2657 }
2658
2659 if (IS_ERR(handler)) {
2660 err = PTR_ERR(handler);
2661 handler = NULL;
2662 goto destroy_ft;
2663 }
2664
2665 mutex_unlock(&dev->flow_db.lock);
2666 kfree(dst);
2667
2668 return &handler->ibflow;
2669
2670destroy_ft:
2671 put_flow_table(dev, ft_prio, false);
2672 if (ft_prio_tx)
2673 put_flow_table(dev, ft_prio_tx, false);
2674unlock:
2675 mutex_unlock(&dev->flow_db.lock);
2676 kfree(dst);
2677 kfree(handler);
2678 return ERR_PTR(err);
2679}
2680
2681static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2682{
2683 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2684 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
2685 int err;
2686
2687 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
2688 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2689 return -EOPNOTSUPP;
2690 }
2691
2692 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2693 if (err)
2694 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2695 ibqp->qp_num, gid->raw);
2696
2697 return err;
2698}
2699
2700static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2701{
2702 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2703 int err;
2704
2705 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2706 if (err)
2707 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2708 ibqp->qp_num, gid->raw);
2709
2710 return err;
2711}
2712
2713static int init_node_data(struct mlx5_ib_dev *dev)
2714{
2715 int err;
2716
2717 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2718 if (err)
2719 return err;
2720
2721 dev->mdev->rev_id = dev->mdev->pdev->revision;
2722
2723 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2724}
2725
2726static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2727 char *buf)
2728{
2729 struct mlx5_ib_dev *dev =
2730 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2731
2732 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2733}
2734
2735static ssize_t show_reg_pages(struct device *device,
2736 struct device_attribute *attr, char *buf)
2737{
2738 struct mlx5_ib_dev *dev =
2739 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2740
2741 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2742}
2743
2744static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2745 char *buf)
2746{
2747 struct mlx5_ib_dev *dev =
2748 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2749 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2750}
2751
2752static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2753 char *buf)
2754{
2755 struct mlx5_ib_dev *dev =
2756 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2757 return sprintf(buf, "%x\n", dev->mdev->rev_id);
2758}
2759
2760static ssize_t show_board(struct device *device, struct device_attribute *attr,
2761 char *buf)
2762{
2763 struct mlx5_ib_dev *dev =
2764 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2765 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2766 dev->mdev->board_id);
2767}
2768
2769static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2770static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2771static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2772static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2773static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2774
2775static struct device_attribute *mlx5_class_attributes[] = {
2776 &dev_attr_hw_rev,
2777 &dev_attr_hca_type,
2778 &dev_attr_board_id,
2779 &dev_attr_fw_pages,
2780 &dev_attr_reg_pages,
2781};
2782
2783static void pkey_change_handler(struct work_struct *work)
2784{
2785 struct mlx5_ib_port_resources *ports =
2786 container_of(work, struct mlx5_ib_port_resources,
2787 pkey_change_work);
2788
2789 mutex_lock(&ports->devr->mutex);
2790 mlx5_ib_gsi_pkey_change(ports->gsi);
2791 mutex_unlock(&ports->devr->mutex);
2792}
2793
2794static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2795{
2796 struct mlx5_ib_qp *mqp;
2797 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2798 struct mlx5_core_cq *mcq;
2799 struct list_head cq_armed_list;
2800 unsigned long flags_qp;
2801 unsigned long flags_cq;
2802 unsigned long flags;
2803
2804 INIT_LIST_HEAD(&cq_armed_list);
2805
2806
2807 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2808 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2809 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2810 if (mqp->sq.tail != mqp->sq.head) {
2811 send_mcq = to_mcq(mqp->ibqp.send_cq);
2812 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2813 if (send_mcq->mcq.comp &&
2814 mqp->ibqp.send_cq->comp_handler) {
2815 if (!send_mcq->mcq.reset_notify_added) {
2816 send_mcq->mcq.reset_notify_added = 1;
2817 list_add_tail(&send_mcq->mcq.reset_notify,
2818 &cq_armed_list);
2819 }
2820 }
2821 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2822 }
2823 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2824 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2825
2826 if (!mqp->ibqp.srq) {
2827 if (mqp->rq.tail != mqp->rq.head) {
2828 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2829 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2830 if (recv_mcq->mcq.comp &&
2831 mqp->ibqp.recv_cq->comp_handler) {
2832 if (!recv_mcq->mcq.reset_notify_added) {
2833 recv_mcq->mcq.reset_notify_added = 1;
2834 list_add_tail(&recv_mcq->mcq.reset_notify,
2835 &cq_armed_list);
2836 }
2837 }
2838 spin_unlock_irqrestore(&recv_mcq->lock,
2839 flags_cq);
2840 }
2841 }
2842 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2843 }
2844
2845
2846
2847 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2848 mcq->comp(mcq);
2849 }
2850 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2851}
2852
2853static void delay_drop_handler(struct work_struct *work)
2854{
2855 int err;
2856 struct mlx5_ib_delay_drop *delay_drop =
2857 container_of(work, struct mlx5_ib_delay_drop,
2858 delay_drop_work);
2859
2860 atomic_inc(&delay_drop->events_cnt);
2861
2862 mutex_lock(&delay_drop->lock);
2863 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
2864 delay_drop->timeout);
2865 if (err) {
2866 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2867 delay_drop->timeout);
2868 delay_drop->activate = false;
2869 }
2870 mutex_unlock(&delay_drop->lock);
2871}
2872
2873static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2874 enum mlx5_dev_event event, unsigned long param)
2875{
2876 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2877 struct ib_event ibev;
2878 bool fatal = false;
2879 u8 port = 0;
2880
2881 switch (event) {
2882 case MLX5_DEV_EVENT_SYS_ERROR:
2883 ibev.event = IB_EVENT_DEVICE_FATAL;
2884 mlx5_ib_handle_internal_error(ibdev);
2885 fatal = true;
2886 break;
2887
2888 case MLX5_DEV_EVENT_PORT_UP:
2889 case MLX5_DEV_EVENT_PORT_DOWN:
2890 case MLX5_DEV_EVENT_PORT_INITIALIZED:
2891 port = (u8)param;
2892
2893
2894
2895
2896 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2897 IB_LINK_LAYER_ETHERNET)
2898 return;
2899
2900 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2901 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2902 break;
2903
2904 case MLX5_DEV_EVENT_LID_CHANGE:
2905 ibev.event = IB_EVENT_LID_CHANGE;
2906 port = (u8)param;
2907 break;
2908
2909 case MLX5_DEV_EVENT_PKEY_CHANGE:
2910 ibev.event = IB_EVENT_PKEY_CHANGE;
2911 port = (u8)param;
2912
2913 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2914 break;
2915
2916 case MLX5_DEV_EVENT_GUID_CHANGE:
2917 ibev.event = IB_EVENT_GID_CHANGE;
2918 port = (u8)param;
2919 break;
2920
2921 case MLX5_DEV_EVENT_CLIENT_REREG:
2922 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2923 port = (u8)param;
2924 break;
2925 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
2926 schedule_work(&ibdev->delay_drop.delay_drop_work);
2927 goto out;
2928 default:
2929 goto out;
2930 }
2931
2932 ibev.device = &ibdev->ib_dev;
2933 ibev.element.port_num = port;
2934
2935 if (port < 1 || port > ibdev->num_ports) {
2936 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2937 goto out;
2938 }
2939
2940 if (ibdev->ib_active)
2941 ib_dispatch_event(&ibev);
2942
2943 if (fatal)
2944 ibdev->ib_active = false;
2945
2946out:
2947 return;
2948}
2949
2950static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2951{
2952 struct mlx5_hca_vport_context vport_ctx;
2953 int err;
2954 int port;
2955
2956 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2957 dev->mdev->port_caps[port - 1].has_smi = false;
2958 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2959 MLX5_CAP_PORT_TYPE_IB) {
2960 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2961 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2962 port, 0,
2963 &vport_ctx);
2964 if (err) {
2965 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2966 port, err);
2967 return err;
2968 }
2969 dev->mdev->port_caps[port - 1].has_smi =
2970 vport_ctx.has_smi;
2971 } else {
2972 dev->mdev->port_caps[port - 1].has_smi = true;
2973 }
2974 }
2975 }
2976 return 0;
2977}
2978
2979static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2980{
2981 int port;
2982
2983 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2984 mlx5_query_ext_port_caps(dev, port);
2985}
2986
2987static int get_port_caps(struct mlx5_ib_dev *dev)
2988{
2989 struct ib_device_attr *dprops = NULL;
2990 struct ib_port_attr *pprops = NULL;
2991 int err = -ENOMEM;
2992 int port;
2993 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2994
2995 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2996 if (!pprops)
2997 goto out;
2998
2999 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3000 if (!dprops)
3001 goto out;
3002
3003 err = set_has_smi_cap(dev);
3004 if (err)
3005 goto out;
3006
3007 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
3008 if (err) {
3009 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3010 goto out;
3011 }
3012
3013 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
3014 memset(pprops, 0, sizeof(*pprops));
3015 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3016 if (err) {
3017 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3018 port, err);
3019 break;
3020 }
3021 dev->mdev->port_caps[port - 1].pkey_table_len =
3022 dprops->max_pkeys;
3023 dev->mdev->port_caps[port - 1].gid_table_len =
3024 pprops->gid_tbl_len;
3025 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
3026 dprops->max_pkeys, pprops->gid_tbl_len);
3027 }
3028
3029out:
3030 kfree(pprops);
3031 kfree(dprops);
3032
3033 return err;
3034}
3035
3036static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3037{
3038 int err;
3039
3040 err = mlx5_mr_cache_cleanup(dev);
3041 if (err)
3042 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3043
3044 mlx5_ib_destroy_qp(dev->umrc.qp);
3045 ib_free_cq(dev->umrc.cq);
3046 ib_dealloc_pd(dev->umrc.pd);
3047}
3048
3049enum {
3050 MAX_UMR_WR = 128,
3051};
3052
3053static int create_umr_res(struct mlx5_ib_dev *dev)
3054{
3055 struct ib_qp_init_attr *init_attr = NULL;
3056 struct ib_qp_attr *attr = NULL;
3057 struct ib_pd *pd;
3058 struct ib_cq *cq;
3059 struct ib_qp *qp;
3060 int ret;
3061
3062 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3063 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3064 if (!attr || !init_attr) {
3065 ret = -ENOMEM;
3066 goto error_0;
3067 }
3068
3069 pd = ib_alloc_pd(&dev->ib_dev, 0);
3070 if (IS_ERR(pd)) {
3071 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3072 ret = PTR_ERR(pd);
3073 goto error_0;
3074 }
3075
3076 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
3077 if (IS_ERR(cq)) {
3078 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3079 ret = PTR_ERR(cq);
3080 goto error_2;
3081 }
3082
3083 init_attr->send_cq = cq;
3084 init_attr->recv_cq = cq;
3085 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3086 init_attr->cap.max_send_wr = MAX_UMR_WR;
3087 init_attr->cap.max_send_sge = 1;
3088 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3089 init_attr->port_num = 1;
3090 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3091 if (IS_ERR(qp)) {
3092 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3093 ret = PTR_ERR(qp);
3094 goto error_3;
3095 }
3096 qp->device = &dev->ib_dev;
3097 qp->real_qp = qp;
3098 qp->uobject = NULL;
3099 qp->qp_type = MLX5_IB_QPT_REG_UMR;
3100
3101 attr->qp_state = IB_QPS_INIT;
3102 attr->port_num = 1;
3103 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3104 IB_QP_PORT, NULL);
3105 if (ret) {
3106 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3107 goto error_4;
3108 }
3109
3110 memset(attr, 0, sizeof(*attr));
3111 attr->qp_state = IB_QPS_RTR;
3112 attr->path_mtu = IB_MTU_256;
3113
3114 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3115 if (ret) {
3116 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3117 goto error_4;
3118 }
3119
3120 memset(attr, 0, sizeof(*attr));
3121 attr->qp_state = IB_QPS_RTS;
3122 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3123 if (ret) {
3124 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3125 goto error_4;
3126 }
3127
3128 dev->umrc.qp = qp;
3129 dev->umrc.cq = cq;
3130 dev->umrc.pd = pd;
3131
3132 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3133 ret = mlx5_mr_cache_init(dev);
3134 if (ret) {
3135 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3136 goto error_4;
3137 }
3138
3139 kfree(attr);
3140 kfree(init_attr);
3141
3142 return 0;
3143
3144error_4:
3145 mlx5_ib_destroy_qp(qp);
3146
3147error_3:
3148 ib_free_cq(cq);
3149
3150error_2:
3151 ib_dealloc_pd(pd);
3152
3153error_0:
3154 kfree(attr);
3155 kfree(init_attr);
3156 return ret;
3157}
3158
3159static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3160{
3161 switch (umr_fence_cap) {
3162 case MLX5_CAP_UMR_FENCE_NONE:
3163 return MLX5_FENCE_MODE_NONE;
3164 case MLX5_CAP_UMR_FENCE_SMALL:
3165 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3166 default:
3167 return MLX5_FENCE_MODE_STRONG_ORDERING;
3168 }
3169}
3170
3171static int create_dev_resources(struct mlx5_ib_resources *devr)
3172{
3173 struct ib_srq_init_attr attr;
3174 struct mlx5_ib_dev *dev;
3175 struct ib_cq_init_attr cq_attr = {.cqe = 1};
3176 int port;
3177 int ret = 0;
3178
3179 dev = container_of(devr, struct mlx5_ib_dev, devr);
3180
3181 mutex_init(&devr->mutex);
3182
3183 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3184 if (IS_ERR(devr->p0)) {
3185 ret = PTR_ERR(devr->p0);
3186 goto error0;
3187 }
3188 devr->p0->device = &dev->ib_dev;
3189 devr->p0->uobject = NULL;
3190 atomic_set(&devr->p0->usecnt, 0);
3191
3192 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
3193 if (IS_ERR(devr->c0)) {
3194 ret = PTR_ERR(devr->c0);
3195 goto error1;
3196 }
3197 devr->c0->device = &dev->ib_dev;
3198 devr->c0->uobject = NULL;
3199 devr->c0->comp_handler = NULL;
3200 devr->c0->event_handler = NULL;
3201 devr->c0->cq_context = NULL;
3202 atomic_set(&devr->c0->usecnt, 0);
3203
3204 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3205 if (IS_ERR(devr->x0)) {
3206 ret = PTR_ERR(devr->x0);
3207 goto error2;
3208 }
3209 devr->x0->device = &dev->ib_dev;
3210 devr->x0->inode = NULL;
3211 atomic_set(&devr->x0->usecnt, 0);
3212 mutex_init(&devr->x0->tgt_qp_mutex);
3213 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3214
3215 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3216 if (IS_ERR(devr->x1)) {
3217 ret = PTR_ERR(devr->x1);
3218 goto error3;
3219 }
3220 devr->x1->device = &dev->ib_dev;
3221 devr->x1->inode = NULL;
3222 atomic_set(&devr->x1->usecnt, 0);
3223 mutex_init(&devr->x1->tgt_qp_mutex);
3224 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3225
3226 memset(&attr, 0, sizeof(attr));
3227 attr.attr.max_sge = 1;
3228 attr.attr.max_wr = 1;
3229 attr.srq_type = IB_SRQT_XRC;
3230 attr.ext.cq = devr->c0;
3231 attr.ext.xrc.xrcd = devr->x0;
3232
3233 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3234 if (IS_ERR(devr->s0)) {
3235 ret = PTR_ERR(devr->s0);
3236 goto error4;
3237 }
3238 devr->s0->device = &dev->ib_dev;
3239 devr->s0->pd = devr->p0;
3240 devr->s0->uobject = NULL;
3241 devr->s0->event_handler = NULL;
3242 devr->s0->srq_context = NULL;
3243 devr->s0->srq_type = IB_SRQT_XRC;
3244 devr->s0->ext.xrc.xrcd = devr->x0;
3245 devr->s0->ext.cq = devr->c0;
3246 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3247 atomic_inc(&devr->s0->ext.cq->usecnt);
3248 atomic_inc(&devr->p0->usecnt);
3249 atomic_set(&devr->s0->usecnt, 0);
3250
3251 memset(&attr, 0, sizeof(attr));
3252 attr.attr.max_sge = 1;
3253 attr.attr.max_wr = 1;
3254 attr.srq_type = IB_SRQT_BASIC;
3255 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3256 if (IS_ERR(devr->s1)) {
3257 ret = PTR_ERR(devr->s1);
3258 goto error5;
3259 }
3260 devr->s1->device = &dev->ib_dev;
3261 devr->s1->pd = devr->p0;
3262 devr->s1->uobject = NULL;
3263 devr->s1->event_handler = NULL;
3264 devr->s1->srq_context = NULL;
3265 devr->s1->srq_type = IB_SRQT_BASIC;
3266 devr->s1->ext.cq = devr->c0;
3267 atomic_inc(&devr->p0->usecnt);
3268 atomic_set(&devr->s1->usecnt, 0);
3269
3270 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3271 INIT_WORK(&devr->ports[port].pkey_change_work,
3272 pkey_change_handler);
3273 devr->ports[port].devr = devr;
3274 }
3275
3276 return 0;
3277
3278error5:
3279 mlx5_ib_destroy_srq(devr->s0);
3280error4:
3281 mlx5_ib_dealloc_xrcd(devr->x1);
3282error3:
3283 mlx5_ib_dealloc_xrcd(devr->x0);
3284error2:
3285 mlx5_ib_destroy_cq(devr->c0);
3286error1:
3287 mlx5_ib_dealloc_pd(devr->p0);
3288error0:
3289 return ret;
3290}
3291
3292static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3293{
3294 struct mlx5_ib_dev *dev =
3295 container_of(devr, struct mlx5_ib_dev, devr);
3296 int port;
3297
3298 mlx5_ib_destroy_srq(devr->s1);
3299 mlx5_ib_destroy_srq(devr->s0);
3300 mlx5_ib_dealloc_xrcd(devr->x0);
3301 mlx5_ib_dealloc_xrcd(devr->x1);
3302 mlx5_ib_destroy_cq(devr->c0);
3303 mlx5_ib_dealloc_pd(devr->p0);
3304
3305
3306 for (port = 0; port < dev->num_ports; ++port)
3307 cancel_work_sync(&devr->ports[port].pkey_change_work);
3308}
3309
3310static u32 get_core_cap_flags(struct ib_device *ibdev)
3311{
3312 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3313 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3314 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3315 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3316 u32 ret = 0;
3317
3318 if (ll == IB_LINK_LAYER_INFINIBAND)
3319 return RDMA_CORE_PORT_IBA_IB;
3320
3321 ret = RDMA_CORE_PORT_RAW_PACKET;
3322
3323 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3324 return ret;
3325
3326 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3327 return ret;
3328
3329 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3330 ret |= RDMA_CORE_PORT_IBA_ROCE;
3331
3332 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3333 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3334
3335 return ret;
3336}
3337
3338static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3339 struct ib_port_immutable *immutable)
3340{
3341 struct ib_port_attr attr;
3342 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3343 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3344 int err;
3345
3346 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3347
3348 err = ib_query_port(ibdev, port_num, &attr);
3349 if (err)
3350 return err;
3351
3352 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3353 immutable->gid_tbl_len = attr.gid_tbl_len;
3354 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3355 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3356 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3357
3358 return 0;
3359}
3360
3361static void get_dev_fw_str(struct ib_device *ibdev, char *str)
3362{
3363 struct mlx5_ib_dev *dev =
3364 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3365 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3366 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3367 fw_rev_sub(dev->mdev));
3368}
3369
3370static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3371{
3372 struct mlx5_core_dev *mdev = dev->mdev;
3373 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3374 MLX5_FLOW_NAMESPACE_LAG);
3375 struct mlx5_flow_table *ft;
3376 int err;
3377
3378 if (!ns || !mlx5_lag_is_active(mdev))
3379 return 0;
3380
3381 err = mlx5_cmd_create_vport_lag(mdev);
3382 if (err)
3383 return err;
3384
3385 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3386 if (IS_ERR(ft)) {
3387 err = PTR_ERR(ft);
3388 goto err_destroy_vport_lag;
3389 }
3390
3391 dev->flow_db.lag_demux_ft = ft;
3392 return 0;
3393
3394err_destroy_vport_lag:
3395 mlx5_cmd_destroy_vport_lag(mdev);
3396 return err;
3397}
3398
3399static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3400{
3401 struct mlx5_core_dev *mdev = dev->mdev;
3402
3403 if (dev->flow_db.lag_demux_ft) {
3404 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3405 dev->flow_db.lag_demux_ft = NULL;
3406
3407 mlx5_cmd_destroy_vport_lag(mdev);
3408 }
3409}
3410
3411static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3412{
3413 int err;
3414
3415 dev->roce.nb.notifier_call = mlx5_netdev_event;
3416 err = register_netdevice_notifier(&dev->roce.nb);
3417 if (err) {
3418 dev->roce.nb.notifier_call = NULL;
3419 return err;
3420 }
3421
3422 return 0;
3423}
3424
3425static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
3426{
3427 if (dev->roce.nb.notifier_call) {
3428 unregister_netdevice_notifier(&dev->roce.nb);
3429 dev->roce.nb.notifier_call = NULL;
3430 }
3431}
3432
3433static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3434{
3435 int err;
3436
3437 err = mlx5_add_netdev_notifier(dev);
3438 if (err)
3439 return err;
3440
3441 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3442 err = mlx5_nic_vport_enable_roce(dev->mdev);
3443 if (err)
3444 goto err_unregister_netdevice_notifier;
3445 }
3446
3447 err = mlx5_eth_lag_init(dev);
3448 if (err)
3449 goto err_disable_roce;
3450
3451 return 0;
3452
3453err_disable_roce:
3454 if (MLX5_CAP_GEN(dev->mdev, roce))
3455 mlx5_nic_vport_disable_roce(dev->mdev);
3456
3457err_unregister_netdevice_notifier:
3458 mlx5_remove_netdev_notifier(dev);
3459 return err;
3460}
3461
3462static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3463{
3464 mlx5_eth_lag_cleanup(dev);
3465 if (MLX5_CAP_GEN(dev->mdev, roce))
3466 mlx5_nic_vport_disable_roce(dev->mdev);
3467}
3468
3469struct mlx5_ib_counter {
3470 const char *name;
3471 size_t offset;
3472};
3473
3474#define INIT_Q_COUNTER(_name) \
3475 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3476
3477static const struct mlx5_ib_counter basic_q_cnts[] = {
3478 INIT_Q_COUNTER(rx_write_requests),
3479 INIT_Q_COUNTER(rx_read_requests),
3480 INIT_Q_COUNTER(rx_atomic_requests),
3481 INIT_Q_COUNTER(out_of_buffer),
3482};
3483
3484static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
3485 INIT_Q_COUNTER(out_of_sequence),
3486};
3487
3488static const struct mlx5_ib_counter retrans_q_cnts[] = {
3489 INIT_Q_COUNTER(duplicate_request),
3490 INIT_Q_COUNTER(rnr_nak_retry_err),
3491 INIT_Q_COUNTER(packet_seq_err),
3492 INIT_Q_COUNTER(implied_nak_seq_err),
3493 INIT_Q_COUNTER(local_ack_timeout_err),
3494};
3495
3496#define INIT_CONG_COUNTER(_name) \
3497 { .name = #_name, .offset = \
3498 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3499
3500static const struct mlx5_ib_counter cong_cnts[] = {
3501 INIT_CONG_COUNTER(rp_cnp_ignored),
3502 INIT_CONG_COUNTER(rp_cnp_handled),
3503 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3504 INIT_CONG_COUNTER(np_cnp_sent),
3505};
3506
3507static const struct mlx5_ib_counter extended_err_cnts[] = {
3508 INIT_Q_COUNTER(resp_local_length_error),
3509 INIT_Q_COUNTER(resp_cqe_error),
3510 INIT_Q_COUNTER(req_cqe_error),
3511 INIT_Q_COUNTER(req_remote_invalid_request),
3512 INIT_Q_COUNTER(req_remote_access_errors),
3513 INIT_Q_COUNTER(resp_remote_access_errors),
3514 INIT_Q_COUNTER(resp_cqe_flush_error),
3515 INIT_Q_COUNTER(req_cqe_flush_error),
3516};
3517
3518static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
3519{
3520 unsigned int i;
3521
3522 for (i = 0; i < dev->num_ports; i++) {
3523 mlx5_core_dealloc_q_counter(dev->mdev,
3524 dev->port[i].cnts.set_id);
3525 kfree(dev->port[i].cnts.names);
3526 kfree(dev->port[i].cnts.offsets);
3527 }
3528}
3529
3530static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3531 struct mlx5_ib_counters *cnts)
3532{
3533 u32 num_counters;
3534
3535 num_counters = ARRAY_SIZE(basic_q_cnts);
3536
3537 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3538 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3539
3540 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3541 num_counters += ARRAY_SIZE(retrans_q_cnts);
3542
3543 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3544 num_counters += ARRAY_SIZE(extended_err_cnts);
3545
3546 cnts->num_q_counters = num_counters;
3547
3548 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3549 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3550 num_counters += ARRAY_SIZE(cong_cnts);
3551 }
3552
3553 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3554 if (!cnts->names)
3555 return -ENOMEM;
3556
3557 cnts->offsets = kcalloc(num_counters,
3558 sizeof(cnts->offsets), GFP_KERNEL);
3559 if (!cnts->offsets)
3560 goto err_names;
3561
3562 return 0;
3563
3564err_names:
3565 kfree(cnts->names);
3566 return -ENOMEM;
3567}
3568
3569static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3570 const char **names,
3571 size_t *offsets)
3572{
3573 int i;
3574 int j = 0;
3575
3576 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3577 names[j] = basic_q_cnts[i].name;
3578 offsets[j] = basic_q_cnts[i].offset;
3579 }
3580
3581 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3582 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3583 names[j] = out_of_seq_q_cnts[i].name;
3584 offsets[j] = out_of_seq_q_cnts[i].offset;
3585 }
3586 }
3587
3588 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3589 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3590 names[j] = retrans_q_cnts[i].name;
3591 offsets[j] = retrans_q_cnts[i].offset;
3592 }
3593 }
3594
3595 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
3596 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
3597 names[j] = extended_err_cnts[i].name;
3598 offsets[j] = extended_err_cnts[i].offset;
3599 }
3600 }
3601
3602 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3603 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3604 names[j] = cong_cnts[i].name;
3605 offsets[j] = cong_cnts[i].offset;
3606 }
3607 }
3608}
3609
3610static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
3611{
3612 int i;
3613 int ret;
3614
3615 for (i = 0; i < dev->num_ports; i++) {
3616 struct mlx5_ib_port *port = &dev->port[i];
3617
3618 ret = mlx5_core_alloc_q_counter(dev->mdev,
3619 &port->cnts.set_id);
3620 if (ret) {
3621 mlx5_ib_warn(dev,
3622 "couldn't allocate queue counter for port %d, err %d\n",
3623 i + 1, ret);
3624 goto dealloc_counters;
3625 }
3626
3627 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
3628 if (ret)
3629 goto dealloc_counters;
3630
3631 mlx5_ib_fill_counters(dev, port->cnts.names,
3632 port->cnts.offsets);
3633 }
3634
3635 return 0;
3636
3637dealloc_counters:
3638 while (--i >= 0)
3639 mlx5_core_dealloc_q_counter(dev->mdev,
3640 dev->port[i].cnts.set_id);
3641
3642 return ret;
3643}
3644
3645static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3646 u8 port_num)
3647{
3648 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3649 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3650
3651
3652 if (port_num == 0)
3653 return NULL;
3654
3655 return rdma_alloc_hw_stats_struct(port->cnts.names,
3656 port->cnts.num_q_counters +
3657 port->cnts.num_cong_counters,
3658 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3659}
3660
3661static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3662 struct mlx5_ib_port *port,
3663 struct rdma_hw_stats *stats)
3664{
3665 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3666 void *out;
3667 __be32 val;
3668 int ret, i;
3669
3670 out = kvzalloc(outlen, GFP_KERNEL);
3671 if (!out)
3672 return -ENOMEM;
3673
3674 ret = mlx5_core_query_q_counter(dev->mdev,
3675 port->cnts.set_id, 0,
3676 out, outlen);
3677 if (ret)
3678 goto free;
3679
3680 for (i = 0; i < port->cnts.num_q_counters; i++) {
3681 val = *(__be32 *)(out + port->cnts.offsets[i]);
3682 stats->value[i] = (u64)be32_to_cpu(val);
3683 }
3684
3685free:
3686 kvfree(out);
3687 return ret;
3688}
3689
3690static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev,
3691 struct mlx5_ib_port *port,
3692 struct rdma_hw_stats *stats)
3693{
3694 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3695 void *out;
3696 int ret, i;
3697 int offset = port->cnts.num_q_counters;
3698
3699 out = kvzalloc(outlen, GFP_KERNEL);
3700 if (!out)
3701 return -ENOMEM;
3702
3703 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3704 if (ret)
3705 goto free;
3706
3707 for (i = 0; i < port->cnts.num_cong_counters; i++) {
3708 stats->value[i + offset] =
3709 be64_to_cpup((__be64 *)(out +
3710 port->cnts.offsets[i + offset]));
3711 }
3712
3713free:
3714 kvfree(out);
3715 return ret;
3716}
3717
3718static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3719 struct rdma_hw_stats *stats,
3720 u8 port_num, int index)
3721{
3722 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3723 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3724 int ret, num_counters;
3725
3726 if (!stats)
3727 return -EINVAL;
3728
3729 ret = mlx5_ib_query_q_counters(dev, port, stats);
3730 if (ret)
3731 return ret;
3732 num_counters = port->cnts.num_q_counters;
3733
3734 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3735 ret = mlx5_ib_query_cong_counters(dev, port, stats);
3736 if (ret)
3737 return ret;
3738 num_counters += port->cnts.num_cong_counters;
3739 }
3740
3741 return num_counters;
3742}
3743
3744static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3745{
3746 return mlx5_rdma_netdev_free(netdev);
3747}
3748
3749static struct net_device*
3750mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3751 u8 port_num,
3752 enum rdma_netdev_t type,
3753 const char *name,
3754 unsigned char name_assign_type,
3755 void (*setup)(struct net_device *))
3756{
3757 struct net_device *netdev;
3758 struct rdma_netdev *rn;
3759
3760 if (type != RDMA_NETDEV_IPOIB)
3761 return ERR_PTR(-EOPNOTSUPP);
3762
3763 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3764 name, setup);
3765 if (likely(!IS_ERR_OR_NULL(netdev))) {
3766 rn = netdev_priv(netdev);
3767 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3768 }
3769 return netdev;
3770}
3771
3772static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
3773{
3774 if (!dev->delay_drop.dbg)
3775 return;
3776 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
3777 kfree(dev->delay_drop.dbg);
3778 dev->delay_drop.dbg = NULL;
3779}
3780
3781static void cancel_delay_drop(struct mlx5_ib_dev *dev)
3782{
3783 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3784 return;
3785
3786 cancel_work_sync(&dev->delay_drop.delay_drop_work);
3787 delay_drop_debugfs_cleanup(dev);
3788}
3789
3790static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3791 size_t count, loff_t *pos)
3792{
3793 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3794 char lbuf[20];
3795 int len;
3796
3797 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3798 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3799}
3800
3801static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3802 size_t count, loff_t *pos)
3803{
3804 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3805 u32 timeout;
3806 u32 var;
3807
3808 if (kstrtouint_from_user(buf, count, 0, &var))
3809 return -EFAULT;
3810
3811 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3812 1000);
3813 if (timeout != var)
3814 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3815 timeout);
3816
3817 delay_drop->timeout = timeout;
3818
3819 return count;
3820}
3821
3822static const struct file_operations fops_delay_drop_timeout = {
3823 .owner = THIS_MODULE,
3824 .open = simple_open,
3825 .write = delay_drop_timeout_write,
3826 .read = delay_drop_timeout_read,
3827};
3828
3829static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
3830{
3831 struct mlx5_ib_dbg_delay_drop *dbg;
3832
3833 if (!mlx5_debugfs_root)
3834 return 0;
3835
3836 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
3837 if (!dbg)
3838 return -ENOMEM;
3839
3840 dev->delay_drop.dbg = dbg;
3841
3842 dbg->dir_debugfs =
3843 debugfs_create_dir("delay_drop",
3844 dev->mdev->priv.dbg_root);
3845 if (!dbg->dir_debugfs)
3846 goto out_debugfs;
3847
3848 dbg->events_cnt_debugfs =
3849 debugfs_create_atomic_t("num_timeout_events", 0400,
3850 dbg->dir_debugfs,
3851 &dev->delay_drop.events_cnt);
3852 if (!dbg->events_cnt_debugfs)
3853 goto out_debugfs;
3854
3855 dbg->rqs_cnt_debugfs =
3856 debugfs_create_atomic_t("num_rqs", 0400,
3857 dbg->dir_debugfs,
3858 &dev->delay_drop.rqs_cnt);
3859 if (!dbg->rqs_cnt_debugfs)
3860 goto out_debugfs;
3861
3862 dbg->timeout_debugfs =
3863 debugfs_create_file("timeout", 0600,
3864 dbg->dir_debugfs,
3865 &dev->delay_drop,
3866 &fops_delay_drop_timeout);
3867 if (!dbg->timeout_debugfs)
3868 goto out_debugfs;
3869
3870 return 0;
3871
3872out_debugfs:
3873 delay_drop_debugfs_cleanup(dev);
3874 return -ENOMEM;
3875}
3876
3877static void init_delay_drop(struct mlx5_ib_dev *dev)
3878{
3879 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3880 return;
3881
3882 mutex_init(&dev->delay_drop.lock);
3883 dev->delay_drop.dev = dev;
3884 dev->delay_drop.activate = false;
3885 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
3886 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
3887 atomic_set(&dev->delay_drop.rqs_cnt, 0);
3888 atomic_set(&dev->delay_drop.events_cnt, 0);
3889
3890 if (delay_drop_debugfs_init(dev))
3891 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
3892}
3893
3894static const struct cpumask *
3895mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
3896{
3897 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3898
3899 return mlx5_get_vector_affinity(dev->mdev, comp_vector);
3900}
3901
3902static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3903{
3904 struct mlx5_ib_dev *dev;
3905 enum rdma_link_layer ll;
3906 int port_type_cap;
3907 const char *name;
3908 int err;
3909 int i;
3910
3911 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3912 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3913
3914 printk_once(KERN_INFO "%s", mlx5_version);
3915
3916 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3917 if (!dev)
3918 return NULL;
3919
3920 dev->mdev = mdev;
3921
3922 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3923 GFP_KERNEL);
3924 if (!dev->port)
3925 goto err_dealloc;
3926
3927 rwlock_init(&dev->roce.netdev_lock);
3928 err = get_port_caps(dev);
3929 if (err)
3930 goto err_free_port;
3931
3932 if (mlx5_use_mad_ifc(dev))
3933 get_ext_port_caps(dev);
3934
3935 if (!mlx5_lag_is_active(mdev))
3936 name = "mlx5_%d";
3937 else
3938 name = "mlx5_bond_%d";
3939
3940 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
3941 dev->ib_dev.owner = THIS_MODULE;
3942 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3943 dev->ib_dev.local_dma_lkey = 0 ;
3944 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
3945 dev->ib_dev.phys_port_cnt = dev->num_ports;
3946 dev->ib_dev.num_comp_vectors =
3947 dev->mdev->priv.eq_table.num_comp_vectors;
3948 dev->ib_dev.dev.parent = &mdev->pdev->dev;
3949
3950 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3951 dev->ib_dev.uverbs_cmd_mask =
3952 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3953 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3954 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3955 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3956 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
3957 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3958 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
3959 (1ull << IB_USER_VERBS_CMD_REG_MR) |
3960 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
3961 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3962 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3963 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3964 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3965 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3966 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3967 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3968 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3969 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3970 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3971 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3972 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3973 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3974 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3975 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3976 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3977 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3978 dev->ib_dev.uverbs_ex_cmd_mask =
3979 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3980 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
3981 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
3982 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
3983
3984 dev->ib_dev.query_device = mlx5_ib_query_device;
3985 dev->ib_dev.query_port = mlx5_ib_query_port;
3986 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
3987 if (ll == IB_LINK_LAYER_ETHERNET)
3988 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
3989 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3990 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3991 dev->ib_dev.del_gid = mlx5_ib_del_gid;
3992 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3993 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3994 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3995 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3996 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3997 dev->ib_dev.mmap = mlx5_ib_mmap;
3998 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3999 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
4000 dev->ib_dev.create_ah = mlx5_ib_create_ah;
4001 dev->ib_dev.query_ah = mlx5_ib_query_ah;
4002 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
4003 dev->ib_dev.create_srq = mlx5_ib_create_srq;
4004 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
4005 dev->ib_dev.query_srq = mlx5_ib_query_srq;
4006 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
4007 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
4008 dev->ib_dev.create_qp = mlx5_ib_create_qp;
4009 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
4010 dev->ib_dev.query_qp = mlx5_ib_query_qp;
4011 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
4012 dev->ib_dev.post_send = mlx5_ib_post_send;
4013 dev->ib_dev.post_recv = mlx5_ib_post_recv;
4014 dev->ib_dev.create_cq = mlx5_ib_create_cq;
4015 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
4016 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
4017 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
4018 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
4019 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
4020 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
4021 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
4022 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
4023 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
4024 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
4025 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
4026 dev->ib_dev.process_mad = mlx5_ib_process_mad;
4027 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
4028 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
4029 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
4030 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
4031 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
4032 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
4033 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
4034 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
4035
4036 if (mlx5_core_is_pf(mdev)) {
4037 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
4038 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
4039 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
4040 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
4041 }
4042
4043 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
4044
4045 mlx5_ib_internal_fill_odp_caps(dev);
4046
4047 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4048
4049 if (MLX5_CAP_GEN(mdev, imaicl)) {
4050 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
4051 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
4052 dev->ib_dev.uverbs_cmd_mask |=
4053 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
4054 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4055 }
4056
4057 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
4058 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
4059 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
4060 }
4061
4062 if (MLX5_CAP_GEN(mdev, xrc)) {
4063 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4064 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4065 dev->ib_dev.uverbs_cmd_mask |=
4066 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4067 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4068 }
4069
4070 dev->ib_dev.create_flow = mlx5_ib_create_flow;
4071 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4072 dev->ib_dev.uverbs_ex_cmd_mask |=
4073 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4074 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4075
4076 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
4077 IB_LINK_LAYER_ETHERNET) {
4078 dev->ib_dev.create_wq = mlx5_ib_create_wq;
4079 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
4080 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
4081 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4082 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
4083 dev->ib_dev.uverbs_ex_cmd_mask |=
4084 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4085 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
4086 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4087 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4088 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
4089 }
4090 err = init_node_data(dev);
4091 if (err)
4092 goto err_free_port;
4093
4094 mutex_init(&dev->flow_db.lock);
4095 mutex_init(&dev->cap_mask_mutex);
4096 INIT_LIST_HEAD(&dev->qp_list);
4097 spin_lock_init(&dev->reset_flow_resource_lock);
4098
4099 if (ll == IB_LINK_LAYER_ETHERNET) {
4100 err = mlx5_enable_eth(dev);
4101 if (err)
4102 goto err_free_port;
4103 dev->roce.last_port_state = IB_PORT_DOWN;
4104 }
4105
4106 err = create_dev_resources(&dev->devr);
4107 if (err)
4108 goto err_disable_eth;
4109
4110 err = mlx5_ib_odp_init_one(dev);
4111 if (err)
4112 goto err_rsrc;
4113
4114 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
4115 err = mlx5_ib_alloc_counters(dev);
4116 if (err)
4117 goto err_odp;
4118 }
4119
4120 err = mlx5_ib_init_cong_debugfs(dev);
4121 if (err)
4122 goto err_cnt;
4123
4124 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4125 if (!dev->mdev->priv.uar)
4126 goto err_cong;
4127
4128 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4129 if (err)
4130 goto err_uar_page;
4131
4132 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4133 if (err)
4134 goto err_bfreg;
4135
4136 err = ib_register_device(&dev->ib_dev, NULL);
4137 if (err)
4138 goto err_fp_bfreg;
4139
4140 err = create_umr_res(dev);
4141 if (err)
4142 goto err_dev;
4143
4144 init_delay_drop(dev);
4145
4146 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
4147 err = device_create_file(&dev->ib_dev.dev,
4148 mlx5_class_attributes[i]);
4149 if (err)
4150 goto err_delay_drop;
4151 }
4152
4153 if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4154 MLX5_CAP_GEN(mdev, disable_local_lb))
4155 mutex_init(&dev->lb_mutex);
4156
4157 dev->ib_active = true;
4158
4159 return dev;
4160
4161err_delay_drop:
4162 cancel_delay_drop(dev);
4163 destroy_umrc_res(dev);
4164
4165err_dev:
4166 ib_unregister_device(&dev->ib_dev);
4167
4168err_fp_bfreg:
4169 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4170
4171err_bfreg:
4172 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4173
4174err_uar_page:
4175 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4176
4177err_cong:
4178 mlx5_ib_cleanup_cong_debugfs(dev);
4179err_cnt:
4180 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
4181 mlx5_ib_dealloc_counters(dev);
4182
4183err_odp:
4184 mlx5_ib_odp_remove_one(dev);
4185
4186err_rsrc:
4187 destroy_dev_resources(&dev->devr);
4188
4189err_disable_eth:
4190 if (ll == IB_LINK_LAYER_ETHERNET) {
4191 mlx5_disable_eth(dev);
4192 mlx5_remove_netdev_notifier(dev);
4193 }
4194
4195err_free_port:
4196 kfree(dev->port);
4197
4198err_dealloc:
4199 ib_dealloc_device((struct ib_device *)dev);
4200
4201 return NULL;
4202}
4203
4204static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
4205{
4206 struct mlx5_ib_dev *dev = context;
4207 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
4208
4209 cancel_delay_drop(dev);
4210 mlx5_remove_netdev_notifier(dev);
4211 ib_unregister_device(&dev->ib_dev);
4212 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4213 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4214 mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
4215 mlx5_ib_cleanup_cong_debugfs(dev);
4216 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
4217 mlx5_ib_dealloc_counters(dev);
4218 destroy_umrc_res(dev);
4219 mlx5_ib_odp_remove_one(dev);
4220 destroy_dev_resources(&dev->devr);
4221 if (ll == IB_LINK_LAYER_ETHERNET)
4222 mlx5_disable_eth(dev);
4223 kfree(dev->port);
4224 ib_dealloc_device(&dev->ib_dev);
4225}
4226
4227static struct mlx5_interface mlx5_ib_interface = {
4228 .add = mlx5_ib_add,
4229 .remove = mlx5_ib_remove,
4230 .event = mlx5_ib_event,
4231#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4232 .pfault = mlx5_ib_pfault,
4233#endif
4234 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
4235};
4236
4237static int __init mlx5_ib_init(void)
4238{
4239 int err;
4240
4241 mlx5_ib_odp_init();
4242
4243 err = mlx5_register_interface(&mlx5_ib_interface);
4244
4245 return err;
4246}
4247
4248static void __exit mlx5_ib_cleanup(void)
4249{
4250 mlx5_unregister_interface(&mlx5_ib_interface);
4251}
4252
4253module_init(mlx5_ib_init);
4254module_exit(mlx5_ib_cleanup);
4255
