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13#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
14
15#include <linux/bitops.h>
16#include <linux/bug.h>
17#include <linux/device.h>
18#include <linux/errno.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/slab.h>
23#include <linux/types.h>
24#include <linux/videodev2.h>
25
26#include <media/v4l2-device.h>
27#include <media/v4l2-ioctl.h>
28
29#include "fimc-is.h"
30#include "fimc-is-command.h"
31#include "fimc-is-errno.h"
32#include "fimc-is-param.h"
33#include "fimc-is-regs.h"
34#include "fimc-is-sensor.h"
35
36static void __hw_param_copy(void *dst, void *src)
37{
38 memcpy(dst, src, FIMC_IS_PARAM_MAX_SIZE);
39}
40
41static void __fimc_is_hw_update_param_global_shotmode(struct fimc_is *is)
42{
43 struct param_global_shotmode *dst, *src;
44
45 dst = &is->is_p_region->parameter.global.shotmode;
46 src = &is->config[is->config_index].global.shotmode;
47 __hw_param_copy(dst, src);
48}
49
50static void __fimc_is_hw_update_param_sensor_framerate(struct fimc_is *is)
51{
52 struct param_sensor_framerate *dst, *src;
53
54 dst = &is->is_p_region->parameter.sensor.frame_rate;
55 src = &is->config[is->config_index].sensor.frame_rate;
56 __hw_param_copy(dst, src);
57}
58
59int __fimc_is_hw_update_param(struct fimc_is *is, u32 offset)
60{
61 struct is_param_region *par = &is->is_p_region->parameter;
62 struct chain_config *cfg = &is->config[is->config_index];
63
64 switch (offset) {
65 case PARAM_ISP_CONTROL:
66 __hw_param_copy(&par->isp.control, &cfg->isp.control);
67 break;
68
69 case PARAM_ISP_OTF_INPUT:
70 __hw_param_copy(&par->isp.otf_input, &cfg->isp.otf_input);
71 break;
72
73 case PARAM_ISP_DMA1_INPUT:
74 __hw_param_copy(&par->isp.dma1_input, &cfg->isp.dma1_input);
75 break;
76
77 case PARAM_ISP_DMA2_INPUT:
78 __hw_param_copy(&par->isp.dma2_input, &cfg->isp.dma2_input);
79 break;
80
81 case PARAM_ISP_AA:
82 __hw_param_copy(&par->isp.aa, &cfg->isp.aa);
83 break;
84
85 case PARAM_ISP_FLASH:
86 __hw_param_copy(&par->isp.flash, &cfg->isp.flash);
87 break;
88
89 case PARAM_ISP_AWB:
90 __hw_param_copy(&par->isp.awb, &cfg->isp.awb);
91 break;
92
93 case PARAM_ISP_IMAGE_EFFECT:
94 __hw_param_copy(&par->isp.effect, &cfg->isp.effect);
95 break;
96
97 case PARAM_ISP_ISO:
98 __hw_param_copy(&par->isp.iso, &cfg->isp.iso);
99 break;
100
101 case PARAM_ISP_ADJUST:
102 __hw_param_copy(&par->isp.adjust, &cfg->isp.adjust);
103 break;
104
105 case PARAM_ISP_METERING:
106 __hw_param_copy(&par->isp.metering, &cfg->isp.metering);
107 break;
108
109 case PARAM_ISP_AFC:
110 __hw_param_copy(&par->isp.afc, &cfg->isp.afc);
111 break;
112
113 case PARAM_ISP_OTF_OUTPUT:
114 __hw_param_copy(&par->isp.otf_output, &cfg->isp.otf_output);
115 break;
116
117 case PARAM_ISP_DMA1_OUTPUT:
118 __hw_param_copy(&par->isp.dma1_output, &cfg->isp.dma1_output);
119 break;
120
121 case PARAM_ISP_DMA2_OUTPUT:
122 __hw_param_copy(&par->isp.dma2_output, &cfg->isp.dma2_output);
123 break;
124
125 case PARAM_DRC_CONTROL:
126 __hw_param_copy(&par->drc.control, &cfg->drc.control);
127 break;
128
129 case PARAM_DRC_OTF_INPUT:
130 __hw_param_copy(&par->drc.otf_input, &cfg->drc.otf_input);
131 break;
132
133 case PARAM_DRC_DMA_INPUT:
134 __hw_param_copy(&par->drc.dma_input, &cfg->drc.dma_input);
135 break;
136
137 case PARAM_DRC_OTF_OUTPUT:
138 __hw_param_copy(&par->drc.otf_output, &cfg->drc.otf_output);
139 break;
140
141 case PARAM_FD_CONTROL:
142 __hw_param_copy(&par->fd.control, &cfg->fd.control);
143 break;
144
145 case PARAM_FD_OTF_INPUT:
146 __hw_param_copy(&par->fd.otf_input, &cfg->fd.otf_input);
147 break;
148
149 case PARAM_FD_DMA_INPUT:
150 __hw_param_copy(&par->fd.dma_input, &cfg->fd.dma_input);
151 break;
152
153 case PARAM_FD_CONFIG:
154 __hw_param_copy(&par->fd.config, &cfg->fd.config);
155 break;
156
157 default:
158 return -EINVAL;
159 }
160
161 return 0;
162}
163
164unsigned int __get_pending_param_count(struct fimc_is *is)
165{
166 struct chain_config *config = &is->config[is->config_index];
167 unsigned long flags;
168 unsigned int count;
169
170 spin_lock_irqsave(&is->slock, flags);
171 count = hweight32(config->p_region_index[0]);
172 count += hweight32(config->p_region_index[1]);
173 spin_unlock_irqrestore(&is->slock, flags);
174
175 return count;
176}
177
178int __is_hw_update_params(struct fimc_is *is)
179{
180 unsigned long *p_index;
181 int i, id, ret = 0;
182
183 id = is->config_index;
184 p_index = &is->config[id].p_region_index[0];
185
186 if (test_bit(PARAM_GLOBAL_SHOTMODE, p_index))
187 __fimc_is_hw_update_param_global_shotmode(is);
188
189 if (test_bit(PARAM_SENSOR_FRAME_RATE, p_index))
190 __fimc_is_hw_update_param_sensor_framerate(is);
191
192 for (i = PARAM_ISP_CONTROL; i < PARAM_DRC_CONTROL; i++) {
193 if (test_bit(i, p_index))
194 ret = __fimc_is_hw_update_param(is, i);
195 }
196
197 for (i = PARAM_DRC_CONTROL; i < PARAM_SCALERC_CONTROL; i++) {
198 if (test_bit(i, p_index))
199 ret = __fimc_is_hw_update_param(is, i);
200 }
201
202 for (i = PARAM_FD_CONTROL; i <= PARAM_FD_CONFIG; i++) {
203 if (test_bit(i, p_index))
204 ret = __fimc_is_hw_update_param(is, i);
205 }
206
207 return ret;
208}
209
210void __is_get_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf)
211{
212 struct isp_param *isp;
213
214 isp = &is->config[is->config_index].isp;
215 mf->width = isp->otf_input.width;
216 mf->height = isp->otf_input.height;
217}
218
219void __is_set_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf)
220{
221 unsigned int index = is->config_index;
222 struct isp_param *isp;
223 struct drc_param *drc;
224 struct fd_param *fd;
225
226 isp = &is->config[index].isp;
227 drc = &is->config[index].drc;
228 fd = &is->config[index].fd;
229
230
231 isp->otf_input.width = mf->width;
232 isp->otf_input.height = mf->height;
233 isp->otf_output.width = mf->width;
234 isp->otf_output.height = mf->height;
235
236 drc->otf_input.width = mf->width;
237 drc->otf_input.height = mf->height;
238 drc->otf_output.width = mf->width;
239 drc->otf_output.height = mf->height;
240
241 fd->otf_input.width = mf->width;
242 fd->otf_input.height = mf->height;
243
244 if (test_bit(PARAM_ISP_OTF_INPUT,
245 &is->config[index].p_region_index[0]))
246 return;
247
248
249 fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT);
250 fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT);
251 fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT);
252 fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT);
253 fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT);
254}
255
256int fimc_is_hw_get_sensor_max_framerate(struct fimc_is *is)
257{
258 switch (is->sensor->drvdata->id) {
259 case FIMC_IS_SENSOR_ID_S5K6A3:
260 return 30;
261 default:
262 return 15;
263 }
264}
265
266void __is_set_sensor(struct fimc_is *is, int fps)
267{
268 unsigned int index = is->config_index;
269 struct sensor_param *sensor;
270 struct isp_param *isp;
271
272 sensor = &is->config[index].sensor;
273 isp = &is->config[index].isp;
274
275 if (fps == 0) {
276 sensor->frame_rate.frame_rate =
277 fimc_is_hw_get_sensor_max_framerate(is);
278 isp->otf_input.frametime_min = 0;
279 isp->otf_input.frametime_max = 66666;
280 } else {
281 sensor->frame_rate.frame_rate = fps;
282 isp->otf_input.frametime_min = 0;
283 isp->otf_input.frametime_max = (u32)1000000 / fps;
284 }
285
286 fimc_is_set_param_bit(is, PARAM_SENSOR_FRAME_RATE);
287 fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT);
288}
289
290static void __maybe_unused __is_set_init_isp_aa(struct fimc_is *is)
291{
292 struct isp_param *isp;
293
294 isp = &is->config[is->config_index].isp;
295
296 isp->aa.cmd = ISP_AA_COMMAND_START;
297 isp->aa.target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
298 ISP_AA_TARGET_AWB;
299 isp->aa.mode = 0;
300 isp->aa.scene = 0;
301 isp->aa.sleep = 0;
302 isp->aa.face = 0;
303 isp->aa.touch_x = 0;
304 isp->aa.touch_y = 0;
305 isp->aa.manual_af_setting = 0;
306 isp->aa.err = ISP_AF_ERROR_NONE;
307
308 fimc_is_set_param_bit(is, PARAM_ISP_AA);
309}
310
311void __is_set_isp_flash(struct fimc_is *is, u32 cmd, u32 redeye)
312{
313 unsigned int index = is->config_index;
314 struct isp_param *isp = &is->config[index].isp;
315
316 isp->flash.cmd = cmd;
317 isp->flash.redeye = redeye;
318 isp->flash.err = ISP_FLASH_ERROR_NONE;
319
320 fimc_is_set_param_bit(is, PARAM_ISP_FLASH);
321}
322
323void __is_set_isp_awb(struct fimc_is *is, u32 cmd, u32 val)
324{
325 unsigned int index = is->config_index;
326 struct isp_param *isp;
327
328 isp = &is->config[index].isp;
329
330 isp->awb.cmd = cmd;
331 isp->awb.illumination = val;
332 isp->awb.err = ISP_AWB_ERROR_NONE;
333
334 fimc_is_set_param_bit(is, PARAM_ISP_AWB);
335}
336
337void __is_set_isp_effect(struct fimc_is *is, u32 cmd)
338{
339 unsigned int index = is->config_index;
340 struct isp_param *isp;
341
342 isp = &is->config[index].isp;
343
344 isp->effect.cmd = cmd;
345 isp->effect.err = ISP_IMAGE_EFFECT_ERROR_NONE;
346
347 fimc_is_set_param_bit(is, PARAM_ISP_IMAGE_EFFECT);
348}
349
350void __is_set_isp_iso(struct fimc_is *is, u32 cmd, u32 val)
351{
352 unsigned int index = is->config_index;
353 struct isp_param *isp;
354
355 isp = &is->config[index].isp;
356
357 isp->iso.cmd = cmd;
358 isp->iso.value = val;
359 isp->iso.err = ISP_ISO_ERROR_NONE;
360
361 fimc_is_set_param_bit(is, PARAM_ISP_ISO);
362}
363
364void __is_set_isp_adjust(struct fimc_is *is, u32 cmd, u32 val)
365{
366 unsigned int index = is->config_index;
367 unsigned long *p_index;
368 struct isp_param *isp;
369
370 p_index = &is->config[index].p_region_index[0];
371 isp = &is->config[index].isp;
372
373 switch (cmd) {
374 case ISP_ADJUST_COMMAND_MANUAL_CONTRAST:
375 isp->adjust.contrast = val;
376 break;
377 case ISP_ADJUST_COMMAND_MANUAL_SATURATION:
378 isp->adjust.saturation = val;
379 break;
380 case ISP_ADJUST_COMMAND_MANUAL_SHARPNESS:
381 isp->adjust.sharpness = val;
382 break;
383 case ISP_ADJUST_COMMAND_MANUAL_EXPOSURE:
384 isp->adjust.exposure = val;
385 break;
386 case ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS:
387 isp->adjust.brightness = val;
388 break;
389 case ISP_ADJUST_COMMAND_MANUAL_HUE:
390 isp->adjust.hue = val;
391 break;
392 case ISP_ADJUST_COMMAND_AUTO:
393 isp->adjust.contrast = 0;
394 isp->adjust.saturation = 0;
395 isp->adjust.sharpness = 0;
396 isp->adjust.exposure = 0;
397 isp->adjust.brightness = 0;
398 isp->adjust.hue = 0;
399 break;
400 }
401
402 if (!test_bit(PARAM_ISP_ADJUST, p_index)) {
403 isp->adjust.cmd = cmd;
404 isp->adjust.err = ISP_ADJUST_ERROR_NONE;
405 fimc_is_set_param_bit(is, PARAM_ISP_ADJUST);
406 } else {
407 isp->adjust.cmd |= cmd;
408 }
409}
410
411void __is_set_isp_metering(struct fimc_is *is, u32 id, u32 val)
412{
413 unsigned int index = is->config_index;
414 struct isp_param *isp;
415 unsigned long *p_index;
416
417 p_index = &is->config[index].p_region_index[0];
418 isp = &is->config[index].isp;
419
420 switch (id) {
421 case IS_METERING_CONFIG_CMD:
422 isp->metering.cmd = val;
423 break;
424 case IS_METERING_CONFIG_WIN_POS_X:
425 isp->metering.win_pos_x = val;
426 break;
427 case IS_METERING_CONFIG_WIN_POS_Y:
428 isp->metering.win_pos_y = val;
429 break;
430 case IS_METERING_CONFIG_WIN_WIDTH:
431 isp->metering.win_width = val;
432 break;
433 case IS_METERING_CONFIG_WIN_HEIGHT:
434 isp->metering.win_height = val;
435 break;
436 default:
437 return;
438 }
439
440 if (!test_bit(PARAM_ISP_METERING, p_index)) {
441 isp->metering.err = ISP_METERING_ERROR_NONE;
442 fimc_is_set_param_bit(is, PARAM_ISP_METERING);
443 }
444}
445
446void __is_set_isp_afc(struct fimc_is *is, u32 cmd, u32 val)
447{
448 unsigned int index = is->config_index;
449 struct isp_param *isp;
450
451 isp = &is->config[index].isp;
452
453 isp->afc.cmd = cmd;
454 isp->afc.manual = val;
455 isp->afc.err = ISP_AFC_ERROR_NONE;
456
457 fimc_is_set_param_bit(is, PARAM_ISP_AFC);
458}
459
460void __is_set_drc_control(struct fimc_is *is, u32 val)
461{
462 unsigned int index = is->config_index;
463 struct drc_param *drc;
464
465 drc = &is->config[index].drc;
466
467 drc->control.bypass = val;
468
469 fimc_is_set_param_bit(is, PARAM_DRC_CONTROL);
470}
471
472void __is_set_fd_control(struct fimc_is *is, u32 val)
473{
474 unsigned int index = is->config_index;
475 struct fd_param *fd;
476 unsigned long *p_index;
477
478 p_index = &is->config[index].p_region_index[1];
479 fd = &is->config[index].fd;
480
481 fd->control.cmd = val;
482
483 if (!test_bit((PARAM_FD_CONFIG - 32), p_index))
484 fimc_is_set_param_bit(is, PARAM_FD_CONTROL);
485}
486
487void __is_set_fd_config_maxface(struct fimc_is *is, u32 val)
488{
489 unsigned int index = is->config_index;
490 struct fd_param *fd;
491 unsigned long *p_index;
492
493 p_index = &is->config[index].p_region_index[1];
494 fd = &is->config[index].fd;
495
496 fd->config.max_number = val;
497
498 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
499 fd->config.cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER;
500 fd->config.err = ERROR_FD_NONE;
501 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
502 } else {
503 fd->config.cmd |= FD_CONFIG_COMMAND_MAXIMUM_NUMBER;
504 }
505}
506
507void __is_set_fd_config_rollangle(struct fimc_is *is, u32 val)
508{
509 unsigned int index = is->config_index;
510 struct fd_param *fd;
511 unsigned long *p_index;
512
513 p_index = &is->config[index].p_region_index[1];
514 fd = &is->config[index].fd;
515
516 fd->config.roll_angle = val;
517
518 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
519 fd->config.cmd = FD_CONFIG_COMMAND_ROLL_ANGLE;
520 fd->config.err = ERROR_FD_NONE;
521 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
522 } else {
523 fd->config.cmd |= FD_CONFIG_COMMAND_ROLL_ANGLE;
524 }
525}
526
527void __is_set_fd_config_yawangle(struct fimc_is *is, u32 val)
528{
529 unsigned int index = is->config_index;
530 struct fd_param *fd;
531 unsigned long *p_index;
532
533 p_index = &is->config[index].p_region_index[1];
534 fd = &is->config[index].fd;
535
536 fd->config.yaw_angle = val;
537
538 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
539 fd->config.cmd = FD_CONFIG_COMMAND_YAW_ANGLE;
540 fd->config.err = ERROR_FD_NONE;
541 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
542 } else {
543 fd->config.cmd |= FD_CONFIG_COMMAND_YAW_ANGLE;
544 }
545}
546
547void __is_set_fd_config_smilemode(struct fimc_is *is, u32 val)
548{
549 unsigned int index = is->config_index;
550 struct fd_param *fd;
551 unsigned long *p_index;
552
553 p_index = &is->config[index].p_region_index[1];
554 fd = &is->config[index].fd;
555
556 fd->config.smile_mode = val;
557
558 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
559 fd->config.cmd = FD_CONFIG_COMMAND_SMILE_MODE;
560 fd->config.err = ERROR_FD_NONE;
561 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
562 } else {
563 fd->config.cmd |= FD_CONFIG_COMMAND_SMILE_MODE;
564 }
565}
566
567void __is_set_fd_config_blinkmode(struct fimc_is *is, u32 val)
568{
569 unsigned int index = is->config_index;
570 struct fd_param *fd;
571 unsigned long *p_index;
572
573 p_index = &is->config[index].p_region_index[1];
574 fd = &is->config[index].fd;
575
576 fd->config.blink_mode = val;
577
578 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
579 fd->config.cmd = FD_CONFIG_COMMAND_BLINK_MODE;
580 fd->config.err = ERROR_FD_NONE;
581 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
582 } else {
583 fd->config.cmd |= FD_CONFIG_COMMAND_BLINK_MODE;
584 }
585}
586
587void __is_set_fd_config_eyedetect(struct fimc_is *is, u32 val)
588{
589 unsigned int index = is->config_index;
590 struct fd_param *fd;
591 unsigned long *p_index;
592
593 p_index = &is->config[index].p_region_index[1];
594 fd = &is->config[index].fd;
595
596 fd->config.eye_detect = val;
597
598 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
599 fd->config.cmd = FD_CONFIG_COMMAND_EYES_DETECT;
600 fd->config.err = ERROR_FD_NONE;
601 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
602 } else {
603 fd->config.cmd |= FD_CONFIG_COMMAND_EYES_DETECT;
604 }
605}
606
607void __is_set_fd_config_mouthdetect(struct fimc_is *is, u32 val)
608{
609 unsigned int index = is->config_index;
610 struct fd_param *fd;
611 unsigned long *p_index;
612
613 p_index = &is->config[index].p_region_index[1];
614 fd = &is->config[index].fd;
615
616 fd->config.mouth_detect = val;
617
618 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
619 fd->config.cmd = FD_CONFIG_COMMAND_MOUTH_DETECT;
620 fd->config.err = ERROR_FD_NONE;
621 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
622 } else {
623 fd->config.cmd |= FD_CONFIG_COMMAND_MOUTH_DETECT;
624 }
625}
626
627void __is_set_fd_config_orientation(struct fimc_is *is, u32 val)
628{
629 unsigned int index = is->config_index;
630 struct fd_param *fd;
631 unsigned long *p_index;
632
633 p_index = &is->config[index].p_region_index[1];
634 fd = &is->config[index].fd;
635
636 fd->config.orientation = val;
637
638 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
639 fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION;
640 fd->config.err = ERROR_FD_NONE;
641 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
642 } else {
643 fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION;
644 }
645}
646
647void __is_set_fd_config_orientation_val(struct fimc_is *is, u32 val)
648{
649 unsigned int index = is->config_index;
650 struct fd_param *fd;
651 unsigned long *p_index;
652
653 p_index = &is->config[index].p_region_index[1];
654 fd = &is->config[index].fd;
655
656 fd->config.orientation_value = val;
657
658 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
659 fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION_VALUE;
660 fd->config.err = ERROR_FD_NONE;
661 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
662 } else {
663 fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION_VALUE;
664 }
665}
666
667void fimc_is_set_initial_params(struct fimc_is *is)
668{
669 struct global_param *global;
670 struct isp_param *isp;
671 struct drc_param *drc;
672 struct fd_param *fd;
673 unsigned long *p_index;
674 unsigned int index;
675
676 index = is->config_index;
677 global = &is->config[index].global;
678 isp = &is->config[index].isp;
679 drc = &is->config[index].drc;
680 fd = &is->config[index].fd;
681 p_index = &is->config[index].p_region_index[0];
682
683
684 global->shotmode.cmd = 1;
685 fimc_is_set_param_bit(is, PARAM_GLOBAL_SHOTMODE);
686
687
688 isp->control.cmd = CONTROL_COMMAND_START;
689 isp->control.bypass = CONTROL_BYPASS_DISABLE;
690 isp->control.err = CONTROL_ERROR_NONE;
691 fimc_is_set_param_bit(is, PARAM_ISP_CONTROL);
692
693 isp->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
694 if (!test_bit(PARAM_ISP_OTF_INPUT, p_index)) {
695 isp->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH;
696 isp->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT;
697 fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT);
698 }
699 if (is->sensor->test_pattern)
700 isp->otf_input.format = OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER;
701 else
702 isp->otf_input.format = OTF_INPUT_FORMAT_BAYER;
703 isp->otf_input.bitwidth = 10;
704 isp->otf_input.order = OTF_INPUT_ORDER_BAYER_GR_BG;
705 isp->otf_input.crop_offset_x = 0;
706 isp->otf_input.crop_offset_y = 0;
707 isp->otf_input.err = OTF_INPUT_ERROR_NONE;
708
709 isp->dma1_input.cmd = DMA_INPUT_COMMAND_DISABLE;
710 isp->dma1_input.width = 0;
711 isp->dma1_input.height = 0;
712 isp->dma1_input.format = 0;
713 isp->dma1_input.bitwidth = 0;
714 isp->dma1_input.plane = 0;
715 isp->dma1_input.order = 0;
716 isp->dma1_input.buffer_number = 0;
717 isp->dma1_input.width = 0;
718 isp->dma1_input.err = DMA_INPUT_ERROR_NONE;
719 fimc_is_set_param_bit(is, PARAM_ISP_DMA1_INPUT);
720
721 isp->dma2_input.cmd = DMA_INPUT_COMMAND_DISABLE;
722 isp->dma2_input.width = 0;
723 isp->dma2_input.height = 0;
724 isp->dma2_input.format = 0;
725 isp->dma2_input.bitwidth = 0;
726 isp->dma2_input.plane = 0;
727 isp->dma2_input.order = 0;
728 isp->dma2_input.buffer_number = 0;
729 isp->dma2_input.width = 0;
730 isp->dma2_input.err = DMA_INPUT_ERROR_NONE;
731 fimc_is_set_param_bit(is, PARAM_ISP_DMA2_INPUT);
732
733 isp->aa.cmd = ISP_AA_COMMAND_START;
734 isp->aa.target = ISP_AA_TARGET_AE | ISP_AA_TARGET_AWB;
735 fimc_is_set_param_bit(is, PARAM_ISP_AA);
736
737 if (!test_bit(PARAM_ISP_FLASH, p_index))
738 __is_set_isp_flash(is, ISP_FLASH_COMMAND_DISABLE,
739 ISP_FLASH_REDEYE_DISABLE);
740
741 if (!test_bit(PARAM_ISP_AWB, p_index))
742 __is_set_isp_awb(is, ISP_AWB_COMMAND_AUTO, 0);
743
744 if (!test_bit(PARAM_ISP_IMAGE_EFFECT, p_index))
745 __is_set_isp_effect(is, ISP_IMAGE_EFFECT_DISABLE);
746
747 if (!test_bit(PARAM_ISP_ISO, p_index))
748 __is_set_isp_iso(is, ISP_ISO_COMMAND_AUTO, 0);
749
750 if (!test_bit(PARAM_ISP_ADJUST, p_index)) {
751 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_CONTRAST, 0);
752 __is_set_isp_adjust(is,
753 ISP_ADJUST_COMMAND_MANUAL_SATURATION, 0);
754 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SHARPNESS, 0);
755 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_EXPOSURE, 0);
756 __is_set_isp_adjust(is,
757 ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS, 0);
758 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_HUE, 0);
759 }
760
761 if (!test_bit(PARAM_ISP_METERING, p_index)) {
762 __is_set_isp_metering(is, 0, ISP_METERING_COMMAND_CENTER);
763 __is_set_isp_metering(is, 1, 0);
764 __is_set_isp_metering(is, 2, 0);
765 __is_set_isp_metering(is, 3, 0);
766 __is_set_isp_metering(is, 4, 0);
767 }
768
769 if (!test_bit(PARAM_ISP_AFC, p_index))
770 __is_set_isp_afc(is, ISP_AFC_COMMAND_AUTO, 0);
771
772 isp->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
773 if (!test_bit(PARAM_ISP_OTF_OUTPUT, p_index)) {
774 isp->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH;
775 isp->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT;
776 fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT);
777 }
778 isp->otf_output.format = OTF_OUTPUT_FORMAT_YUV444;
779 isp->otf_output.bitwidth = 12;
780 isp->otf_output.order = 0;
781 isp->otf_output.err = OTF_OUTPUT_ERROR_NONE;
782
783 if (!test_bit(PARAM_ISP_DMA1_OUTPUT, p_index)) {
784 isp->dma1_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
785 isp->dma1_output.width = 0;
786 isp->dma1_output.height = 0;
787 isp->dma1_output.format = 0;
788 isp->dma1_output.bitwidth = 0;
789 isp->dma1_output.plane = 0;
790 isp->dma1_output.order = 0;
791 isp->dma1_output.buffer_number = 0;
792 isp->dma1_output.buffer_address = 0;
793 isp->dma1_output.notify_dma_done = 0;
794 isp->dma1_output.dma_out_mask = 0;
795 isp->dma1_output.err = DMA_OUTPUT_ERROR_NONE;
796 fimc_is_set_param_bit(is, PARAM_ISP_DMA1_OUTPUT);
797 }
798
799 if (!test_bit(PARAM_ISP_DMA2_OUTPUT, p_index)) {
800 isp->dma2_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
801 isp->dma2_output.width = 0;
802 isp->dma2_output.height = 0;
803 isp->dma2_output.format = 0;
804 isp->dma2_output.bitwidth = 0;
805 isp->dma2_output.plane = 0;
806 isp->dma2_output.order = 0;
807 isp->dma2_output.buffer_number = 0;
808 isp->dma2_output.buffer_address = 0;
809 isp->dma2_output.notify_dma_done = 0;
810 isp->dma2_output.dma_out_mask = 0;
811 isp->dma2_output.err = DMA_OUTPUT_ERROR_NONE;
812 fimc_is_set_param_bit(is, PARAM_ISP_DMA2_OUTPUT);
813 }
814
815
816 if (!test_bit(PARAM_SENSOR_FRAME_RATE, p_index)) {
817 if (is->config_index == 0)
818 __is_set_sensor(is, 0);
819 }
820
821
822 drc->control.cmd = CONTROL_COMMAND_START;
823 __is_set_drc_control(is, CONTROL_BYPASS_ENABLE);
824
825 drc->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
826 if (!test_bit(PARAM_DRC_OTF_INPUT, p_index)) {
827 drc->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH;
828 drc->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT;
829 fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT);
830 }
831 drc->otf_input.format = OTF_INPUT_FORMAT_YUV444;
832 drc->otf_input.bitwidth = 12;
833 drc->otf_input.order = 0;
834 drc->otf_input.err = OTF_INPUT_ERROR_NONE;
835
836 drc->dma_input.cmd = DMA_INPUT_COMMAND_DISABLE;
837 drc->dma_input.width = 0;
838 drc->dma_input.height = 0;
839 drc->dma_input.format = 0;
840 drc->dma_input.bitwidth = 0;
841 drc->dma_input.plane = 0;
842 drc->dma_input.order = 0;
843 drc->dma_input.buffer_number = 0;
844 drc->dma_input.width = 0;
845 drc->dma_input.err = DMA_INPUT_ERROR_NONE;
846 fimc_is_set_param_bit(is, PARAM_DRC_DMA_INPUT);
847
848 drc->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
849 if (!test_bit(PARAM_DRC_OTF_OUTPUT, p_index)) {
850 drc->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH;
851 drc->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT;
852 fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT);
853 }
854 drc->otf_output.format = OTF_OUTPUT_FORMAT_YUV444;
855 drc->otf_output.bitwidth = 8;
856 drc->otf_output.order = 0;
857 drc->otf_output.err = OTF_OUTPUT_ERROR_NONE;
858
859
860 __is_set_fd_control(is, CONTROL_COMMAND_STOP);
861 fd->control.bypass = CONTROL_BYPASS_DISABLE;
862
863 fd->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
864 if (!test_bit(PARAM_FD_OTF_INPUT, p_index)) {
865 fd->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH;
866 fd->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT;
867 fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT);
868 }
869
870 fd->otf_input.format = OTF_INPUT_FORMAT_YUV444;
871 fd->otf_input.bitwidth = 8;
872 fd->otf_input.order = 0;
873 fd->otf_input.err = OTF_INPUT_ERROR_NONE;
874
875 fd->dma_input.cmd = DMA_INPUT_COMMAND_DISABLE;
876 fd->dma_input.width = 0;
877 fd->dma_input.height = 0;
878 fd->dma_input.format = 0;
879 fd->dma_input.bitwidth = 0;
880 fd->dma_input.plane = 0;
881 fd->dma_input.order = 0;
882 fd->dma_input.buffer_number = 0;
883 fd->dma_input.width = 0;
884 fd->dma_input.err = DMA_INPUT_ERROR_NONE;
885 fimc_is_set_param_bit(is, PARAM_FD_DMA_INPUT);
886
887 __is_set_fd_config_maxface(is, 5);
888 __is_set_fd_config_rollangle(is, FD_CONFIG_ROLL_ANGLE_FULL);
889 __is_set_fd_config_yawangle(is, FD_CONFIG_YAW_ANGLE_45_90);
890 __is_set_fd_config_smilemode(is, FD_CONFIG_SMILE_MODE_DISABLE);
891 __is_set_fd_config_blinkmode(is, FD_CONFIG_BLINK_MODE_DISABLE);
892 __is_set_fd_config_eyedetect(is, FD_CONFIG_EYES_DETECT_ENABLE);
893 __is_set_fd_config_mouthdetect(is, FD_CONFIG_MOUTH_DETECT_DISABLE);
894 __is_set_fd_config_orientation(is, FD_CONFIG_ORIENTATION_DISABLE);
895 __is_set_fd_config_orientation_val(is, 0);
896}
897
