LXR linux/drivers/mtd/maps/esb2rom.c

   1/*
   2 * esb2rom.c
   3 *
   4 * Normal mappings of flash chips in physical memory
   5 * through the Intel ESB2 Southbridge.
   6 *
   7 * This was derived from ichxrom.c in May 2006 by
   8 *      Lew Glendenning <lglendenning@lnxi.com>
   9 *
  10 * Eric Biederman, of course, was a major help in this effort.
  11 */
  12
  13#include <linux/module.h>
  14#include <linux/types.h>
  15#include <linux/kernel.h>
  16#include <linux/init.h>
  17#include <linux/slab.h>
  18#include <asm/io.h>
  19#include <linux/mtd/mtd.h>
  20#include <linux/mtd/map.h>
  21#include <linux/mtd/cfi.h>
  22#include <linux/mtd/flashchip.h>
  23#include <linux/pci.h>
  24#include <linux/pci_ids.h>
  25#include <linux/list.h>
  26
  27#define MOD_NAME KBUILD_BASENAME
  28
  29#define ADDRESS_NAME_LEN 18
  30
  31#define ROM_PROBE_STEP_SIZE (64*1024) /* 64KiB */
  32
  33#define BIOS_CNTL               0xDC
  34#define BIOS_LOCK_ENABLE        0x02
  35#define BIOS_WRITE_ENABLE       0x01
  36
  37/* This became a 16-bit register, and EN2 has disappeared */
  38#define FWH_DEC_EN1     0xD8
  39#define FWH_F8_EN       0x8000
  40#define FWH_F0_EN       0x4000
  41#define FWH_E8_EN       0x2000
  42#define FWH_E0_EN       0x1000
  43#define FWH_D8_EN       0x0800
  44#define FWH_D0_EN       0x0400
  45#define FWH_C8_EN       0x0200
  46#define FWH_C0_EN       0x0100
  47#define FWH_LEGACY_F_EN 0x0080
  48#define FWH_LEGACY_E_EN 0x0040
  49/* reserved  0x0020 and 0x0010 */
  50#define FWH_70_EN       0x0008
  51#define FWH_60_EN       0x0004
  52#define FWH_50_EN       0x0002
  53#define FWH_40_EN       0x0001
  54
  55/* these are 32-bit values */
  56#define FWH_SEL1        0xD0
  57#define FWH_SEL2        0xD4
  58
  59#define FWH_8MiB        (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
  60                         FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \
  61                         FWH_70_EN | FWH_60_EN | FWH_50_EN | FWH_40_EN)
  62
  63#define FWH_7MiB        (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
  64                         FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \
  65                         FWH_70_EN | FWH_60_EN | FWH_50_EN)
  66
  67#define FWH_6MiB        (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
  68                         FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \
  69                         FWH_70_EN | FWH_60_EN)
  70
  71#define FWH_5MiB        (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
  72                         FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \
  73                         FWH_70_EN)
  74
  75#define FWH_4MiB        (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
  76                         FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN)
  77
  78#define FWH_3_5MiB      (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
  79                         FWH_D8_EN | FWH_D0_EN | FWH_C8_EN)
  80
  81#define FWH_3MiB        (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
  82                         FWH_D8_EN | FWH_D0_EN)
  83
  84#define FWH_2_5MiB      (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \
  85                         FWH_D8_EN)
  86
  87#define FWH_2MiB        (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN)
  88
  89#define FWH_1_5MiB      (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN)
  90
  91#define FWH_1MiB        (FWH_F8_EN | FWH_F0_EN)
  92
  93#define FWH_0_5MiB      (FWH_F8_EN)
  94
  95
  96struct esb2rom_window {
  97        void __iomem* virt;
  98        unsigned long phys;
  99        unsigned long size;
 100        struct list_head maps;
 101        struct resource rsrc;
 102        struct pci_dev *pdev;
 103};
 104
 105struct esb2rom_map_info {
 106        struct list_head list;
 107        struct map_info map;
 108        struct mtd_info *mtd;
 109        struct resource rsrc;
 110        char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN];
 111};
 112
 113static struct esb2rom_window esb2rom_window = {
 114        .maps = LIST_HEAD_INIT(esb2rom_window.maps),
 115};
 116
 117static void esb2rom_cleanup(struct esb2rom_window *window)
 118{
 119        struct esb2rom_map_info *map, *scratch;
 120        u8 byte;
 121
 122        /* Disable writes through the rom window */
 123        pci_read_config_byte(window->pdev, BIOS_CNTL, &byte);
 124        pci_write_config_byte(window->pdev, BIOS_CNTL,
 125                byte & ~BIOS_WRITE_ENABLE);
 126
 127        /* Free all of the mtd devices */
 128        list_for_each_entry_safe(map, scratch, &window->maps, list) {
 129                if (map->rsrc.parent)
 130                        release_resource(&map->rsrc);
 131                mtd_device_unregister(map->mtd);
 132                map_destroy(map->mtd);
 133                list_del(&map->list);
 134                kfree(map);
 135        }
 136        if (window->rsrc.parent)
 137                release_resource(&window->rsrc);
 138        if (window->virt) {
 139                iounmap(window->virt);
 140                window->virt = NULL;
 141                window->phys = 0;
 142                window->size = 0;
 143        }
 144        pci_dev_put(window->pdev);
 145}
 146
 147static int __init esb2rom_init_one(struct pci_dev *pdev,
 148                                   const struct pci_device_id *ent)
 149{
 150        static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL };
 151        struct esb2rom_window *window = &esb2rom_window;
 152        struct esb2rom_map_info *map = NULL;
 153        unsigned long map_top;
 154        u8 byte;
 155        u16 word;
 156
 157        /* For now I just handle the ecb2 and I assume there
 158         * are not a lot of resources up at the top of the address
 159         * space.  It is possible to handle other devices in the
 160         * top 16MiB but it is very painful.  Also since
 161         * you can only really attach a FWH to an ICHX there
 162         * a number of simplifications you can make.
 163         *
 164         * Also you can page firmware hubs if an 8MiB window isn't enough
 165         * but don't currently handle that case either.
 166         */
 167        window->pdev = pci_dev_get(pdev);
 168
 169        /* RLG:  experiment 2.  Force the window registers to the widest values */
 170
 171/*
 172        pci_read_config_word(pdev, FWH_DEC_EN1, &word);
 173        printk(KERN_DEBUG "Original FWH_DEC_EN1 : %x\n", word);
 174        pci_write_config_byte(pdev, FWH_DEC_EN1, 0xff);
 175        pci_read_config_byte(pdev, FWH_DEC_EN1, &byte);
 176        printk(KERN_DEBUG "New FWH_DEC_EN1 : %x\n", byte);
 177
 178        pci_read_config_byte(pdev, FWH_DEC_EN2, &byte);
 179        printk(KERN_DEBUG "Original FWH_DEC_EN2 : %x\n", byte);
 180        pci_write_config_byte(pdev, FWH_DEC_EN2, 0x0f);
 181        pci_read_config_byte(pdev, FWH_DEC_EN2, &byte);
 182        printk(KERN_DEBUG "New FWH_DEC_EN2 : %x\n", byte);
 183*/
 184
 185        /* Find a region continuous to the end of the ROM window  */
 186        window->phys = 0;
 187        pci_read_config_word(pdev, FWH_DEC_EN1, &word);
 188        printk(KERN_DEBUG "pci_read_config_word : %x\n", word);
 189
 190        if ((word & FWH_8MiB) == FWH_8MiB)
 191                window->phys = 0xff400000;
 192        else if ((word & FWH_7MiB) == FWH_7MiB)
 193                window->phys = 0xff500000;
 194        else if ((word & FWH_6MiB) == FWH_6MiB)
 195                window->phys = 0xff600000;
 196        else if ((word & FWH_5MiB) == FWH_5MiB)
 197                window->phys = 0xFF700000;
 198        else if ((word & FWH_4MiB) == FWH_4MiB)
 199                window->phys = 0xffc00000;
 200        else if ((word & FWH_3_5MiB) == FWH_3_5MiB)
 201                window->phys = 0xffc80000;
 202        else if ((word & FWH_3MiB) == FWH_3MiB)
 203                window->phys = 0xffd00000;
 204        else if ((word & FWH_2_5MiB) == FWH_2_5MiB)
 205                window->phys = 0xffd80000;
 206        else if ((word & FWH_2MiB) == FWH_2MiB)
 207                window->phys = 0xffe00000;
 208        else if ((word & FWH_1_5MiB) == FWH_1_5MiB)
 209                window->phys = 0xffe80000;
 210        else if ((word & FWH_1MiB) == FWH_1MiB)
 211                window->phys = 0xfff00000;
 212        else if ((word & FWH_0_5MiB) == FWH_0_5MiB)
 213                window->phys = 0xfff80000;
 214
 215        if (window->phys == 0) {
 216                printk(KERN_ERR MOD_NAME ": Rom window is closed\n");
 217                goto out;
 218        }
 219
 220        /* reserved  0x0020 and 0x0010 */
 221        window->phys -= 0x400000UL;
 222        window->size = (0xffffffffUL - window->phys) + 1UL;
 223
 224        /* Enable writes through the rom window */
 225        pci_read_config_byte(pdev, BIOS_CNTL, &byte);
 226        if (!(byte & BIOS_WRITE_ENABLE)  && (byte & (BIOS_LOCK_ENABLE))) {
 227                /* The BIOS will generate an error if I enable
 228                 * this device, so don't even try.
 229                 */
 230                printk(KERN_ERR MOD_NAME ": firmware access control, I can't enable writes\n");
 231                goto out;
 232        }
 233        pci_write_config_byte(pdev, BIOS_CNTL, byte | BIOS_WRITE_ENABLE);
 234
 235        /*
 236         * Try to reserve the window mem region.  If this fails then
 237         * it is likely due to the window being "reserved" by the BIOS.
 238         */
 239        window->rsrc.name = MOD_NAME;
 240        window->rsrc.start = window->phys;
 241        window->rsrc.end   = window->phys + window->size - 1;
 242        window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 243        if (request_resource(&iomem_resource, &window->rsrc)) {
 244                window->rsrc.parent = NULL;
 245                printk(KERN_DEBUG MOD_NAME ": "
 246                       "%s(): Unable to register resource %pR - kernel bug?\n",
 247                        __func__, &window->rsrc);
 248        }
 249
 250        /* Map the firmware hub into my address space. */
 251        window->virt = ioremap_nocache(window->phys, window->size);
 252        if (!window->virt) {
 253                printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n",
 254                        window->phys, window->size);
 255                goto out;
 256        }
 257
 258        /* Get the first address to look for an rom chip at */
 259        map_top = window->phys;
 260        if ((window->phys & 0x3fffff) != 0) {
 261                /* if not aligned on 4MiB, look 4MiB lower in address space */
 262                map_top = window->phys + 0x400000;
 263        }
 264#if 1
 265        /* The probe sequence run over the firmware hub lock
 266         * registers sets them to 0x7 (no access).
 267         * (Insane hardware design, but most copied Intel's.)
 268         * ==> Probe at most the last 4M of the address space.
 269         */
 270        if (map_top < 0xffc00000)
 271                map_top = 0xffc00000;
 272#endif
 273        /* Loop through and look for rom chips */
 274        while ((map_top - 1) < 0xffffffffUL) {
 275                struct cfi_private *cfi;
 276                unsigned long offset;
 277                int i;
 278
 279                if (!map)
 280                        map = kmalloc(sizeof(*map), GFP_KERNEL);
 281                if (!map) {
 282                        printk(KERN_ERR MOD_NAME ": kmalloc failed");
 283                        goto out;
 284                }
 285                memset(map, 0, sizeof(*map));
 286                INIT_LIST_HEAD(&map->list);
 287                map->map.name = map->map_name;
 288                map->map.phys = map_top;
 289                offset = map_top - window->phys;
 290                map->map.virt = (void __iomem *)
 291                        (((unsigned long)(window->virt)) + offset);
 292                map->map.size = 0xffffffffUL - map_top + 1UL;
 293                /* Set the name of the map to the address I am trying */
 294                sprintf(map->map_name, "%s @%08Lx",
 295                        MOD_NAME, (unsigned long long)map->map.phys);
 296
 297                /* Firmware hubs only use vpp when being programmed
 298                 * in a factory setting.  So in-place programming
 299                 * needs to use a different method.
 300                 */
 301                for(map->map.bankwidth = 32; map->map.bankwidth;
 302                        map->map.bankwidth >>= 1) {
 303                        char **probe_type;
 304                        /* Skip bankwidths that are not supported */
 305                        if (!map_bankwidth_supported(map->map.bankwidth))
 306                                continue;
 307
 308                        /* Setup the map methods */
 309                        simple_map_init(&map->map);
 310
 311                        /* Try all of the probe methods */
 312                        probe_type = rom_probe_types;
 313                        for(; *probe_type; probe_type++) {
 314                                map->mtd = do_map_probe(*probe_type, &map->map);
 315                                if (map->mtd)
 316                                        goto found;
 317                        }
 318                }
 319                map_top += ROM_PROBE_STEP_SIZE;
 320                continue;
 321        found:
 322                /* Trim the size if we are larger than the map */
 323                if (map->mtd->size > map->map.size) {
 324                        printk(KERN_WARNING MOD_NAME
 325                                " rom(%llu) larger than window(%lu). fixing...\n",
 326                                (unsigned long long)map->mtd->size, map->map.size);
 327                        map->mtd->size = map->map.size;
 328                }
 329                if (window->rsrc.parent) {
 330                        /*
 331                         * Registering the MTD device in iomem may not be possible
 332                         * if there is a BIOS "reserved" and BUSY range.  If this
 333                         * fails then continue anyway.
 334                         */
 335                        map->rsrc.name  = map->map_name;
 336                        map->rsrc.start = map->map.phys;
 337                        map->rsrc.end   = map->map.phys + map->mtd->size - 1;
 338                        map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 339                        if (request_resource(&window->rsrc, &map->rsrc)) {
 340                                printk(KERN_ERR MOD_NAME
 341                                        ": cannot reserve MTD resource\n");
 342                                map->rsrc.parent = NULL;
 343                        }
 344                }
 345
 346                /* Make the whole region visible in the map */
 347                map->map.virt = window->virt;
 348                map->map.phys = window->phys;
 349                cfi = map->map.fldrv_priv;
 350                for(i = 0; i < cfi->numchips; i++)
 351                        cfi->chips[i].start += offset;
 352
 353                /* Now that the mtd devices is complete claim and export it */
 354                map->mtd->owner = THIS_MODULE;
 355                if (mtd_device_register(map->mtd, NULL, 0)) {
 356                        map_destroy(map->mtd);
 357                        map->mtd = NULL;
 358                        goto out;
 359                }
 360
 361                /* Calculate the new value of map_top */
 362                map_top += map->mtd->size;
 363
 364                /* File away the map structure */
 365                list_add(&map->list, &window->maps);
 366                map = NULL;
 367        }
 368
 369 out:
 370        /* Free any left over map structures */
 371        kfree(map);
 372
 373        /* See if I have any map structures */
 374        if (list_empty(&window->maps)) {
 375                esb2rom_cleanup(window);
 376                return -ENODEV;
 377        }
 378        return 0;
 379}
 380
 381static void esb2rom_remove_one(struct pci_dev *pdev)
 382{
 383        struct esb2rom_window *window = &esb2rom_window;
 384        esb2rom_cleanup(window);
 385}
 386
 387static const struct pci_device_id esb2rom_pci_tbl[] = {
 388        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0,
 389          PCI_ANY_ID, PCI_ANY_ID, },
 390        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
 391          PCI_ANY_ID, PCI_ANY_ID, },
 392        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
 393          PCI_ANY_ID, PCI_ANY_ID, },
 394        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
 395          PCI_ANY_ID, PCI_ANY_ID, },
 396        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
 397          PCI_ANY_ID, PCI_ANY_ID, },
 398        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
 399          PCI_ANY_ID, PCI_ANY_ID, },
 400        { 0, },
 401};
 402
 403#if 0
 404MODULE_DEVICE_TABLE(pci, esb2rom_pci_tbl);
 405
 406static struct pci_driver esb2rom_driver = {
 407        .name =         MOD_NAME,
 408        .id_table =     esb2rom_pci_tbl,
 409        .probe =        esb2rom_init_one,
 410        .remove =       esb2rom_remove_one,
 411};
 412#endif
 413
 414static int __init init_esb2rom(void)
 415{
 416        struct pci_dev *pdev;
 417        const struct pci_device_id *id;
 418        int retVal;
 419
 420        pdev = NULL;
 421        for (id = esb2rom_pci_tbl; id->vendor; id++) {
 422                printk(KERN_DEBUG "device id = %x\n", id->device);
 423                pdev = pci_get_device(id->vendor, id->device, NULL);
 424                if (pdev) {
 425                        printk(KERN_DEBUG "matched device = %x\n", id->device);
 426                        break;
 427                }
 428        }
 429        if (pdev) {
 430                printk(KERN_DEBUG "matched device id %x\n", id->device);
 431                retVal = esb2rom_init_one(pdev, &esb2rom_pci_tbl[0]);
 432                pci_dev_put(pdev);
 433                printk(KERN_DEBUG "retVal = %d\n", retVal);
 434                return retVal;
 435        }
 436        return -ENXIO;
 437#if 0
 438        return pci_register_driver(&esb2rom_driver);
 439#endif
 440}
 441
 442static void __exit cleanup_esb2rom(void)
 443{
 444        esb2rom_remove_one(esb2rom_window.pdev);
 445}
 446
 447module_init(init_esb2rom);
 448module_exit(cleanup_esb2rom);
 449
 450MODULE_LICENSE("GPL");
 451MODULE_AUTHOR("Lew Glendenning <lglendenning@lnxi.com>");
 452MODULE_DESCRIPTION("MTD map driver for BIOS chips on the ESB2 southbridge");
 453