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8#include <linux/clk.h>
9#include <linux/errno.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/interrupt.h>
13#include <linux/module.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/partitions.h>
16#include <linux/mtd/spi-nor.h>
17#include <linux/mutex.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21#include <linux/reset.h>
22#include <linux/sizes.h>
23
24#define QUADSPI_CR 0x00
25#define CR_EN BIT(0)
26#define CR_ABORT BIT(1)
27#define CR_DMAEN BIT(2)
28#define CR_TCEN BIT(3)
29#define CR_SSHIFT BIT(4)
30#define CR_DFM BIT(6)
31#define CR_FSEL BIT(7)
32#define CR_FTHRES_SHIFT 8
33#define CR_FTHRES_MASK GENMASK(12, 8)
34#define CR_FTHRES(n) (((n) << CR_FTHRES_SHIFT) & CR_FTHRES_MASK)
35#define CR_TEIE BIT(16)
36#define CR_TCIE BIT(17)
37#define CR_FTIE BIT(18)
38#define CR_SMIE BIT(19)
39#define CR_TOIE BIT(20)
40#define CR_PRESC_SHIFT 24
41#define CR_PRESC_MASK GENMASK(31, 24)
42#define CR_PRESC(n) (((n) << CR_PRESC_SHIFT) & CR_PRESC_MASK)
43
44#define QUADSPI_DCR 0x04
45#define DCR_CSHT_SHIFT 8
46#define DCR_CSHT_MASK GENMASK(10, 8)
47#define DCR_CSHT(n) (((n) << DCR_CSHT_SHIFT) & DCR_CSHT_MASK)
48#define DCR_FSIZE_SHIFT 16
49#define DCR_FSIZE_MASK GENMASK(20, 16)
50#define DCR_FSIZE(n) (((n) << DCR_FSIZE_SHIFT) & DCR_FSIZE_MASK)
51
52#define QUADSPI_SR 0x08
53#define SR_TEF BIT(0)
54#define SR_TCF BIT(1)
55#define SR_FTF BIT(2)
56#define SR_SMF BIT(3)
57#define SR_TOF BIT(4)
58#define SR_BUSY BIT(5)
59#define SR_FLEVEL_SHIFT 8
60#define SR_FLEVEL_MASK GENMASK(13, 8)
61
62#define QUADSPI_FCR 0x0c
63#define FCR_CTCF BIT(1)
64
65#define QUADSPI_DLR 0x10
66
67#define QUADSPI_CCR 0x14
68#define CCR_INST_SHIFT 0
69#define CCR_INST_MASK GENMASK(7, 0)
70#define CCR_INST(n) (((n) << CCR_INST_SHIFT) & CCR_INST_MASK)
71#define CCR_IMODE_NONE (0U << 8)
72#define CCR_IMODE_1 (1U << 8)
73#define CCR_IMODE_2 (2U << 8)
74#define CCR_IMODE_4 (3U << 8)
75#define CCR_ADMODE_NONE (0U << 10)
76#define CCR_ADMODE_1 (1U << 10)
77#define CCR_ADMODE_2 (2U << 10)
78#define CCR_ADMODE_4 (3U << 10)
79#define CCR_ADSIZE_SHIFT 12
80#define CCR_ADSIZE_MASK GENMASK(13, 12)
81#define CCR_ADSIZE(n) (((n) << CCR_ADSIZE_SHIFT) & CCR_ADSIZE_MASK)
82#define CCR_ABMODE_NONE (0U << 14)
83#define CCR_ABMODE_1 (1U << 14)
84#define CCR_ABMODE_2 (2U << 14)
85#define CCR_ABMODE_4 (3U << 14)
86#define CCR_ABSIZE_8 (0U << 16)
87#define CCR_ABSIZE_16 (1U << 16)
88#define CCR_ABSIZE_24 (2U << 16)
89#define CCR_ABSIZE_32 (3U << 16)
90#define CCR_DCYC_SHIFT 18
91#define CCR_DCYC_MASK GENMASK(22, 18)
92#define CCR_DCYC(n) (((n) << CCR_DCYC_SHIFT) & CCR_DCYC_MASK)
93#define CCR_DMODE_NONE (0U << 24)
94#define CCR_DMODE_1 (1U << 24)
95#define CCR_DMODE_2 (2U << 24)
96#define CCR_DMODE_4 (3U << 24)
97#define CCR_FMODE_INDW (0U << 26)
98#define CCR_FMODE_INDR (1U << 26)
99#define CCR_FMODE_APM (2U << 26)
100#define CCR_FMODE_MM (3U << 26)
101
102#define QUADSPI_AR 0x18
103#define QUADSPI_ABR 0x1c
104#define QUADSPI_DR 0x20
105#define QUADSPI_PSMKR 0x24
106#define QUADSPI_PSMAR 0x28
107#define QUADSPI_PIR 0x2c
108#define QUADSPI_LPTR 0x30
109#define LPTR_DFT_TIMEOUT 0x10
110
111#define FSIZE_VAL(size) (__fls(size) - 1)
112
113#define STM32_MAX_MMAP_SZ SZ_256M
114#define STM32_MAX_NORCHIP 2
115
116#define STM32_QSPI_FIFO_TIMEOUT_US 30000
117#define STM32_QSPI_BUSY_TIMEOUT_US 100000
118
119struct stm32_qspi_flash {
120 struct spi_nor nor;
121 struct stm32_qspi *qspi;
122 u32 cs;
123 u32 fsize;
124 u32 presc;
125 u32 read_mode;
126 bool registered;
127};
128
129struct stm32_qspi {
130 struct device *dev;
131 void __iomem *io_base;
132 void __iomem *mm_base;
133 resource_size_t mm_size;
134 u32 nor_num;
135 struct clk *clk;
136 u32 clk_rate;
137 struct stm32_qspi_flash flash[STM32_MAX_NORCHIP];
138 struct completion cmd_completion;
139
140
141
142
143
144 struct mutex lock;
145};
146
147struct stm32_qspi_cmd {
148 u8 addr_width;
149 u8 dummy;
150 bool tx_data;
151 u8 opcode;
152 u32 framemode;
153 u32 qspimode;
154 u32 addr;
155 size_t len;
156 void *buf;
157};
158
159static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi)
160{
161 u32 cr;
162 int err = 0;
163
164 if (readl_relaxed(qspi->io_base + QUADSPI_SR) & SR_TCF)
165 return 0;
166
167 reinit_completion(&qspi->cmd_completion);
168 cr = readl_relaxed(qspi->io_base + QUADSPI_CR);
169 writel_relaxed(cr | CR_TCIE, qspi->io_base + QUADSPI_CR);
170
171 if (!wait_for_completion_interruptible_timeout(&qspi->cmd_completion,
172 msecs_to_jiffies(1000)))
173 err = -ETIMEDOUT;
174
175 writel_relaxed(cr, qspi->io_base + QUADSPI_CR);
176 return err;
177}
178
179static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
180{
181 u32 sr;
182
183 return readl_relaxed_poll_timeout(qspi->io_base + QUADSPI_SR, sr,
184 !(sr & SR_BUSY), 10,
185 STM32_QSPI_BUSY_TIMEOUT_US);
186}
187
188static void stm32_qspi_set_framemode(struct spi_nor *nor,
189 struct stm32_qspi_cmd *cmd, bool read)
190{
191 u32 dmode = CCR_DMODE_1;
192
193 cmd->framemode = CCR_IMODE_1;
194
195 if (read) {
196 switch (nor->read_proto) {
197 default:
198 case SNOR_PROTO_1_1_1:
199 dmode = CCR_DMODE_1;
200 break;
201 case SNOR_PROTO_1_1_2:
202 dmode = CCR_DMODE_2;
203 break;
204 case SNOR_PROTO_1_1_4:
205 dmode = CCR_DMODE_4;
206 break;
207 }
208 }
209
210 cmd->framemode |= cmd->tx_data ? dmode : 0;
211 cmd->framemode |= cmd->addr_width ? CCR_ADMODE_1 : 0;
212}
213
214static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
215{
216 *val = readb_relaxed(addr);
217}
218
219static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
220{
221 writeb_relaxed(*val, addr);
222}
223
224static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
225 const struct stm32_qspi_cmd *cmd)
226{
227 void (*tx_fifo)(u8 *, void __iomem *);
228 u32 len = cmd->len, sr;
229 u8 *buf = cmd->buf;
230 int ret;
231
232 if (cmd->qspimode == CCR_FMODE_INDW)
233 tx_fifo = stm32_qspi_write_fifo;
234 else
235 tx_fifo = stm32_qspi_read_fifo;
236
237 while (len--) {
238 ret = readl_relaxed_poll_timeout(qspi->io_base + QUADSPI_SR,
239 sr, (sr & SR_FTF), 10,
240 STM32_QSPI_FIFO_TIMEOUT_US);
241 if (ret) {
242 dev_err(qspi->dev, "fifo timeout (stat:%#x)\n", sr);
243 break;
244 }
245 tx_fifo(buf++, qspi->io_base + QUADSPI_DR);
246 }
247
248 return ret;
249}
250
251static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
252 const struct stm32_qspi_cmd *cmd)
253{
254 memcpy_fromio(cmd->buf, qspi->mm_base + cmd->addr, cmd->len);
255 return 0;
256}
257
258static int stm32_qspi_tx(struct stm32_qspi *qspi,
259 const struct stm32_qspi_cmd *cmd)
260{
261 if (!cmd->tx_data)
262 return 0;
263
264 if (cmd->qspimode == CCR_FMODE_MM)
265 return stm32_qspi_tx_mm(qspi, cmd);
266
267 return stm32_qspi_tx_poll(qspi, cmd);
268}
269
270static int stm32_qspi_send(struct stm32_qspi_flash *flash,
271 const struct stm32_qspi_cmd *cmd)
272{
273 struct stm32_qspi *qspi = flash->qspi;
274 u32 ccr, dcr, cr;
275 int err;
276
277 err = stm32_qspi_wait_nobusy(qspi);
278 if (err)
279 goto abort;
280
281 dcr = readl_relaxed(qspi->io_base + QUADSPI_DCR) & ~DCR_FSIZE_MASK;
282 dcr |= DCR_FSIZE(flash->fsize);
283 writel_relaxed(dcr, qspi->io_base + QUADSPI_DCR);
284
285 cr = readl_relaxed(qspi->io_base + QUADSPI_CR);
286 cr &= ~CR_PRESC_MASK & ~CR_FSEL;
287 cr |= CR_PRESC(flash->presc);
288 cr |= flash->cs ? CR_FSEL : 0;
289 writel_relaxed(cr, qspi->io_base + QUADSPI_CR);
290
291 if (cmd->tx_data)
292 writel_relaxed(cmd->len - 1, qspi->io_base + QUADSPI_DLR);
293
294 ccr = cmd->framemode | cmd->qspimode;
295
296 if (cmd->dummy)
297 ccr |= CCR_DCYC(cmd->dummy);
298
299 if (cmd->addr_width)
300 ccr |= CCR_ADSIZE(cmd->addr_width - 1);
301
302 ccr |= CCR_INST(cmd->opcode);
303 writel_relaxed(ccr, qspi->io_base + QUADSPI_CCR);
304
305 if (cmd->addr_width && cmd->qspimode != CCR_FMODE_MM)
306 writel_relaxed(cmd->addr, qspi->io_base + QUADSPI_AR);
307
308 err = stm32_qspi_tx(qspi, cmd);
309 if (err)
310 goto abort;
311
312 if (cmd->qspimode != CCR_FMODE_MM) {
313 err = stm32_qspi_wait_cmd(qspi);
314 if (err)
315 goto abort;
316 writel_relaxed(FCR_CTCF, qspi->io_base + QUADSPI_FCR);
317 }
318
319 return err;
320
321abort:
322 cr = readl_relaxed(qspi->io_base + QUADSPI_CR) | CR_ABORT;
323 writel_relaxed(cr, qspi->io_base + QUADSPI_CR);
324
325 dev_err(qspi->dev, "%s abort err:%d\n", __func__, err);
326 return err;
327}
328
329static int stm32_qspi_read_reg(struct spi_nor *nor,
330 u8 opcode, u8 *buf, int len)
331{
332 struct stm32_qspi_flash *flash = nor->priv;
333 struct device *dev = flash->qspi->dev;
334 struct stm32_qspi_cmd cmd;
335
336 dev_dbg(dev, "read_reg: cmd:%#.2x buf:%p len:%#x\n", opcode, buf, len);
337
338 memset(&cmd, 0, sizeof(cmd));
339 cmd.opcode = opcode;
340 cmd.tx_data = true;
341 cmd.len = len;
342 cmd.buf = buf;
343 cmd.qspimode = CCR_FMODE_INDR;
344
345 stm32_qspi_set_framemode(nor, &cmd, false);
346
347 return stm32_qspi_send(flash, &cmd);
348}
349
350static int stm32_qspi_write_reg(struct spi_nor *nor, u8 opcode,
351 u8 *buf, int len)
352{
353 struct stm32_qspi_flash *flash = nor->priv;
354 struct device *dev = flash->qspi->dev;
355 struct stm32_qspi_cmd cmd;
356
357 dev_dbg(dev, "write_reg: cmd:%#.2x buf:%p len:%#x\n", opcode, buf, len);
358
359 memset(&cmd, 0, sizeof(cmd));
360 cmd.opcode = opcode;
361 cmd.tx_data = !!(buf && len > 0);
362 cmd.len = len;
363 cmd.buf = buf;
364 cmd.qspimode = CCR_FMODE_INDW;
365
366 stm32_qspi_set_framemode(nor, &cmd, false);
367
368 return stm32_qspi_send(flash, &cmd);
369}
370
371static ssize_t stm32_qspi_read(struct spi_nor *nor, loff_t from, size_t len,
372 u_char *buf)
373{
374 struct stm32_qspi_flash *flash = nor->priv;
375 struct stm32_qspi *qspi = flash->qspi;
376 struct stm32_qspi_cmd cmd;
377 int err;
378
379 dev_dbg(qspi->dev, "read(%#.2x): buf:%p from:%#.8x len:%#zx\n",
380 nor->read_opcode, buf, (u32)from, len);
381
382 memset(&cmd, 0, sizeof(cmd));
383 cmd.opcode = nor->read_opcode;
384 cmd.addr_width = nor->addr_width;
385 cmd.addr = (u32)from;
386 cmd.tx_data = true;
387 cmd.dummy = nor->read_dummy;
388 cmd.len = len;
389 cmd.buf = buf;
390 cmd.qspimode = flash->read_mode;
391
392 stm32_qspi_set_framemode(nor, &cmd, true);
393 err = stm32_qspi_send(flash, &cmd);
394
395 return err ? err : len;
396}
397
398static ssize_t stm32_qspi_write(struct spi_nor *nor, loff_t to, size_t len,
399 const u_char *buf)
400{
401 struct stm32_qspi_flash *flash = nor->priv;
402 struct device *dev = flash->qspi->dev;
403 struct stm32_qspi_cmd cmd;
404 int err;
405
406 dev_dbg(dev, "write(%#.2x): buf:%p to:%#.8x len:%#zx\n",
407 nor->program_opcode, buf, (u32)to, len);
408
409 memset(&cmd, 0, sizeof(cmd));
410 cmd.opcode = nor->program_opcode;
411 cmd.addr_width = nor->addr_width;
412 cmd.addr = (u32)to;
413 cmd.tx_data = true;
414 cmd.len = len;
415 cmd.buf = (void *)buf;
416 cmd.qspimode = CCR_FMODE_INDW;
417
418 stm32_qspi_set_framemode(nor, &cmd, false);
419 err = stm32_qspi_send(flash, &cmd);
420
421 return err ? err : len;
422}
423
424static int stm32_qspi_erase(struct spi_nor *nor, loff_t offs)
425{
426 struct stm32_qspi_flash *flash = nor->priv;
427 struct device *dev = flash->qspi->dev;
428 struct stm32_qspi_cmd cmd;
429
430 dev_dbg(dev, "erase(%#.2x):offs:%#x\n", nor->erase_opcode, (u32)offs);
431
432 memset(&cmd, 0, sizeof(cmd));
433 cmd.opcode = nor->erase_opcode;
434 cmd.addr_width = nor->addr_width;
435 cmd.addr = (u32)offs;
436 cmd.qspimode = CCR_FMODE_INDW;
437
438 stm32_qspi_set_framemode(nor, &cmd, false);
439
440 return stm32_qspi_send(flash, &cmd);
441}
442
443static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
444{
445 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
446 u32 cr, sr, fcr = 0;
447
448 cr = readl_relaxed(qspi->io_base + QUADSPI_CR);
449 sr = readl_relaxed(qspi->io_base + QUADSPI_SR);
450
451 if ((cr & CR_TCIE) && (sr & SR_TCF)) {
452
453 fcr |= FCR_CTCF;
454 complete(&qspi->cmd_completion);
455 } else {
456 dev_info_ratelimited(qspi->dev, "spurious interrupt\n");
457 }
458
459 writel_relaxed(fcr, qspi->io_base + QUADSPI_FCR);
460
461 return IRQ_HANDLED;
462}
463
464static int stm32_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
465{
466 struct stm32_qspi_flash *flash = nor->priv;
467 struct stm32_qspi *qspi = flash->qspi;
468
469 mutex_lock(&qspi->lock);
470 return 0;
471}
472
473static void stm32_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
474{
475 struct stm32_qspi_flash *flash = nor->priv;
476 struct stm32_qspi *qspi = flash->qspi;
477
478 mutex_unlock(&qspi->lock);
479}
480
481static int stm32_qspi_flash_setup(struct stm32_qspi *qspi,
482 struct device_node *np)
483{
484 struct spi_nor_hwcaps hwcaps = {
485 .mask = SNOR_HWCAPS_READ |
486 SNOR_HWCAPS_READ_FAST |
487 SNOR_HWCAPS_PP,
488 };
489 u32 width, presc, cs_num, max_rate = 0;
490 struct stm32_qspi_flash *flash;
491 struct mtd_info *mtd;
492 int ret;
493
494 of_property_read_u32(np, "reg", &cs_num);
495 if (cs_num >= STM32_MAX_NORCHIP)
496 return -EINVAL;
497
498 of_property_read_u32(np, "spi-max-frequency", &max_rate);
499 if (!max_rate)
500 return -EINVAL;
501
502 presc = DIV_ROUND_UP(qspi->clk_rate, max_rate) - 1;
503
504 if (of_property_read_u32(np, "spi-rx-bus-width", &width))
505 width = 1;
506
507 if (width == 4)
508 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
509 else if (width == 2)
510 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
511 else if (width != 1)
512 return -EINVAL;
513
514 flash = &qspi->flash[cs_num];
515 flash->qspi = qspi;
516 flash->cs = cs_num;
517 flash->presc = presc;
518
519 flash->nor.dev = qspi->dev;
520 spi_nor_set_flash_node(&flash->nor, np);
521 flash->nor.priv = flash;
522 mtd = &flash->nor.mtd;
523
524 flash->nor.read = stm32_qspi_read;
525 flash->nor.write = stm32_qspi_write;
526 flash->nor.erase = stm32_qspi_erase;
527 flash->nor.read_reg = stm32_qspi_read_reg;
528 flash->nor.write_reg = stm32_qspi_write_reg;
529 flash->nor.prepare = stm32_qspi_prep;
530 flash->nor.unprepare = stm32_qspi_unprep;
531
532 writel_relaxed(LPTR_DFT_TIMEOUT, qspi->io_base + QUADSPI_LPTR);
533
534 writel_relaxed(CR_PRESC(presc) | CR_FTHRES(3) | CR_TCEN | CR_SSHIFT
535 | CR_EN, qspi->io_base + QUADSPI_CR);
536
537
538
539
540
541
542
543
544 flash->fsize = FSIZE_VAL(SZ_1K);
545
546 ret = spi_nor_scan(&flash->nor, NULL, &hwcaps);
547 if (ret) {
548 dev_err(qspi->dev, "device scan failed\n");
549 return ret;
550 }
551
552 flash->fsize = FSIZE_VAL(mtd->size);
553
554 flash->read_mode = CCR_FMODE_MM;
555 if (mtd->size > qspi->mm_size)
556 flash->read_mode = CCR_FMODE_INDR;
557
558 writel_relaxed(DCR_CSHT(1), qspi->io_base + QUADSPI_DCR);
559
560 ret = mtd_device_register(mtd, NULL, 0);
561 if (ret) {
562 dev_err(qspi->dev, "mtd device parse failed\n");
563 return ret;
564 }
565
566 flash->registered = true;
567
568 dev_dbg(qspi->dev, "read mm:%s cs:%d bus:%d\n",
569 flash->read_mode == CCR_FMODE_MM ? "yes" : "no", cs_num, width);
570
571 return 0;
572}
573
574static void stm32_qspi_mtd_free(struct stm32_qspi *qspi)
575{
576 int i;
577
578 for (i = 0; i < STM32_MAX_NORCHIP; i++)
579 if (qspi->flash[i].registered)
580 mtd_device_unregister(&qspi->flash[i].nor.mtd);
581}
582
583static int stm32_qspi_probe(struct platform_device *pdev)
584{
585 struct device *dev = &pdev->dev;
586 struct device_node *flash_np;
587 struct reset_control *rstc;
588 struct stm32_qspi *qspi;
589 struct resource *res;
590 int ret, irq;
591
592 qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL);
593 if (!qspi)
594 return -ENOMEM;
595
596 qspi->nor_num = of_get_child_count(dev->of_node);
597 if (!qspi->nor_num || qspi->nor_num > STM32_MAX_NORCHIP)
598 return -ENODEV;
599
600 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
601 qspi->io_base = devm_ioremap_resource(dev, res);
602 if (IS_ERR(qspi->io_base))
603 return PTR_ERR(qspi->io_base);
604
605 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
606 qspi->mm_base = devm_ioremap_resource(dev, res);
607 if (IS_ERR(qspi->mm_base))
608 return PTR_ERR(qspi->mm_base);
609
610 qspi->mm_size = resource_size(res);
611
612 irq = platform_get_irq(pdev, 0);
613 ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
614 dev_name(dev), qspi);
615 if (ret) {
616 dev_err(dev, "failed to request irq\n");
617 return ret;
618 }
619
620 init_completion(&qspi->cmd_completion);
621
622 qspi->clk = devm_clk_get(dev, NULL);
623 if (IS_ERR(qspi->clk))
624 return PTR_ERR(qspi->clk);
625
626 qspi->clk_rate = clk_get_rate(qspi->clk);
627 if (!qspi->clk_rate)
628 return -EINVAL;
629
630 ret = clk_prepare_enable(qspi->clk);
631 if (ret) {
632 dev_err(dev, "can not enable the clock\n");
633 return ret;
634 }
635
636 rstc = devm_reset_control_get(dev, NULL);
637 if (!IS_ERR(rstc)) {
638 reset_control_assert(rstc);
639 udelay(2);
640 reset_control_deassert(rstc);
641 }
642
643 qspi->dev = dev;
644 platform_set_drvdata(pdev, qspi);
645 mutex_init(&qspi->lock);
646
647 for_each_available_child_of_node(dev->of_node, flash_np) {
648 ret = stm32_qspi_flash_setup(qspi, flash_np);
649 if (ret) {
650 dev_err(dev, "unable to setup flash chip\n");
651 goto err_flash;
652 }
653 }
654
655 return 0;
656
657err_flash:
658 mutex_destroy(&qspi->lock);
659 stm32_qspi_mtd_free(qspi);
660
661 clk_disable_unprepare(qspi->clk);
662 return ret;
663}
664
665static int stm32_qspi_remove(struct platform_device *pdev)
666{
667 struct stm32_qspi *qspi = platform_get_drvdata(pdev);
668
669
670 writel_relaxed(0, qspi->io_base + QUADSPI_CR);
671
672 stm32_qspi_mtd_free(qspi);
673 mutex_destroy(&qspi->lock);
674
675 clk_disable_unprepare(qspi->clk);
676 return 0;
677}
678
679static const struct of_device_id stm32_qspi_match[] = {
680 {.compatible = "st,stm32f469-qspi"},
681 {}
682};
683MODULE_DEVICE_TABLE(of, stm32_qspi_match);
684
685static struct platform_driver stm32_qspi_driver = {
686 .probe = stm32_qspi_probe,
687 .remove = stm32_qspi_remove,
688 .driver = {
689 .name = "stm32-quadspi",
690 .of_match_table = stm32_qspi_match,
691 },
692};
693module_platform_driver(stm32_qspi_driver);
694
695MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
696MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
697MODULE_LICENSE("GPL v2");
698
