LXR linux/drivers/net/ethernet/aquantia/atlantic/aq

   1/*
   2 * aQuantia Corporation Network Driver
   3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms and conditions of the GNU General Public License,
   7 * version 2, as published by the Free Software Foundation.
   8 */
   9
  10/* File aq_ring.h: Declaration of functions for Rx/Tx rings. */
  11
  12#ifndef AQ_RING_H
  13#define AQ_RING_H
  14
  15#include "aq_common.h"
  16
  17struct page;
  18
  19/*           TxC       SOP        DX         EOP
  20 *         +----------+----------+----------+-----------
  21 *   8bytes|len l3,l4 | pa       | pa       | pa
  22 *         +----------+----------+----------+-----------
  23 * 4/8bytes|len pkt   |len pkt   |          | skb
  24 *         +----------+----------+----------+-----------
  25 * 4/8bytes|is_txc    |len,flags |len       |len,is_eop
  26 *         +----------+----------+----------+-----------
  27 *
  28 *  This aq_ring_buff_s doesn't have endianness dependency.
  29 *  It is __packed for cache line optimizations.
  30 */
  31struct __packed aq_ring_buff_s {
  32        union {
  33                /* RX */
  34                struct {
  35                        u32 rss_hash;
  36                        u16 next;
  37                        u8 is_hash_l4;
  38                        u8 rsvd1;
  39                        struct page *page;
  40                };
  41                /* EOP */
  42                struct {
  43                        dma_addr_t pa_eop;
  44                        struct sk_buff *skb;
  45                };
  46                /* DX */
  47                struct {
  48                        dma_addr_t pa;
  49                };
  50                /* SOP */
  51                struct {
  52                        dma_addr_t pa_sop;
  53                        u32 len_pkt_sop;
  54                };
  55                /* TxC */
  56                struct {
  57                        u32 mss;
  58                        u8 len_l2;
  59                        u8 len_l3;
  60                        u8 len_l4;
  61                        u8 is_ipv6:1;
  62                        u8 rsvd2:7;
  63                        u32 len_pkt;
  64                };
  65        };
  66        union {
  67                struct {
  68                        u16 len;
  69                        u32 is_ip_cso:1;
  70                        u32 is_udp_cso:1;
  71                        u32 is_tcp_cso:1;
  72                        u32 is_cso_err:1;
  73                        u32 is_sop:1;
  74                        u32 is_eop:1;
  75                        u32 is_txc:1;
  76                        u32 is_mapped:1;
  77                        u32 is_cleaned:1;
  78                        u32 is_error:1;
  79                        u32 rsvd3:6;
  80                        u16 eop_index;
  81                        u16 rsvd4;
  82                };
  83                u64 flags;
  84        };
  85};
  86
  87struct aq_ring_stats_rx_s {
  88        u64 errors;
  89        u64 packets;
  90        u64 bytes;
  91        u64 lro_packets;
  92        u64 jumbo_packets;
  93};
  94
  95struct aq_ring_stats_tx_s {
  96        u64 errors;
  97        u64 packets;
  98        u64 bytes;
  99        u64 queue_restarts;
 100};
 101
 102union aq_ring_stats_s {
 103        struct aq_ring_stats_rx_s rx;
 104        struct aq_ring_stats_tx_s tx;
 105};
 106
 107struct aq_ring_s {
 108        struct aq_obj_s header;
 109        struct aq_ring_buff_s *buff_ring;
 110        u8 *dx_ring;            /* descriptors ring, dma shared mem */
 111        struct aq_nic_s *aq_nic;
 112        unsigned int idx;       /* for HW layer registers operations */
 113        unsigned int hw_head;
 114        unsigned int sw_head;
 115        unsigned int sw_tail;
 116        unsigned int size;      /* descriptors number */
 117        unsigned int dx_size;   /* TX or RX descriptor size,  */
 118                                /* stored here for fater math */
 119        union aq_ring_stats_s stats;
 120        dma_addr_t dx_ring_pa;
 121};
 122
 123struct aq_ring_param_s {
 124        unsigned int vec_idx;
 125        unsigned int cpu;
 126        cpumask_t affinity_mask;
 127};
 128
 129static inline unsigned int aq_ring_next_dx(struct aq_ring_s *self,
 130                                           unsigned int dx)
 131{
 132        return (++dx >= self->size) ? 0U : dx;
 133}
 134
 135static inline unsigned int aq_ring_avail_dx(struct aq_ring_s *self)
 136{
 137        return (((self->sw_tail >= self->sw_head)) ?
 138                (self->size - 1) - self->sw_tail + self->sw_head :
 139                self->sw_head - self->sw_tail - 1);
 140}
 141
 142struct aq_ring_s *aq_ring_tx_alloc(struct aq_ring_s *self,
 143                                   struct aq_nic_s *aq_nic,
 144                                   unsigned int idx,
 145                                   struct aq_nic_cfg_s *aq_nic_cfg);
 146struct aq_ring_s *aq_ring_rx_alloc(struct aq_ring_s *self,
 147                                   struct aq_nic_s *aq_nic,
 148                                   unsigned int idx,
 149                                   struct aq_nic_cfg_s *aq_nic_cfg);
 150int aq_ring_init(struct aq_ring_s *self);
 151void aq_ring_rx_deinit(struct aq_ring_s *self);
 152void aq_ring_free(struct aq_ring_s *self);
 153void aq_ring_update_queue_state(struct aq_ring_s *ring);
 154void aq_ring_queue_wake(struct aq_ring_s *ring);
 155void aq_ring_queue_stop(struct aq_ring_s *ring);
 156void aq_ring_tx_clean(struct aq_ring_s *self);
 157int aq_ring_rx_clean(struct aq_ring_s *self,
 158                     struct napi_struct *napi,
 159                     int *work_done,
 160                     int budget);
 161int aq_ring_rx_fill(struct aq_ring_s *self);
 162
 163#endif /* AQ_RING_H */
 164