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23#ifndef _E1000_HW_H_
24#define _E1000_HW_H_
25
26#include <linux/types.h>
27#include <linux/delay.h>
28#include <linux/io.h>
29#include <linux/netdevice.h>
30
31#include "e1000_regs.h"
32#include "e1000_defines.h"
33
34struct e1000_hw;
35
36#define E1000_DEV_ID_82576 0x10C9
37#define E1000_DEV_ID_82576_FIBER 0x10E6
38#define E1000_DEV_ID_82576_SERDES 0x10E7
39#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
40#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
41#define E1000_DEV_ID_82576_NS 0x150A
42#define E1000_DEV_ID_82576_NS_SERDES 0x1518
43#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
44#define E1000_DEV_ID_82575EB_COPPER 0x10A7
45#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
46#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
47#define E1000_DEV_ID_82580_COPPER 0x150E
48#define E1000_DEV_ID_82580_FIBER 0x150F
49#define E1000_DEV_ID_82580_SERDES 0x1510
50#define E1000_DEV_ID_82580_SGMII 0x1511
51#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
52#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
53#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
54#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
55#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
56#define E1000_DEV_ID_DH89XXCC_SFP 0x0440
57#define E1000_DEV_ID_I350_COPPER 0x1521
58#define E1000_DEV_ID_I350_FIBER 0x1522
59#define E1000_DEV_ID_I350_SERDES 0x1523
60#define E1000_DEV_ID_I350_SGMII 0x1524
61#define E1000_DEV_ID_I210_COPPER 0x1533
62#define E1000_DEV_ID_I210_FIBER 0x1536
63#define E1000_DEV_ID_I210_SERDES 0x1537
64#define E1000_DEV_ID_I210_SGMII 0x1538
65#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B
66#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C
67#define E1000_DEV_ID_I211_COPPER 0x1539
68#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
69#define E1000_DEV_ID_I354_SGMII 0x1F41
70#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
71
72#define E1000_REVISION_2 2
73#define E1000_REVISION_4 4
74
75#define E1000_FUNC_0 0
76#define E1000_FUNC_1 1
77#define E1000_FUNC_2 2
78#define E1000_FUNC_3 3
79
80#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
81#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
82#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
83#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
84
85enum e1000_mac_type {
86 e1000_undefined = 0,
87 e1000_82575,
88 e1000_82576,
89 e1000_82580,
90 e1000_i350,
91 e1000_i354,
92 e1000_i210,
93 e1000_i211,
94 e1000_num_macs
95};
96
97enum e1000_media_type {
98 e1000_media_type_unknown = 0,
99 e1000_media_type_copper = 1,
100 e1000_media_type_fiber = 2,
101 e1000_media_type_internal_serdes = 3,
102 e1000_num_media_types
103};
104
105enum e1000_nvm_type {
106 e1000_nvm_unknown = 0,
107 e1000_nvm_none,
108 e1000_nvm_eeprom_spi,
109 e1000_nvm_flash_hw,
110 e1000_nvm_invm,
111 e1000_nvm_flash_sw
112};
113
114enum e1000_nvm_override {
115 e1000_nvm_override_none = 0,
116 e1000_nvm_override_spi_small,
117 e1000_nvm_override_spi_large,
118};
119
120enum e1000_phy_type {
121 e1000_phy_unknown = 0,
122 e1000_phy_none,
123 e1000_phy_m88,
124 e1000_phy_igp,
125 e1000_phy_igp_2,
126 e1000_phy_gg82563,
127 e1000_phy_igp_3,
128 e1000_phy_ife,
129 e1000_phy_82580,
130 e1000_phy_i210,
131 e1000_phy_bcm54616,
132};
133
134enum e1000_bus_type {
135 e1000_bus_type_unknown = 0,
136 e1000_bus_type_pci,
137 e1000_bus_type_pcix,
138 e1000_bus_type_pci_express,
139 e1000_bus_type_reserved
140};
141
142enum e1000_bus_speed {
143 e1000_bus_speed_unknown = 0,
144 e1000_bus_speed_33,
145 e1000_bus_speed_66,
146 e1000_bus_speed_100,
147 e1000_bus_speed_120,
148 e1000_bus_speed_133,
149 e1000_bus_speed_2500,
150 e1000_bus_speed_5000,
151 e1000_bus_speed_reserved
152};
153
154enum e1000_bus_width {
155 e1000_bus_width_unknown = 0,
156 e1000_bus_width_pcie_x1,
157 e1000_bus_width_pcie_x2,
158 e1000_bus_width_pcie_x4 = 4,
159 e1000_bus_width_pcie_x8 = 8,
160 e1000_bus_width_32,
161 e1000_bus_width_64,
162 e1000_bus_width_reserved
163};
164
165enum e1000_1000t_rx_status {
166 e1000_1000t_rx_status_not_ok = 0,
167 e1000_1000t_rx_status_ok,
168 e1000_1000t_rx_status_undefined = 0xFF
169};
170
171enum e1000_rev_polarity {
172 e1000_rev_polarity_normal = 0,
173 e1000_rev_polarity_reversed,
174 e1000_rev_polarity_undefined = 0xFF
175};
176
177enum e1000_fc_mode {
178 e1000_fc_none = 0,
179 e1000_fc_rx_pause,
180 e1000_fc_tx_pause,
181 e1000_fc_full,
182 e1000_fc_default = 0xFF
183};
184
185
186struct e1000_hw_stats {
187 u64 crcerrs;
188 u64 algnerrc;
189 u64 symerrs;
190 u64 rxerrc;
191 u64 mpc;
192 u64 scc;
193 u64 ecol;
194 u64 mcc;
195 u64 latecol;
196 u64 colc;
197 u64 dc;
198 u64 tncrs;
199 u64 sec;
200 u64 cexterr;
201 u64 rlec;
202 u64 xonrxc;
203 u64 xontxc;
204 u64 xoffrxc;
205 u64 xofftxc;
206 u64 fcruc;
207 u64 prc64;
208 u64 prc127;
209 u64 prc255;
210 u64 prc511;
211 u64 prc1023;
212 u64 prc1522;
213 u64 gprc;
214 u64 bprc;
215 u64 mprc;
216 u64 gptc;
217 u64 gorc;
218 u64 gotc;
219 u64 rnbc;
220 u64 ruc;
221 u64 rfc;
222 u64 roc;
223 u64 rjc;
224 u64 mgprc;
225 u64 mgpdc;
226 u64 mgptc;
227 u64 tor;
228 u64 tot;
229 u64 tpr;
230 u64 tpt;
231 u64 ptc64;
232 u64 ptc127;
233 u64 ptc255;
234 u64 ptc511;
235 u64 ptc1023;
236 u64 ptc1522;
237 u64 mptc;
238 u64 bptc;
239 u64 tsctc;
240 u64 tsctfc;
241 u64 iac;
242 u64 icrxptc;
243 u64 icrxatc;
244 u64 ictxptc;
245 u64 ictxatc;
246 u64 ictxqec;
247 u64 ictxqmtc;
248 u64 icrxdmtc;
249 u64 icrxoc;
250 u64 cbtmpc;
251 u64 htdpmc;
252 u64 cbrdpc;
253 u64 cbrmpc;
254 u64 rpthc;
255 u64 hgptc;
256 u64 htcbdpc;
257 u64 hgorc;
258 u64 hgotc;
259 u64 lenerrs;
260 u64 scvpc;
261 u64 hrmpc;
262 u64 doosync;
263 u64 o2bgptc;
264 u64 o2bspc;
265 u64 b2ospc;
266 u64 b2ogprc;
267};
268
269struct e1000_host_mng_dhcp_cookie {
270 u32 signature;
271 u8 status;
272 u8 reserved0;
273 u16 vlan_id;
274 u32 reserved1;
275 u16 reserved2;
276 u8 reserved3;
277 u8 checksum;
278};
279
280
281struct e1000_host_command_header {
282 u8 command_id;
283 u8 command_length;
284 u8 command_options;
285 u8 checksum;
286};
287
288#define E1000_HI_MAX_DATA_LENGTH 252
289struct e1000_host_command_info {
290 struct e1000_host_command_header command_header;
291 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
292};
293
294
295struct e1000_host_mng_command_header {
296 u8 command_id;
297 u8 checksum;
298 u16 reserved1;
299 u16 reserved2;
300 u16 command_length;
301};
302
303#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
304struct e1000_host_mng_command_info {
305 struct e1000_host_mng_command_header command_header;
306 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
307};
308
309#include "e1000_mac.h"
310#include "e1000_phy.h"
311#include "e1000_nvm.h"
312#include "e1000_mbx.h"
313
314struct e1000_mac_operations {
315 s32 (*check_for_link)(struct e1000_hw *);
316 s32 (*reset_hw)(struct e1000_hw *);
317 s32 (*init_hw)(struct e1000_hw *);
318 bool (*check_mng_mode)(struct e1000_hw *);
319 s32 (*setup_physical_interface)(struct e1000_hw *);
320 void (*rar_set)(struct e1000_hw *, u8 *, u32);
321 s32 (*read_mac_addr)(struct e1000_hw *);
322 s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
323 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
324 void (*release_swfw_sync)(struct e1000_hw *, u16);
325#ifdef CONFIG_IGB_HWMON
326 s32 (*get_thermal_sensor_data)(struct e1000_hw *);
327 s32 (*init_thermal_sensor_thresh)(struct e1000_hw *);
328#endif
329 void (*write_vfta)(struct e1000_hw *, u32, u32);
330};
331
332struct e1000_phy_operations {
333 s32 (*acquire)(struct e1000_hw *);
334 s32 (*check_polarity)(struct e1000_hw *);
335 s32 (*check_reset_block)(struct e1000_hw *);
336 s32 (*force_speed_duplex)(struct e1000_hw *);
337 s32 (*get_cfg_done)(struct e1000_hw *hw);
338 s32 (*get_cable_length)(struct e1000_hw *);
339 s32 (*get_phy_info)(struct e1000_hw *);
340 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
341 void (*release)(struct e1000_hw *);
342 s32 (*reset)(struct e1000_hw *);
343 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
344 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
345 s32 (*write_reg)(struct e1000_hw *, u32, u16);
346 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
347 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
348};
349
350struct e1000_nvm_operations {
351 s32 (*acquire)(struct e1000_hw *);
352 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
353 void (*release)(struct e1000_hw *);
354 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
355 s32 (*update)(struct e1000_hw *);
356 s32 (*validate)(struct e1000_hw *);
357 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
358};
359
360#define E1000_MAX_SENSORS 3
361
362struct e1000_thermal_diode_data {
363 u8 location;
364 u8 temp;
365 u8 caution_thresh;
366 u8 max_op_thresh;
367};
368
369struct e1000_thermal_sensor_data {
370 struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS];
371};
372
373struct e1000_info {
374 s32 (*get_invariants)(struct e1000_hw *);
375 struct e1000_mac_operations *mac_ops;
376 const struct e1000_phy_operations *phy_ops;
377 struct e1000_nvm_operations *nvm_ops;
378};
379
380extern const struct e1000_info e1000_82575_info;
381
382struct e1000_mac_info {
383 struct e1000_mac_operations ops;
384
385 u8 addr[6];
386 u8 perm_addr[6];
387
388 enum e1000_mac_type type;
389
390 u32 ledctl_default;
391 u32 ledctl_mode1;
392 u32 ledctl_mode2;
393 u32 mc_filter_type;
394 u32 txcw;
395
396 u16 mta_reg_count;
397 u16 uta_reg_count;
398
399
400 #define MAX_MTA_REG 128
401 u32 mta_shadow[MAX_MTA_REG];
402 u16 rar_entry_count;
403
404 u8 forced_speed_duplex;
405
406 bool adaptive_ifs;
407 bool arc_subsystem_valid;
408 bool asf_firmware_present;
409 bool autoneg;
410 bool autoneg_failed;
411 bool disable_hw_init_bits;
412 bool get_link_status;
413 bool ifs_params_forced;
414 bool in_ifs_mode;
415 bool report_tx_early;
416 bool serdes_has_link;
417 bool tx_pkt_filtering;
418 struct e1000_thermal_sensor_data thermal_sensor_data;
419};
420
421struct e1000_phy_info {
422 struct e1000_phy_operations ops;
423
424 enum e1000_phy_type type;
425
426 enum e1000_1000t_rx_status local_rx;
427 enum e1000_1000t_rx_status remote_rx;
428 enum e1000_ms_type ms_type;
429 enum e1000_ms_type original_ms_type;
430 enum e1000_rev_polarity cable_polarity;
431 enum e1000_smart_speed smart_speed;
432
433 u32 addr;
434 u32 id;
435 u32 reset_delay_us;
436 u32 revision;
437
438 enum e1000_media_type media_type;
439
440 u16 autoneg_advertised;
441 u16 autoneg_mask;
442 u16 cable_length;
443 u16 max_cable_length;
444 u16 min_cable_length;
445 u16 pair_length[4];
446
447 u8 mdix;
448
449 bool disable_polarity_correction;
450 bool is_mdix;
451 bool polarity_correction;
452 bool reset_disable;
453 bool speed_downgraded;
454 bool autoneg_wait_to_complete;
455};
456
457struct e1000_nvm_info {
458 struct e1000_nvm_operations ops;
459 enum e1000_nvm_type type;
460 enum e1000_nvm_override override;
461
462 u32 flash_bank_size;
463 u32 flash_base_addr;
464
465 u16 word_size;
466 u16 delay_usec;
467 u16 address_bits;
468 u16 opcode_bits;
469 u16 page_size;
470};
471
472struct e1000_bus_info {
473 enum e1000_bus_type type;
474 enum e1000_bus_speed speed;
475 enum e1000_bus_width width;
476
477 u32 snoop;
478
479 u16 func;
480 u16 pci_cmd_word;
481};
482
483struct e1000_fc_info {
484 u32 high_water;
485 u32 low_water;
486 u16 pause_time;
487 bool send_xon;
488 bool strict_ieee;
489 enum e1000_fc_mode current_mode;
490 enum e1000_fc_mode requested_mode;
491};
492
493struct e1000_mbx_operations {
494 s32 (*init_params)(struct e1000_hw *hw);
495 s32 (*read)(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id,
496 bool unlock);
497 s32 (*write)(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id);
498 s32 (*read_posted)(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id);
499 s32 (*write_posted)(struct e1000_hw *hw, u32 *msg, u16 size,
500 u16 mbx_id);
501 s32 (*check_for_msg)(struct e1000_hw *hw, u16 mbx_id);
502 s32 (*check_for_ack)(struct e1000_hw *hw, u16 mbx_id);
503 s32 (*check_for_rst)(struct e1000_hw *hw, u16 mbx_id);
504 s32 (*unlock)(struct e1000_hw *hw, u16 mbx_id);
505};
506
507struct e1000_mbx_stats {
508 u32 msgs_tx;
509 u32 msgs_rx;
510
511 u32 acks;
512 u32 reqs;
513 u32 rsts;
514};
515
516struct e1000_mbx_info {
517 struct e1000_mbx_operations ops;
518 struct e1000_mbx_stats stats;
519 u32 timeout;
520 u32 usec_delay;
521 u16 size;
522};
523
524struct e1000_dev_spec_82575 {
525 bool sgmii_active;
526 bool global_device_reset;
527 bool eee_disable;
528 bool clear_semaphore_once;
529 struct e1000_sfp_flags eth_flags;
530 bool module_plugged;
531 u8 media_port;
532 bool media_changed;
533 bool mas_capable;
534};
535
536struct e1000_hw {
537 void *back;
538
539 u8 __iomem *hw_addr;
540 u8 __iomem *flash_address;
541 unsigned long io_base;
542
543 struct e1000_mac_info mac;
544 struct e1000_fc_info fc;
545 struct e1000_phy_info phy;
546 struct e1000_nvm_info nvm;
547 struct e1000_bus_info bus;
548 struct e1000_mbx_info mbx;
549 struct e1000_host_mng_dhcp_cookie mng_cookie;
550
551 union {
552 struct e1000_dev_spec_82575 _82575;
553 } dev_spec;
554
555 u16 device_id;
556 u16 subsystem_vendor_id;
557 u16 subsystem_device_id;
558 u16 vendor_id;
559
560 u8 revision_id;
561};
562
563struct net_device *igb_get_hw_dev(struct e1000_hw *hw);
564#define hw_dbg(format, arg...) \
565 netdev_dbg(igb_get_hw_dev(hw), format, ##arg)
566
567
568s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
569s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
570
571void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
572void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
573#endif
574
