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29#ifndef _IXGB_HW_H_
30#define _IXGB_HW_H_
31
32#include <linux/mdio.h>
33
34#include "ixgb_osdep.h"
35
36
37typedef enum {
38 ixgb_mac_unknown = 0,
39 ixgb_82597,
40 ixgb_num_macs
41} ixgb_mac_type;
42
43
44typedef enum {
45 ixgb_phy_type_unknown = 0,
46 ixgb_phy_type_g6005,
47 ixgb_phy_type_g6104,
48 ixgb_phy_type_txn17201,
49 ixgb_phy_type_txn17401,
50 ixgb_phy_type_bcm
51} ixgb_phy_type;
52
53
54typedef enum {
55 ixgb_xpak_vendor_intel,
56 ixgb_xpak_vendor_infineon
57} ixgb_xpak_vendor;
58
59
60typedef enum {
61 ixgb_media_type_unknown = 0,
62 ixgb_media_type_fiber = 1,
63 ixgb_media_type_copper = 2,
64 ixgb_num_media_types
65} ixgb_media_type;
66
67
68typedef enum {
69 ixgb_fc_none = 0,
70 ixgb_fc_rx_pause = 1,
71 ixgb_fc_tx_pause = 2,
72 ixgb_fc_full = 3,
73 ixgb_fc_default = 0xFF
74} ixgb_fc_type;
75
76
77typedef enum {
78 ixgb_bus_type_unknown = 0,
79 ixgb_bus_type_pci,
80 ixgb_bus_type_pcix
81} ixgb_bus_type;
82
83
84typedef enum {
85 ixgb_bus_speed_unknown = 0,
86 ixgb_bus_speed_33,
87 ixgb_bus_speed_66,
88 ixgb_bus_speed_100,
89 ixgb_bus_speed_133,
90 ixgb_bus_speed_reserved
91} ixgb_bus_speed;
92
93
94typedef enum {
95 ixgb_bus_width_unknown = 0,
96 ixgb_bus_width_32,
97 ixgb_bus_width_64
98} ixgb_bus_width;
99
100#define IXGB_EEPROM_SIZE 64
101
102#define SPEED_10000 10000
103#define FULL_DUPLEX 2
104
105#define MIN_NUMBER_OF_DESCRIPTORS 8
106#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
107
108#define IXGB_DELAY_BEFORE_RESET 10
109#define IXGB_DELAY_AFTER_RESET 1
110#define IXGB_DELAY_AFTER_EE_RESET 10
111
112#define IXGB_DELAY_USECS_AFTER_LINK_RESET 13
113
114#define MAX_RESET_ITERATIONS 8
115
116
117#define IXGB_CTRL0 0x00000
118#define IXGB_CTRL1 0x00008
119#define IXGB_STATUS 0x00010
120#define IXGB_EECD 0x00018
121#define IXGB_MFS 0x00020
122
123
124#define IXGB_ICR 0x00080
125#define IXGB_ICS 0x00088
126#define IXGB_IMS 0x00090
127#define IXGB_IMC 0x00098
128
129
130#define IXGB_RCTL 0x00100
131#define IXGB_FCRTL 0x00108
132#define IXGB_FCRTH 0x00110
133#define IXGB_RDBAL 0x00118
134#define IXGB_RDBAH 0x0011C
135#define IXGB_RDLEN 0x00120
136#define IXGB_RDH 0x00128
137#define IXGB_RDT 0x00130
138#define IXGB_RDTR 0x00138
139#define IXGB_RXDCTL 0x00140
140#define IXGB_RAIDC 0x00148
141#define IXGB_RXCSUM 0x00158
142#define IXGB_RA 0x00180
143#define IXGB_RAL 0x00180
144#define IXGB_RAH 0x00184
145#define IXGB_MTA 0x00200
146#define IXGB_VFTA 0x00400
147#define IXGB_REQ_RX_DESCRIPTOR_MULTIPLE 8
148
149
150#define IXGB_TCTL 0x00600
151#define IXGB_TDBAL 0x00608
152#define IXGB_TDBAH 0x0060C
153#define IXGB_TDLEN 0x00610
154#define IXGB_TDH 0x00618
155#define IXGB_TDT 0x00620
156#define IXGB_TIDV 0x00628
157#define IXGB_TXDCTL 0x00630
158#define IXGB_TSPMT 0x00638
159#define IXGB_PAP 0x00640
160#define IXGB_REQ_TX_DESCRIPTOR_MULTIPLE 8
161
162
163#define IXGB_PCSC1 0x00700
164#define IXGB_PCSC2 0x00708
165#define IXGB_PCSS1 0x00710
166#define IXGB_PCSS2 0x00718
167#define IXGB_XPCSS 0x00720
168#define IXGB_UCCR 0x00728
169#define IXGB_XPCSTC 0x00730
170#define IXGB_MACA 0x00738
171#define IXGB_APAE 0x00740
172#define IXGB_ARD 0x00748
173#define IXGB_AIS 0x00750
174#define IXGB_MSCA 0x00758
175#define IXGB_MSRWD 0x00760
176
177
178#define IXGB_WUFC 0x00808
179#define IXGB_WUS 0x00810
180#define IXGB_FFLT 0x01000
181#define IXGB_FFMT 0x01020
182#define IXGB_FTVT 0x01420
183
184
185#define IXGB_TPRL 0x02000
186#define IXGB_TPRH 0x02004
187#define IXGB_GPRCL 0x02008
188#define IXGB_GPRCH 0x0200C
189#define IXGB_BPRCL 0x02010
190#define IXGB_BPRCH 0x02014
191#define IXGB_MPRCL 0x02018
192#define IXGB_MPRCH 0x0201C
193#define IXGB_UPRCL 0x02020
194#define IXGB_UPRCH 0x02024
195#define IXGB_VPRCL 0x02028
196#define IXGB_VPRCH 0x0202C
197#define IXGB_JPRCL 0x02030
198#define IXGB_JPRCH 0x02034
199#define IXGB_GORCL 0x02038
200#define IXGB_GORCH 0x0203C
201#define IXGB_TORL 0x02040
202#define IXGB_TORH 0x02044
203#define IXGB_RNBC 0x02048
204#define IXGB_RUC 0x02050
205#define IXGB_ROC 0x02058
206#define IXGB_RLEC 0x02060
207#define IXGB_CRCERRS 0x02068
208#define IXGB_ICBC 0x02070
209#define IXGB_ECBC 0x02078
210#define IXGB_MPC 0x02080
211#define IXGB_TPTL 0x02100
212#define IXGB_TPTH 0x02104
213#define IXGB_GPTCL 0x02108
214#define IXGB_GPTCH 0x0210C
215#define IXGB_BPTCL 0x02110
216#define IXGB_BPTCH 0x02114
217#define IXGB_MPTCL 0x02118
218#define IXGB_MPTCH 0x0211C
219#define IXGB_UPTCL 0x02120
220#define IXGB_UPTCH 0x02124
221#define IXGB_VPTCL 0x02128
222#define IXGB_VPTCH 0x0212C
223#define IXGB_JPTCL 0x02130
224#define IXGB_JPTCH 0x02134
225#define IXGB_GOTCL 0x02138
226#define IXGB_GOTCH 0x0213C
227#define IXGB_TOTL 0x02140
228#define IXGB_TOTH 0x02144
229#define IXGB_DC 0x02148
230#define IXGB_PLT64C 0x02150
231#define IXGB_TSCTC 0x02170
232#define IXGB_TSCTFC 0x02178
233#define IXGB_IBIC 0x02180
234#define IXGB_RFC 0x02188
235#define IXGB_LFC 0x02190
236#define IXGB_PFRC 0x02198
237#define IXGB_PFTC 0x021A0
238#define IXGB_MCFRC 0x021A8
239#define IXGB_MCFTC 0x021B0
240#define IXGB_XONRXC 0x021B8
241#define IXGB_XONTXC 0x021C0
242#define IXGB_XOFFRXC 0x021C8
243#define IXGB_XOFFTXC 0x021D0
244#define IXGB_RJC 0x021D8
245
246
247#define IXGB_CTRL0_LRST 0x00000008
248#define IXGB_CTRL0_JFE 0x00000010
249#define IXGB_CTRL0_XLE 0x00000020
250#define IXGB_CTRL0_MDCS 0x00000040
251#define IXGB_CTRL0_CMDC 0x00000080
252#define IXGB_CTRL0_SDP0 0x00040000
253#define IXGB_CTRL0_SDP1 0x00080000
254#define IXGB_CTRL0_SDP2 0x00100000
255#define IXGB_CTRL0_SDP3 0x00200000
256#define IXGB_CTRL0_SDP0_DIR 0x00400000
257#define IXGB_CTRL0_SDP1_DIR 0x00800000
258#define IXGB_CTRL0_SDP2_DIR 0x01000000
259#define IXGB_CTRL0_SDP3_DIR 0x02000000
260#define IXGB_CTRL0_RST 0x04000000
261#define IXGB_CTRL0_RPE 0x08000000
262#define IXGB_CTRL0_TPE 0x10000000
263#define IXGB_CTRL0_VME 0x40000000
264
265
266#define IXGB_CTRL1_GPI0_EN 0x00000001
267#define IXGB_CTRL1_GPI1_EN 0x00000002
268#define IXGB_CTRL1_GPI2_EN 0x00000004
269#define IXGB_CTRL1_GPI3_EN 0x00000008
270#define IXGB_CTRL1_SDP4 0x00000010
271#define IXGB_CTRL1_SDP5 0x00000020
272#define IXGB_CTRL1_SDP6 0x00000040
273#define IXGB_CTRL1_SDP7 0x00000080
274#define IXGB_CTRL1_SDP4_DIR 0x00000100
275#define IXGB_CTRL1_SDP5_DIR 0x00000200
276#define IXGB_CTRL1_SDP6_DIR 0x00000400
277#define IXGB_CTRL1_SDP7_DIR 0x00000800
278#define IXGB_CTRL1_EE_RST 0x00002000
279#define IXGB_CTRL1_RO_DIS 0x00020000
280#define IXGB_CTRL1_PCIXHM_MASK 0x00C00000
281#define IXGB_CTRL1_PCIXHM_1_2 0x00000000
282#define IXGB_CTRL1_PCIXHM_5_8 0x00400000
283#define IXGB_CTRL1_PCIXHM_3_4 0x00800000
284#define IXGB_CTRL1_PCIXHM_7_8 0x00C00000
285
286
287#define IXGB_STATUS_LU 0x00000002
288#define IXGB_STATUS_AIP 0x00000004
289#define IXGB_STATUS_TXOFF 0x00000010
290#define IXGB_STATUS_XAUIME 0x00000020
291#define IXGB_STATUS_RES 0x00000040
292#define IXGB_STATUS_RIS 0x00000080
293#define IXGB_STATUS_RIE 0x00000100
294#define IXGB_STATUS_RLF 0x00000200
295#define IXGB_STATUS_RRF 0x00000400
296#define IXGB_STATUS_PCI_SPD 0x00000800
297#define IXGB_STATUS_BUS64 0x00001000
298#define IXGB_STATUS_PCIX_MODE 0x00002000
299#define IXGB_STATUS_PCIX_SPD_MASK 0x0000C000
300#define IXGB_STATUS_PCIX_SPD_66 0x00000000
301#define IXGB_STATUS_PCIX_SPD_100 0x00004000
302#define IXGB_STATUS_PCIX_SPD_133 0x00008000
303#define IXGB_STATUS_REV_ID_MASK 0x000F0000
304#define IXGB_STATUS_REV_ID_SHIFT 16
305
306
307#define IXGB_EECD_SK 0x00000001
308#define IXGB_EECD_CS 0x00000002
309#define IXGB_EECD_DI 0x00000004
310#define IXGB_EECD_DO 0x00000008
311#define IXGB_EECD_FWE_MASK 0x00000030
312#define IXGB_EECD_FWE_DIS 0x00000010
313#define IXGB_EECD_FWE_EN 0x00000020
314
315
316#define IXGB_MFS_SHIFT 16
317
318
319#define IXGB_INT_TXDW 0x00000001
320#define IXGB_INT_TXQE 0x00000002
321#define IXGB_INT_LSC 0x00000004
322#define IXGB_INT_RXSEQ 0x00000008
323#define IXGB_INT_RXDMT0 0x00000010
324#define IXGB_INT_RXO 0x00000040
325#define IXGB_INT_RXT0 0x00000080
326#define IXGB_INT_AUTOSCAN 0x00000200
327#define IXGB_INT_GPI0 0x00000800
328#define IXGB_INT_GPI1 0x00001000
329#define IXGB_INT_GPI2 0x00002000
330#define IXGB_INT_GPI3 0x00004000
331
332
333#define IXGB_RCTL_RXEN 0x00000002
334#define IXGB_RCTL_SBP 0x00000004
335#define IXGB_RCTL_UPE 0x00000008
336#define IXGB_RCTL_MPE 0x00000010
337#define IXGB_RCTL_RDMTS_MASK 0x00000300
338#define IXGB_RCTL_RDMTS_1_2 0x00000000
339#define IXGB_RCTL_RDMTS_1_4 0x00000100
340#define IXGB_RCTL_RDMTS_1_8 0x00000200
341#define IXGB_RCTL_MO_MASK 0x00003000
342#define IXGB_RCTL_MO_47_36 0x00000000
343#define IXGB_RCTL_MO_46_35 0x00001000
344#define IXGB_RCTL_MO_45_34 0x00002000
345#define IXGB_RCTL_MO_43_32 0x00003000
346#define IXGB_RCTL_MO_SHIFT 12
347#define IXGB_RCTL_BAM 0x00008000
348#define IXGB_RCTL_BSIZE_MASK 0x00030000
349#define IXGB_RCTL_BSIZE_2048 0x00000000
350#define IXGB_RCTL_BSIZE_4096 0x00010000
351#define IXGB_RCTL_BSIZE_8192 0x00020000
352#define IXGB_RCTL_BSIZE_16384 0x00030000
353#define IXGB_RCTL_VFE 0x00040000
354#define IXGB_RCTL_CFIEN 0x00080000
355#define IXGB_RCTL_CFI 0x00100000
356#define IXGB_RCTL_RPDA_MASK 0x00600000
357#define IXGB_RCTL_RPDA_MC_MAC 0x00000000
358#define IXGB_RCTL_MC_ONLY 0x00400000
359#define IXGB_RCTL_CFF 0x00800000
360#define IXGB_RCTL_SECRC 0x04000000
361#define IXGB_RDT_FPDB 0x80000000
362
363#define IXGB_RCTL_IDLE_RX_UNIT 0
364
365
366#define IXGB_FCRTL_XONE 0x80000000
367
368
369#define IXGB_RXDCTL_PTHRESH_MASK 0x000001FF
370#define IXGB_RXDCTL_PTHRESH_SHIFT 0
371#define IXGB_RXDCTL_HTHRESH_MASK 0x0003FE00
372#define IXGB_RXDCTL_HTHRESH_SHIFT 9
373#define IXGB_RXDCTL_WTHRESH_MASK 0x07FC0000
374#define IXGB_RXDCTL_WTHRESH_SHIFT 18
375
376
377#define IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F
378#define IXGB_RAIDC_DELAY_MASK 0x000FF800
379#define IXGB_RAIDC_DELAY_SHIFT 11
380#define IXGB_RAIDC_POLL_MASK 0x1FF00000
381#define IXGB_RAIDC_POLL_SHIFT 20
382#define IXGB_RAIDC_RXT_GATE 0x40000000
383#define IXGB_RAIDC_EN 0x80000000
384
385#define IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND 1220
386#define IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND 244
387#define IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND 122
388#define IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND 61
389
390
391#define IXGB_RXCSUM_IPOFL 0x00000100
392#define IXGB_RXCSUM_TUOFL 0x00000200
393
394
395#define IXGB_RAH_ASEL_MASK 0x00030000
396#define IXGB_RAH_ASEL_DEST 0x00000000
397#define IXGB_RAH_ASEL_SRC 0x00010000
398#define IXGB_RAH_AV 0x80000000
399
400
401#define IXGB_TCTL_TCE 0x00000001
402#define IXGB_TCTL_TXEN 0x00000002
403#define IXGB_TCTL_TPDE 0x00000004
404
405#define IXGB_TCTL_IDLE_TX_UNIT 0
406
407
408#define IXGB_TXDCTL_PTHRESH_MASK 0x0000007F
409#define IXGB_TXDCTL_HTHRESH_MASK 0x00007F00
410#define IXGB_TXDCTL_HTHRESH_SHIFT 8
411#define IXGB_TXDCTL_WTHRESH_MASK 0x007F0000
412#define IXGB_TXDCTL_WTHRESH_SHIFT 16
413
414
415#define IXGB_TSPMT_TSMT_MASK 0x0000FFFF
416#define IXGB_TSPMT_TSPBP_MASK 0xFFFF0000
417#define IXGB_TSPMT_TSPBP_SHIFT 16
418
419
420#define IXGB_PAP_TXPC_MASK 0x0000FFFF
421#define IXGB_PAP_TXPV_MASK 0x000F0000
422#define IXGB_PAP_TXPV_10G 0x00000000
423#define IXGB_PAP_TXPV_1G 0x00010000
424#define IXGB_PAP_TXPV_2G 0x00020000
425#define IXGB_PAP_TXPV_3G 0x00030000
426#define IXGB_PAP_TXPV_4G 0x00040000
427#define IXGB_PAP_TXPV_5G 0x00050000
428#define IXGB_PAP_TXPV_6G 0x00060000
429#define IXGB_PAP_TXPV_7G 0x00070000
430#define IXGB_PAP_TXPV_8G 0x00080000
431#define IXGB_PAP_TXPV_9G 0x00090000
432#define IXGB_PAP_TXPV_WAN 0x000F0000
433
434
435#define IXGB_PCSC1_LOOPBACK 0x00004000
436
437
438#define IXGB_PCSC2_PCS_TYPE_MASK 0x00000003
439#define IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001
440
441
442#define IXGB_PCSS1_LOCAL_FAULT 0x00000080
443#define IXGB_PCSS1_RX_LINK_STATUS 0x00000004
444
445
446#define IXGB_PCSS2_DEV_PRES_MASK 0x0000C000
447#define IXGB_PCSS2_DEV_PRES 0x00004000
448#define IXGB_PCSS2_TX_LF 0x00000800
449#define IXGB_PCSS2_RX_LF 0x00000400
450#define IXGB_PCSS2_10GBW 0x00000004
451#define IXGB_PCSS2_10GBX 0x00000002
452#define IXGB_PCSS2_10GBR 0x00000001
453
454
455#define IXGB_XPCSS_ALIGN_STATUS 0x00001000
456#define IXGB_XPCSS_PATTERN_TEST 0x00000800
457#define IXGB_XPCSS_LANE_3_SYNC 0x00000008
458#define IXGB_XPCSS_LANE_2_SYNC 0x00000004
459#define IXGB_XPCSS_LANE_1_SYNC 0x00000002
460#define IXGB_XPCSS_LANE_0_SYNC 0x00000001
461
462
463#define IXGB_XPCSTC_BERT_TRIG 0x00200000
464#define IXGB_XPCSTC_BERT_SST 0x00100000
465#define IXGB_XPCSTC_BERT_PSZ_MASK 0x000C0000
466#define IXGB_XPCSTC_BERT_PSZ_SHIFT 17
467#define IXGB_XPCSTC_BERT_PSZ_INF 0x00000003
468#define IXGB_XPCSTC_BERT_PSZ_68 0x00000001
469#define IXGB_XPCSTC_BERT_PSZ_1028 0x00000000
470
471
472
473#define IXGB_MSCA_NP_ADDR_MASK 0x0000FFFF
474#define IXGB_MSCA_NP_ADDR_SHIFT 0
475
476#define IXGB_MSCA_DEV_TYPE_MASK 0x001F0000
477#define IXGB_MSCA_DEV_TYPE_SHIFT 16
478#define IXGB_MSCA_PHY_ADDR_MASK 0x03E00000
479#define IXGB_MSCA_PHY_ADDR_SHIFT 21
480#define IXGB_MSCA_OP_CODE_MASK 0x0C000000
481
482
483
484
485#define IXGB_MSCA_ADDR_CYCLE 0x00000000
486#define IXGB_MSCA_WRITE 0x04000000
487#define IXGB_MSCA_READ 0x08000000
488#define IXGB_MSCA_READ_AUTOINC 0x0C000000
489#define IXGB_MSCA_OP_CODE_SHIFT 26
490#define IXGB_MSCA_ST_CODE_MASK 0x30000000
491
492
493#define IXGB_MSCA_NEW_PROTOCOL 0x00000000
494#define IXGB_MSCA_OLD_PROTOCOL 0x10000000
495#define IXGB_MSCA_ST_CODE_SHIFT 28
496
497#define IXGB_MSCA_MDI_COMMAND 0x40000000
498
499#define IXGB_MSCA_MDI_IN_PROG_EN 0x80000000
500
501
502#define IXGB_MSRWD_WRITE_DATA_MASK 0x0000FFFF
503#define IXGB_MSRWD_WRITE_DATA_SHIFT 0
504#define IXGB_MSRWD_READ_DATA_MASK 0xFFFF0000
505#define IXGB_MSRWD_READ_DATA_SHIFT 16
506
507
508#define IXGB_PHY_ADDRESS 0x0
509
510#define MDIO_PMA_PMD_XPAK_VENDOR_NAME 0x803A
511
512
513#define G6XXX_PMA_PMD_VS1 0xC001
514#define G6XXX_XGXS_XAUI_VS2 0x18
515
516#define G6XXX_PMA_PMD_VS1_PLL_RESET 0x80
517#define G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET 0x00
518#define G6XXX_XGXS_XAUI_VS2_INPUT_MASK 0x0F
519
520
521
522
523
524
525struct ixgb_rx_desc {
526 __le64 buff_addr;
527 __le16 length;
528 __le16 reserved;
529 u8 status;
530 u8 errors;
531 __le16 special;
532};
533
534#define IXGB_RX_DESC_STATUS_DD 0x01
535#define IXGB_RX_DESC_STATUS_EOP 0x02
536#define IXGB_RX_DESC_STATUS_IXSM 0x04
537#define IXGB_RX_DESC_STATUS_VP 0x08
538#define IXGB_RX_DESC_STATUS_TCPCS 0x20
539#define IXGB_RX_DESC_STATUS_IPCS 0x40
540#define IXGB_RX_DESC_STATUS_PIF 0x80
541
542#define IXGB_RX_DESC_ERRORS_CE 0x01
543#define IXGB_RX_DESC_ERRORS_SE 0x02
544#define IXGB_RX_DESC_ERRORS_P 0x08
545#define IXGB_RX_DESC_ERRORS_TCPE 0x20
546#define IXGB_RX_DESC_ERRORS_IPE 0x40
547#define IXGB_RX_DESC_ERRORS_RXE 0x80
548
549#define IXGB_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF
550#define IXGB_RX_DESC_SPECIAL_PRI_MASK 0xE000
551#define IXGB_RX_DESC_SPECIAL_PRI_SHIFT 0x000D
552
553
554
555
556
557
558struct ixgb_tx_desc {
559 __le64 buff_addr;
560 __le32 cmd_type_len;
561 u8 status;
562 u8 popts;
563 __le16 vlan;
564};
565
566#define IXGB_TX_DESC_LENGTH_MASK 0x000FFFFF
567#define IXGB_TX_DESC_TYPE_MASK 0x00F00000
568#define IXGB_TX_DESC_TYPE_SHIFT 20
569#define IXGB_TX_DESC_CMD_MASK 0xFF000000
570#define IXGB_TX_DESC_CMD_SHIFT 24
571#define IXGB_TX_DESC_CMD_EOP 0x01000000
572#define IXGB_TX_DESC_CMD_TSE 0x04000000
573#define IXGB_TX_DESC_CMD_RS 0x08000000
574#define IXGB_TX_DESC_CMD_VLE 0x40000000
575#define IXGB_TX_DESC_CMD_IDE 0x80000000
576
577#define IXGB_TX_DESC_TYPE 0x00100000
578
579#define IXGB_TX_DESC_STATUS_DD 0x01
580
581#define IXGB_TX_DESC_POPTS_IXSM 0x01
582#define IXGB_TX_DESC_POPTS_TXSM 0x02
583#define IXGB_TX_DESC_SPECIAL_PRI_SHIFT IXGB_RX_DESC_SPECIAL_PRI_SHIFT
584
585struct ixgb_context_desc {
586 u8 ipcss;
587 u8 ipcso;
588 __le16 ipcse;
589 u8 tucss;
590 u8 tucso;
591 __le16 tucse;
592 __le32 cmd_type_len;
593 u8 status;
594 u8 hdr_len;
595 __le16 mss;
596};
597
598#define IXGB_CONTEXT_DESC_CMD_TCP 0x01000000
599#define IXGB_CONTEXT_DESC_CMD_IP 0x02000000
600#define IXGB_CONTEXT_DESC_CMD_TSE 0x04000000
601#define IXGB_CONTEXT_DESC_CMD_RS 0x08000000
602#define IXGB_CONTEXT_DESC_CMD_IDE 0x80000000
603
604#define IXGB_CONTEXT_DESC_TYPE 0x00000000
605
606#define IXGB_CONTEXT_DESC_STATUS_DD 0x01
607
608
609#define IXGB_MC_TBL_SIZE 128
610#define IXGB_VLAN_FILTER_TBL_SIZE 128
611#define IXGB_RAR_ENTRIES 3
612
613#define IXGB_MEMORY_REGISTER_BASE_ADDRESS 0
614#define ENET_HEADER_SIZE 14
615#define ENET_FCS_LENGTH 4
616#define IXGB_MAX_NUM_MULTICAST_ADDRESSES 128
617#define IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS 60
618#define IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS 1514
619#define IXGB_MAX_JUMBO_FRAME_SIZE 0x3F00
620
621
622#define IXGB_OPTICAL_PHY_ADDR 0x0
623#define IXGB_XAUII_PHY_ADDR 0x1
624#define IXGB_DIAG_PHY_ADDR 0x1F
625
626
627struct ixgb_flash_buffer {
628 u8 manufacturer_id;
629 u8 device_id;
630 u8 filler1[0x2AA8];
631 u8 cmd2;
632 u8 filler2[0x2AAA];
633 u8 cmd1;
634 u8 filler3[0xAAAA];
635};
636
637
638struct ixgb_fc {
639 u32 high_water;
640 u32 low_water;
641 u16 pause_time;
642 bool send_xon;
643 ixgb_fc_type type;
644};
645
646
647#define FC_DEFAULT_HI_THRESH (0x8000)
648#define FC_DEFAULT_LO_THRESH (0x4000)
649#define FC_DEFAULT_TX_TIMER (0x100)
650
651
652#define IXGB_MAX_PHY_REG_ADDRESS 0xFFFF
653#define IXGB_MAX_PHY_ADDRESS 31
654#define IXGB_MAX_PHY_DEV_TYPE 31
655
656
657struct ixgb_bus {
658 ixgb_bus_speed speed;
659 ixgb_bus_width width;
660 ixgb_bus_type type;
661};
662
663struct ixgb_hw {
664 u8 __iomem *hw_addr;
665 void *back;
666 struct ixgb_fc fc;
667 struct ixgb_bus bus;
668 u32 phy_id;
669 u32 phy_addr;
670 ixgb_mac_type mac_type;
671 ixgb_phy_type phy_type;
672 u32 max_frame_size;
673 u32 mc_filter_type;
674 u32 num_mc_addrs;
675 u8 curr_mac_addr[ETH_ALEN];
676 u32 num_tx_desc;
677 u32 num_rx_desc;
678 u32 rx_buffer_size;
679 bool link_up;
680 bool adapter_stopped;
681 u16 device_id;
682 u16 vendor_id;
683 u8 revision_id;
684 u16 subsystem_vendor_id;
685 u16 subsystem_id;
686 u32 bar0;
687 u32 bar1;
688 u32 bar2;
689 u32 bar3;
690 u16 pci_cmd_word;
691 __le16 eeprom[IXGB_EEPROM_SIZE];
692 unsigned long io_base;
693 u32 lastLFC;
694 u32 lastRFC;
695};
696
697
698struct ixgb_hw_stats {
699 u64 tprl;
700 u64 tprh;
701 u64 gprcl;
702 u64 gprch;
703 u64 bprcl;
704 u64 bprch;
705 u64 mprcl;
706 u64 mprch;
707 u64 uprcl;
708 u64 uprch;
709 u64 vprcl;
710 u64 vprch;
711 u64 jprcl;
712 u64 jprch;
713 u64 gorcl;
714 u64 gorch;
715 u64 torl;
716 u64 torh;
717 u64 rnbc;
718 u64 ruc;
719 u64 roc;
720 u64 rlec;
721 u64 crcerrs;
722 u64 icbc;
723 u64 ecbc;
724 u64 mpc;
725 u64 tptl;
726 u64 tpth;
727 u64 gptcl;
728 u64 gptch;
729 u64 bptcl;
730 u64 bptch;
731 u64 mptcl;
732 u64 mptch;
733 u64 uptcl;
734 u64 uptch;
735 u64 vptcl;
736 u64 vptch;
737 u64 jptcl;
738 u64 jptch;
739 u64 gotcl;
740 u64 gotch;
741 u64 totl;
742 u64 toth;
743 u64 dc;
744 u64 plt64c;
745 u64 tsctc;
746 u64 tsctfc;
747 u64 ibic;
748 u64 rfc;
749 u64 lfc;
750 u64 pfrc;
751 u64 pftc;
752 u64 mcfrc;
753 u64 mcftc;
754 u64 xonrxc;
755 u64 xontxc;
756 u64 xoffrxc;
757 u64 xofftxc;
758 u64 rjc;
759};
760
761
762bool ixgb_adapter_stop(struct ixgb_hw *hw);
763bool ixgb_init_hw(struct ixgb_hw *hw);
764bool ixgb_adapter_start(struct ixgb_hw *hw);
765void ixgb_check_for_link(struct ixgb_hw *hw);
766bool ixgb_check_for_bad_link(struct ixgb_hw *hw);
767
768void ixgb_rar_set(struct ixgb_hw *hw, u8 *addr, u32 index);
769
770
771void ixgb_mc_addr_list_update(struct ixgb_hw *hw, u8 *mc_addr_list,
772 u32 mc_addr_count, u32 pad);
773
774
775void ixgb_write_vfta(struct ixgb_hw *hw, u32 offset, u32 value);
776
777
778void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, u8 *mac_addr);
779u32 ixgb_get_ee_pba_number(struct ixgb_hw *hw);
780u16 ixgb_get_ee_device_id(struct ixgb_hw *hw);
781bool ixgb_get_eeprom_data(struct ixgb_hw *hw);
782__le16 ixgb_get_eeprom_word(struct ixgb_hw *hw, u16 index);
783
784
785void ixgb_led_on(struct ixgb_hw *hw);
786void ixgb_led_off(struct ixgb_hw *hw);
787void ixgb_write_pci_cfg(struct ixgb_hw *hw,
788 u32 reg,
789 u16 * value);
790
791
792#endif
793