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33#include <linux/prefetch.h>
34#include <linux/ip.h>
35#include <linux/ipv6.h>
36#include <linux/tcp.h>
37#include <linux/bpf_trace.h>
38#include <net/busy_poll.h>
39#include "en.h"
40#include "en_tc.h"
41#include "eswitch.h"
42#include "en_rep.h"
43#include "ipoib/ipoib.h"
44#include "en_accel/ipsec_rxtx.h"
45
46static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp)
47{
48 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
49}
50
51static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
52 void *data)
53{
54 u32 ci = cqcc & cq->wq.sz_m1;
55
56 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
57}
58
59static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
60 struct mlx5e_cq *cq, u32 cqcc)
61{
62 mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
63 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt);
64 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
65 rq->stats.cqe_compress_blks++;
66}
67
68static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
69{
70 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
71 cq->mini_arr_idx = 0;
72}
73
74static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
75{
76 u8 op_own = (cqcc >> cq->wq.log_sz) & 1;
77 u32 wq_sz = 1 << cq->wq.log_sz;
78 u32 ci = cqcc & cq->wq.sz_m1;
79 u32 ci_top = min_t(u32, wq_sz, ci + n);
80
81 for (; ci < ci_top; ci++, n--) {
82 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
83
84 cqe->op_own = op_own;
85 }
86
87 if (unlikely(ci == wq_sz)) {
88 op_own = !op_own;
89 for (ci = 0; ci < n; ci++) {
90 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
91
92 cqe->op_own = op_own;
93 }
94 }
95}
96
97static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
98 struct mlx5e_cq *cq, u32 cqcc)
99{
100 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
101 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum;
102 cq->title.op_own &= 0xf0;
103 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz);
104 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter);
105
106 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
107 cq->decmprs_wqe_counter +=
108 mpwrq_get_cqe_consumed_strides(&cq->title);
109 else
110 cq->decmprs_wqe_counter =
111 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1;
112}
113
114static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
115 struct mlx5e_cq *cq, u32 cqcc)
116{
117 mlx5e_decompress_cqe(rq, cq, cqcc);
118 cq->title.rss_hash_type = 0;
119 cq->title.rss_hash_result = 0;
120}
121
122static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
123 struct mlx5e_cq *cq,
124 int update_owner_only,
125 int budget_rem)
126{
127 u32 cqcc = cq->wq.cc + update_owner_only;
128 u32 cqe_count;
129 u32 i;
130
131 cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
132
133 for (i = update_owner_only; i < cqe_count;
134 i++, cq->mini_arr_idx++, cqcc++) {
135 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
136 mlx5e_read_mini_arr_slot(cq, cqcc);
137
138 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
139 rq->handle_rx_cqe(rq, &cq->title);
140 }
141 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
142 cq->wq.cc = cqcc;
143 cq->decmprs_left -= cqe_count;
144 rq->stats.cqe_compress_pkts += cqe_count;
145
146 return cqe_count;
147}
148
149static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
150 struct mlx5e_cq *cq,
151 int budget_rem)
152{
153 mlx5e_read_title_slot(rq, cq, cq->wq.cc);
154 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
155 mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
156 rq->handle_rx_cqe(rq, &cq->title);
157 cq->mini_arr_idx++;
158
159 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
160}
161
162#define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
163
164static inline bool mlx5e_page_is_reserved(struct page *page)
165{
166 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
167}
168
169static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
170 struct mlx5e_dma_info *dma_info)
171{
172 struct mlx5e_page_cache *cache = &rq->page_cache;
173 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
174
175 if (tail_next == cache->head) {
176 rq->stats.cache_full++;
177 return false;
178 }
179
180 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
181 rq->stats.cache_waive++;
182 return false;
183 }
184
185 cache->page_cache[cache->tail] = *dma_info;
186 cache->tail = tail_next;
187 return true;
188}
189
190static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
191 struct mlx5e_dma_info *dma_info)
192{
193 struct mlx5e_page_cache *cache = &rq->page_cache;
194
195 if (unlikely(cache->head == cache->tail)) {
196 rq->stats.cache_empty++;
197 return false;
198 }
199
200 if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
201 rq->stats.cache_busy++;
202 return false;
203 }
204
205 *dma_info = cache->page_cache[cache->head];
206 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
207 rq->stats.cache_reuse++;
208
209 dma_sync_single_for_device(rq->pdev, dma_info->addr,
210 RQ_PAGE_SIZE(rq),
211 DMA_FROM_DEVICE);
212 return true;
213}
214
215static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
216 struct mlx5e_dma_info *dma_info)
217{
218 if (mlx5e_rx_cache_get(rq, dma_info))
219 return 0;
220
221 dma_info->page = dev_alloc_pages(rq->buff.page_order);
222 if (unlikely(!dma_info->page))
223 return -ENOMEM;
224
225 dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
226 RQ_PAGE_SIZE(rq), rq->buff.map_dir);
227 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
228 put_page(dma_info->page);
229 dma_info->page = NULL;
230 return -ENOMEM;
231 }
232
233 return 0;
234}
235
236void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
237 bool recycle)
238{
239 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info))
240 return;
241
242 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
243 rq->buff.map_dir);
244 put_page(dma_info->page);
245}
246
247static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq,
248 struct mlx5e_wqe_frag_info *wi)
249{
250 return rq->wqe.page_reuse && wi->di.page &&
251 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) &&
252 !mlx5e_page_is_reserved(wi->di.page);
253}
254
255static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
256{
257 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
258
259
260 if (!wi->di.page) {
261 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di)))
262 return -ENOMEM;
263 wi->offset = 0;
264 }
265
266 wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom);
267 return 0;
268}
269
270static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
271 struct mlx5e_wqe_frag_info *wi)
272{
273 mlx5e_page_release(rq, &wi->di, true);
274 wi->di.page = NULL;
275}
276
277static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq,
278 struct mlx5e_wqe_frag_info *wi)
279{
280 if (mlx5e_page_reuse(rq, wi)) {
281 rq->stats.page_reuse++;
282 return;
283 }
284
285 mlx5e_free_rx_wqe(rq, wi);
286}
287
288void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
289{
290 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
291
292 if (wi->di.page)
293 mlx5e_free_rx_wqe(rq, wi);
294}
295
296static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
297{
298 return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
299}
300
301static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
302 struct sk_buff *skb,
303 struct mlx5e_mpw_info *wi,
304 u32 page_idx, u32 frag_offset,
305 u32 len)
306{
307 unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz));
308
309 dma_sync_single_for_cpu(rq->pdev,
310 wi->umr.dma_info[page_idx].addr + frag_offset,
311 len, DMA_FROM_DEVICE);
312 wi->skbs_frags[page_idx]++;
313 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
314 wi->umr.dma_info[page_idx].page, frag_offset,
315 len, truesize);
316}
317
318static inline void
319mlx5e_copy_skb_header_mpwqe(struct device *pdev,
320 struct sk_buff *skb,
321 struct mlx5e_mpw_info *wi,
322 u32 page_idx, u32 offset,
323 u32 headlen)
324{
325 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
326 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
327 unsigned int len;
328
329
330 len = ALIGN(headlen_pg, sizeof(long));
331 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
332 DMA_FROM_DEVICE);
333 skb_copy_to_linear_data_offset(skb, 0,
334 page_address(dma_info->page) + offset,
335 len);
336 if (unlikely(offset + headlen > PAGE_SIZE)) {
337 dma_info++;
338 headlen_pg = len;
339 len = ALIGN(headlen - headlen_pg, sizeof(long));
340 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
341 DMA_FROM_DEVICE);
342 skb_copy_to_linear_data_offset(skb, headlen_pg,
343 page_address(dma_info->page),
344 len);
345 }
346}
347
348static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
349{
350 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
351 struct mlx5e_icosq *sq = &rq->channel->icosq;
352 struct mlx5_wq_cyc *wq = &sq->wq;
353 struct mlx5e_umr_wqe *wqe;
354 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
355 u16 pi;
356
357
358 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
359 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
360 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
361 }
362
363 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
364 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe));
365 wqe->ctrl.opmod_idx_opcode =
366 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
367 MLX5_OPCODE_UMR);
368
369 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
370 sq->pc += num_wqebbs;
371 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl);
372}
373
374static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq,
375 u16 ix)
376{
377 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
378 int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
379 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
380 int err;
381 int i;
382
383 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
384 err = mlx5e_page_alloc_mapped(rq, dma_info);
385 if (unlikely(err))
386 goto err_unmap;
387 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
388 page_ref_add(dma_info->page, pg_strides);
389 }
390
391 memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE);
392 wi->consumed_strides = 0;
393
394 return 0;
395
396err_unmap:
397 while (--i >= 0) {
398 dma_info--;
399 page_ref_sub(dma_info->page, pg_strides);
400 mlx5e_page_release(rq, dma_info, true);
401 }
402
403 return err;
404}
405
406void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
407{
408 int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
409 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
410 int i;
411
412 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
413 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]);
414 mlx5e_page_release(rq, dma_info, true);
415 }
416}
417
418static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
419{
420 struct mlx5_wq_ll *wq = &rq->wq;
421 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
422
423 rq->mpwqe.umr_in_progress = false;
424
425 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
426
427
428 dma_wmb();
429
430 mlx5_wq_ll_update_db_record(wq);
431}
432
433static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
434{
435 int err;
436
437 err = mlx5e_alloc_rx_umr_mpwqe(rq, ix);
438 if (unlikely(err)) {
439 rq->stats.buff_alloc_err++;
440 return err;
441 }
442 rq->mpwqe.umr_in_progress = true;
443 mlx5e_post_umr_wqe(rq, ix);
444 return 0;
445}
446
447void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
448{
449 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
450
451 mlx5e_free_rx_mpwqe(rq, wi);
452}
453
454bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
455{
456 struct mlx5_wq_ll *wq = &rq->wq;
457 int err;
458
459 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
460 return false;
461
462 if (mlx5_wq_ll_is_full(wq))
463 return false;
464
465 do {
466 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
467
468 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head);
469 if (unlikely(err)) {
470 rq->stats.buff_alloc_err++;
471 break;
472 }
473
474 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
475 } while (!mlx5_wq_ll_is_full(wq));
476
477
478 dma_wmb();
479
480 mlx5_wq_ll_update_db_record(wq);
481
482 return !!err;
483}
484
485static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
486 struct mlx5e_icosq *sq,
487 struct mlx5e_rq *rq,
488 struct mlx5_cqe64 *cqe)
489{
490 struct mlx5_wq_cyc *wq = &sq->wq;
491 u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1;
492 struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
493
494 mlx5_cqwq_pop(&cq->wq);
495
496 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
497 WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n",
498 cqe->op_own);
499 return;
500 }
501
502 if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
503 mlx5e_post_rx_mpwqe(rq);
504 return;
505 }
506
507 if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
508 WARN_ONCE(true,
509 "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n",
510 icowi->opcode);
511}
512
513static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
514{
515 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
516 struct mlx5_cqe64 *cqe;
517
518 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
519 return;
520
521 cqe = mlx5_cqwq_get_cqe(&cq->wq);
522 if (likely(!cqe))
523 return;
524
525
526 mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
527
528 mlx5_cqwq_update_db_record(&cq->wq);
529}
530
531bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
532{
533 struct mlx5_wq_ll *wq = &rq->wq;
534
535 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
536 return false;
537
538 mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
539
540 if (mlx5_wq_ll_is_full(wq))
541 return false;
542
543 if (!rq->mpwqe.umr_in_progress)
544 mlx5e_alloc_rx_mpwqe(rq, wq->head);
545
546 return true;
547}
548
549static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
550 u32 cqe_bcnt)
551{
552 struct ethhdr *eth = (struct ethhdr *)(skb->data);
553 struct tcphdr *tcp;
554 int network_depth = 0;
555 __be16 proto;
556 u16 tot_len;
557 void *ip_p;
558
559 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
560 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
561 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
562
563 skb->mac_len = ETH_HLEN;
564 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
565
566 tot_len = cqe_bcnt - network_depth;
567 ip_p = skb->data + network_depth;
568
569 if (proto == htons(ETH_P_IP)) {
570 struct iphdr *ipv4 = ip_p;
571
572 tcp = ip_p + sizeof(struct iphdr);
573 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
574
575 ipv4->ttl = cqe->lro_min_ttl;
576 ipv4->tot_len = cpu_to_be16(tot_len);
577 ipv4->check = 0;
578 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
579 ipv4->ihl);
580 } else {
581 struct ipv6hdr *ipv6 = ip_p;
582
583 tcp = ip_p + sizeof(struct ipv6hdr);
584 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
585
586 ipv6->hop_limit = cqe->lro_min_ttl;
587 ipv6->payload_len = cpu_to_be16(tot_len -
588 sizeof(struct ipv6hdr));
589 }
590
591 tcp->psh = get_cqe_lro_tcppsh(cqe);
592
593 if (tcp_ack) {
594 tcp->ack = 1;
595 tcp->ack_seq = cqe->lro_ack_seq_num;
596 tcp->window = cqe->lro_tcp_win;
597 }
598}
599
600static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
601 struct sk_buff *skb)
602{
603 u8 cht = cqe->rss_hash_type;
604 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
605 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
606 PKT_HASH_TYPE_NONE;
607 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
608}
609
610static inline bool is_first_ethertype_ip(struct sk_buff *skb)
611{
612 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
613
614 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
615}
616
617static inline void mlx5e_handle_csum(struct net_device *netdev,
618 struct mlx5_cqe64 *cqe,
619 struct mlx5e_rq *rq,
620 struct sk_buff *skb,
621 bool lro)
622{
623 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
624 goto csum_none;
625
626 if (lro) {
627 skb->ip_summed = CHECKSUM_UNNECESSARY;
628 rq->stats.csum_unnecessary++;
629 return;
630 }
631
632 if (is_first_ethertype_ip(skb)) {
633 skb->ip_summed = CHECKSUM_COMPLETE;
634 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
635 rq->stats.csum_complete++;
636 return;
637 }
638
639 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
640 (cqe->hds_ip_ext & CQE_L4_OK))) {
641 skb->ip_summed = CHECKSUM_UNNECESSARY;
642 if (cqe_is_tunneled(cqe)) {
643 skb->csum_level = 1;
644 skb->encapsulation = 1;
645 rq->stats.csum_unnecessary_inner++;
646 return;
647 }
648 rq->stats.csum_unnecessary++;
649 return;
650 }
651csum_none:
652 skb->ip_summed = CHECKSUM_NONE;
653 rq->stats.csum_none++;
654}
655
656static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
657 u32 cqe_bcnt,
658 struct mlx5e_rq *rq,
659 struct sk_buff *skb)
660{
661 struct net_device *netdev = rq->netdev;
662 struct mlx5e_tstamp *tstamp = rq->tstamp;
663 int lro_num_seg;
664
665 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
666 if (lro_num_seg > 1) {
667 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
668 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
669
670
671
672 rq->stats.packets += lro_num_seg - 1;
673 rq->stats.lro_packets++;
674 rq->stats.lro_bytes += cqe_bcnt;
675 }
676
677 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
678 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
679
680 skb_record_rx_queue(skb, rq->ix);
681
682 if (likely(netdev->features & NETIF_F_RXHASH))
683 mlx5e_skb_set_hash(cqe, skb);
684
685 if (cqe_has_vlan(cqe))
686 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
687 be16_to_cpu(cqe->vlan_info));
688
689 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
690
691 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
692 skb->protocol = eth_type_trans(skb, netdev);
693}
694
695static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
696 struct mlx5_cqe64 *cqe,
697 u32 cqe_bcnt,
698 struct sk_buff *skb)
699{
700 rq->stats.packets++;
701 rq->stats.bytes += cqe_bcnt;
702 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
703}
704
705static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
706{
707 struct mlx5_wq_cyc *wq = &sq->wq;
708 struct mlx5e_tx_wqe *wqe;
709 u16 pi = (sq->pc - 1) & wq->sz_m1;
710
711 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
712
713 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
714}
715
716static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
717 struct mlx5e_dma_info *di,
718 const struct xdp_buff *xdp)
719{
720 struct mlx5e_xdpsq *sq = &rq->xdpsq;
721 struct mlx5_wq_cyc *wq = &sq->wq;
722 u16 pi = sq->pc & wq->sz_m1;
723 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
724
725 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
726 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
727 struct mlx5_wqe_data_seg *dseg;
728
729 ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
730 dma_addr_t dma_addr = di->addr + data_offset;
731 unsigned int dma_len = xdp->data_end - xdp->data;
732
733 prefetchw(wqe);
734
735 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE ||
736 MLX5E_SW2HW_MTU(rq->channel->priv, rq->netdev->mtu) < dma_len)) {
737 rq->stats.xdp_drop++;
738 return false;
739 }
740
741 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
742 if (sq->db.doorbell) {
743
744 mlx5e_xmit_xdp_doorbell(sq);
745 sq->db.doorbell = false;
746 }
747 rq->stats.xdp_tx_full++;
748 return false;
749 }
750
751 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
752
753 cseg->fm_ce_se = 0;
754
755 dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
756
757
758 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
759 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
760 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
761 dma_len -= MLX5E_XDP_MIN_INLINE;
762 dma_addr += MLX5E_XDP_MIN_INLINE;
763 dseg++;
764 }
765
766
767 dseg->addr = cpu_to_be64(dma_addr);
768 dseg->byte_count = cpu_to_be32(dma_len);
769
770 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
771
772
773
774
775 rq->wqe.xdp_xmit = true;
776 sq->db.di[pi] = *di;
777 sq->pc++;
778
779 sq->db.doorbell = true;
780
781 rq->stats.xdp_tx++;
782 return true;
783}
784
785
786static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq,
787 struct mlx5e_dma_info *di,
788 void *va, u16 *rx_headroom, u32 *len)
789{
790 const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
791 struct xdp_buff xdp;
792 u32 act;
793
794 if (!prog)
795 return false;
796
797 xdp.data = va + *rx_headroom;
798 xdp.data_end = xdp.data + *len;
799 xdp.data_hard_start = va;
800
801 act = bpf_prog_run_xdp(prog, &xdp);
802 switch (act) {
803 case XDP_PASS:
804 *rx_headroom = xdp.data - xdp.data_hard_start;
805 *len = xdp.data_end - xdp.data;
806 return false;
807 case XDP_TX:
808 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
809 trace_xdp_exception(rq->netdev, prog, act);
810 return true;
811 default:
812 bpf_warn_invalid_xdp_action(act);
813 case XDP_ABORTED:
814 trace_xdp_exception(rq->netdev, prog, act);
815 case XDP_DROP:
816 rq->stats.xdp_drop++;
817 return true;
818 }
819}
820
821static inline
822struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
823 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
824{
825 struct mlx5e_dma_info *di = &wi->di;
826 u16 rx_headroom = rq->buff.headroom;
827 struct sk_buff *skb;
828 void *va, *data;
829 bool consumed;
830 u32 frag_size;
831
832 va = page_address(di->page) + wi->offset;
833 data = va + rx_headroom;
834 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
835
836 dma_sync_single_range_for_cpu(rq->pdev,
837 di->addr + wi->offset,
838 0, frag_size,
839 DMA_FROM_DEVICE);
840 prefetch(data);
841 wi->offset += frag_size;
842
843 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
844 rq->stats.wqe_err++;
845 return NULL;
846 }
847
848 rcu_read_lock();
849 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
850 rcu_read_unlock();
851 if (consumed)
852 return NULL;
853
854 skb = build_skb(va, frag_size);
855 if (unlikely(!skb)) {
856 rq->stats.buff_alloc_err++;
857 return NULL;
858 }
859
860
861 page_ref_inc(di->page);
862
863 skb_reserve(skb, rx_headroom);
864 skb_put(skb, cqe_bcnt);
865
866 return skb;
867}
868
869void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
870{
871 struct mlx5e_wqe_frag_info *wi;
872 struct mlx5e_rx_wqe *wqe;
873 __be16 wqe_counter_be;
874 struct sk_buff *skb;
875 u16 wqe_counter;
876 u32 cqe_bcnt;
877
878 wqe_counter_be = cqe->wqe_counter;
879 wqe_counter = be16_to_cpu(wqe_counter_be);
880 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
881 wi = &rq->wqe.frag_info[wqe_counter];
882 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
883
884 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
885 if (!skb) {
886
887 if (rq->wqe.xdp_xmit) {
888 wi->di.page = NULL;
889 rq->wqe.xdp_xmit = false;
890
891 goto wq_ll_pop;
892 }
893
894 mlx5e_free_rx_wqe(rq, wi);
895 goto wq_ll_pop;
896 }
897
898 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
899 napi_gro_receive(rq->cq.napi, skb);
900
901 mlx5e_free_rx_wqe_reuse(rq, wi);
902wq_ll_pop:
903 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
904 &wqe->next.next_wqe_index);
905}
906
907#ifdef CONFIG_MLX5_ESWITCH
908void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
909{
910 struct net_device *netdev = rq->netdev;
911 struct mlx5e_priv *priv = netdev_priv(netdev);
912 struct mlx5e_rep_priv *rpriv = priv->ppriv;
913 struct mlx5_eswitch_rep *rep = rpriv->rep;
914 struct mlx5e_wqe_frag_info *wi;
915 struct mlx5e_rx_wqe *wqe;
916 struct sk_buff *skb;
917 __be16 wqe_counter_be;
918 u16 wqe_counter;
919 u32 cqe_bcnt;
920
921 wqe_counter_be = cqe->wqe_counter;
922 wqe_counter = be16_to_cpu(wqe_counter_be);
923 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
924 wi = &rq->wqe.frag_info[wqe_counter];
925 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
926
927 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
928 if (!skb) {
929 if (rq->wqe.xdp_xmit) {
930 wi->di.page = NULL;
931 rq->wqe.xdp_xmit = false;
932
933 goto wq_ll_pop;
934 }
935
936 mlx5e_free_rx_wqe(rq, wi);
937 goto wq_ll_pop;
938 }
939
940 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
941
942 if (rep->vlan && skb_vlan_tag_present(skb))
943 skb_vlan_pop(skb);
944
945 napi_gro_receive(rq->cq.napi, skb);
946
947 mlx5e_free_rx_wqe_reuse(rq, wi);
948wq_ll_pop:
949 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
950 &wqe->next.next_wqe_index);
951}
952#endif
953
954static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
955 struct mlx5_cqe64 *cqe,
956 struct mlx5e_mpw_info *wi,
957 u32 cqe_bcnt,
958 struct sk_buff *skb)
959{
960 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
961 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz;
962 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
963 u32 page_idx = wqe_offset >> PAGE_SHIFT;
964 u32 head_page_idx = page_idx;
965 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
966 u32 frag_offset = head_offset + headlen;
967 u16 byte_cnt = cqe_bcnt - headlen;
968
969 if (unlikely(frag_offset >= PAGE_SIZE)) {
970 page_idx++;
971 frag_offset -= PAGE_SIZE;
972 }
973
974 while (byte_cnt) {
975 u32 pg_consumed_bytes =
976 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
977
978 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset,
979 pg_consumed_bytes);
980 byte_cnt -= pg_consumed_bytes;
981 frag_offset = 0;
982 page_idx++;
983 }
984
985 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx,
986 head_offset, headlen);
987
988 skb->tail += headlen;
989 skb->len += headlen;
990}
991
992void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
993{
994 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
995 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
996 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
997 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
998 struct sk_buff *skb;
999 u16 cqe_bcnt;
1000
1001 wi->consumed_strides += cstrides;
1002
1003 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1004 rq->stats.wqe_err++;
1005 goto mpwrq_cqe_out;
1006 }
1007
1008 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1009 rq->stats.mpwqe_filler++;
1010 goto mpwrq_cqe_out;
1011 }
1012
1013 skb = napi_alloc_skb(rq->cq.napi,
1014 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
1015 sizeof(long)));
1016 if (unlikely(!skb)) {
1017 rq->stats.buff_alloc_err++;
1018 goto mpwrq_cqe_out;
1019 }
1020
1021 prefetchw(skb->data);
1022 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1023
1024 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
1025 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1026 napi_gro_receive(rq->cq.napi, skb);
1027
1028mpwrq_cqe_out:
1029 if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1030 return;
1031
1032 mlx5e_free_rx_mpwqe(rq, wi);
1033 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1034}
1035
1036int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1037{
1038 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1039 struct mlx5e_xdpsq *xdpsq;
1040 struct mlx5_cqe64 *cqe;
1041 int work_done = 0;
1042
1043 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
1044 return 0;
1045
1046 if (cq->decmprs_left)
1047 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1048
1049 cqe = mlx5_cqwq_get_cqe(&cq->wq);
1050 if (!cqe)
1051 return 0;
1052
1053 xdpsq = &rq->xdpsq;
1054
1055 do {
1056 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1057 work_done +=
1058 mlx5e_decompress_cqes_start(rq, cq,
1059 budget - work_done);
1060 continue;
1061 }
1062
1063 mlx5_cqwq_pop(&cq->wq);
1064
1065 rq->handle_rx_cqe(rq, cqe);
1066 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1067
1068 if (xdpsq->db.doorbell) {
1069 mlx5e_xmit_xdp_doorbell(xdpsq);
1070 xdpsq->db.doorbell = false;
1071 }
1072
1073 mlx5_cqwq_update_db_record(&cq->wq);
1074
1075
1076 wmb();
1077
1078 return work_done;
1079}
1080
1081bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1082{
1083 struct mlx5e_xdpsq *sq;
1084 struct mlx5_cqe64 *cqe;
1085 struct mlx5e_rq *rq;
1086 u16 sqcc;
1087 int i;
1088
1089 sq = container_of(cq, struct mlx5e_xdpsq, cq);
1090
1091 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
1092 return false;
1093
1094 cqe = mlx5_cqwq_get_cqe(&cq->wq);
1095 if (!cqe)
1096 return false;
1097
1098 rq = container_of(sq, struct mlx5e_rq, xdpsq);
1099
1100
1101
1102
1103 sqcc = sq->cc;
1104
1105 i = 0;
1106 do {
1107 u16 wqe_counter;
1108 bool last_wqe;
1109
1110 mlx5_cqwq_pop(&cq->wq);
1111
1112 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1113
1114 do {
1115 struct mlx5e_dma_info *di;
1116 u16 ci;
1117
1118 last_wqe = (sqcc == wqe_counter);
1119
1120 ci = sqcc & sq->wq.sz_m1;
1121 di = &sq->db.di[ci];
1122
1123 sqcc++;
1124
1125 mlx5e_page_release(rq, di, true);
1126 } while (!last_wqe);
1127 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1128
1129 mlx5_cqwq_update_db_record(&cq->wq);
1130
1131
1132 wmb();
1133
1134 sq->cc = sqcc;
1135 return (i == MLX5E_TX_CQ_POLL_BUDGET);
1136}
1137
1138void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1139{
1140 struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1141 struct mlx5e_dma_info *di;
1142 u16 ci;
1143
1144 while (sq->cc != sq->pc) {
1145 ci = sq->cc & sq->wq.sz_m1;
1146 di = &sq->db.di[ci];
1147 sq->cc++;
1148
1149 mlx5e_page_release(rq, di, false);
1150 }
1151}
1152
1153#ifdef CONFIG_MLX5_CORE_IPOIB
1154
1155#define MLX5_IB_GRH_DGID_OFFSET 24
1156#define MLX5_GID_SIZE 16
1157
1158static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1159 struct mlx5_cqe64 *cqe,
1160 u32 cqe_bcnt,
1161 struct sk_buff *skb)
1162{
1163 struct net_device *netdev = rq->netdev;
1164 struct mlx5e_tstamp *tstamp = rq->tstamp;
1165 char *pseudo_header;
1166 u8 *dgid;
1167 u8 g;
1168
1169 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1170 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1171 if ((!g) || dgid[0] != 0xff)
1172 skb->pkt_type = PACKET_HOST;
1173 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1174 skb->pkt_type = PACKET_BROADCAST;
1175 else
1176 skb->pkt_type = PACKET_MULTICAST;
1177
1178
1179
1180
1181
1182 skb_pull(skb, MLX5_IB_GRH_BYTES);
1183
1184 skb->protocol = *((__be16 *)(skb->data));
1185
1186 skb->ip_summed = CHECKSUM_COMPLETE;
1187 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1188
1189 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1190 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
1191
1192 skb_record_rx_queue(skb, rq->ix);
1193
1194 if (likely(netdev->features & NETIF_F_RXHASH))
1195 mlx5e_skb_set_hash(cqe, skb);
1196
1197
1198 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1199 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1200 skb_reset_mac_header(skb);
1201 skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1202
1203 skb->dev = netdev;
1204
1205 rq->stats.csum_complete++;
1206 rq->stats.packets++;
1207 rq->stats.bytes += cqe_bcnt;
1208}
1209
1210void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1211{
1212 struct mlx5e_wqe_frag_info *wi;
1213 struct mlx5e_rx_wqe *wqe;
1214 __be16 wqe_counter_be;
1215 struct sk_buff *skb;
1216 u16 wqe_counter;
1217 u32 cqe_bcnt;
1218
1219 wqe_counter_be = cqe->wqe_counter;
1220 wqe_counter = be16_to_cpu(wqe_counter_be);
1221 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1222 wi = &rq->wqe.frag_info[wqe_counter];
1223 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1224
1225 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1226 if (!skb)
1227 goto wq_free_wqe;
1228
1229 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1230 napi_gro_receive(rq->cq.napi, skb);
1231
1232wq_free_wqe:
1233 mlx5e_free_rx_wqe_reuse(rq, wi);
1234 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1235 &wqe->next.next_wqe_index);
1236}
1237
1238#endif
1239
1240#ifdef CONFIG_MLX5_EN_IPSEC
1241
1242void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1243{
1244 struct mlx5e_wqe_frag_info *wi;
1245 struct mlx5e_rx_wqe *wqe;
1246 __be16 wqe_counter_be;
1247 struct sk_buff *skb;
1248 u16 wqe_counter;
1249 u32 cqe_bcnt;
1250
1251 wqe_counter_be = cqe->wqe_counter;
1252 wqe_counter = be16_to_cpu(wqe_counter_be);
1253 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1254 wi = &rq->wqe.frag_info[wqe_counter];
1255 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1256
1257 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1258 if (unlikely(!skb)) {
1259
1260 mlx5e_free_rx_wqe(rq, wi);
1261 goto wq_ll_pop;
1262 }
1263 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb);
1264 if (unlikely(!skb)) {
1265 mlx5e_free_rx_wqe(rq, wi);
1266 goto wq_ll_pop;
1267 }
1268
1269 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1270 napi_gro_receive(rq->cq.napi, skb);
1271
1272 mlx5e_free_rx_wqe_reuse(rq, wi);
1273wq_ll_pop:
1274 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1275 &wqe->next.next_wqe_index);
1276}
1277
1278#endif
1279
