linux/drivers/net/ethernet/nuvoton/w90p910_ether.c
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   1/*
   2 * Copyright (c) 2008-2009 Nuvoton technology corporation.
   3 *
   4 * Wan ZongShun <mcuos.com@gmail.com>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation;version 2 of the License.
   9 *
  10 */
  11
  12#include <linux/module.h>
  13#include <linux/init.h>
  14#include <linux/interrupt.h>
  15#include <linux/mii.h>
  16#include <linux/netdevice.h>
  17#include <linux/etherdevice.h>
  18#include <linux/skbuff.h>
  19#include <linux/ethtool.h>
  20#include <linux/platform_device.h>
  21#include <linux/clk.h>
  22#include <linux/gfp.h>
  23
  24#define DRV_MODULE_NAME         "w90p910-emc"
  25#define DRV_MODULE_VERSION      "0.1"
  26
  27/* Ethernet MAC Registers */
  28#define REG_CAMCMR              0x00
  29#define REG_CAMEN               0x04
  30#define REG_CAMM_BASE           0x08
  31#define REG_CAML_BASE           0x0c
  32#define REG_TXDLSA              0x88
  33#define REG_RXDLSA              0x8C
  34#define REG_MCMDR               0x90
  35#define REG_MIID                0x94
  36#define REG_MIIDA               0x98
  37#define REG_FFTCR               0x9C
  38#define REG_TSDR                0xa0
  39#define REG_RSDR                0xa4
  40#define REG_DMARFC              0xa8
  41#define REG_MIEN                0xac
  42#define REG_MISTA               0xb0
  43#define REG_CTXDSA              0xcc
  44#define REG_CTXBSA              0xd0
  45#define REG_CRXDSA              0xd4
  46#define REG_CRXBSA              0xd8
  47
  48/* mac controller bit */
  49#define MCMDR_RXON              0x01
  50#define MCMDR_ACP               (0x01 << 3)
  51#define MCMDR_SPCRC             (0x01 << 5)
  52#define MCMDR_TXON              (0x01 << 8)
  53#define MCMDR_FDUP              (0x01 << 18)
  54#define MCMDR_ENMDC             (0x01 << 19)
  55#define MCMDR_OPMOD             (0x01 << 20)
  56#define SWR                     (0x01 << 24)
  57
  58/* cam command regiser */
  59#define CAMCMR_AUP              0x01
  60#define CAMCMR_AMP              (0x01 << 1)
  61#define CAMCMR_ABP              (0x01 << 2)
  62#define CAMCMR_CCAM             (0x01 << 3)
  63#define CAMCMR_ECMP             (0x01 << 4)
  64#define CAM0EN                  0x01
  65
  66/* mac mii controller bit */
  67#define MDCCR                   (0x0a << 20)
  68#define PHYAD                   (0x01 << 8)
  69#define PHYWR                   (0x01 << 16)
  70#define PHYBUSY                 (0x01 << 17)
  71#define PHYPRESP                (0x01 << 18)
  72#define CAM_ENTRY_SIZE          0x08
  73
  74/* rx and tx status */
  75#define TXDS_TXCP               (0x01 << 19)
  76#define RXDS_CRCE               (0x01 << 17)
  77#define RXDS_PTLE               (0x01 << 19)
  78#define RXDS_RXGD               (0x01 << 20)
  79#define RXDS_ALIE               (0x01 << 21)
  80#define RXDS_RP                 (0x01 << 22)
  81
  82/* mac interrupt status*/
  83#define MISTA_EXDEF             (0x01 << 19)
  84#define MISTA_TXBERR            (0x01 << 24)
  85#define MISTA_TDU               (0x01 << 23)
  86#define MISTA_RDU               (0x01 << 10)
  87#define MISTA_RXBERR            (0x01 << 11)
  88
  89#define ENSTART                 0x01
  90#define ENRXINTR                0x01
  91#define ENRXGD                  (0x01 << 4)
  92#define ENRXBERR                (0x01 << 11)
  93#define ENTXINTR                (0x01 << 16)
  94#define ENTXCP                  (0x01 << 18)
  95#define ENTXABT                 (0x01 << 21)
  96#define ENTXBERR                (0x01 << 24)
  97#define ENMDC                   (0x01 << 19)
  98#define PHYBUSY                 (0x01 << 17)
  99#define MDCCR_VAL               0xa00000
 100
 101/* rx and tx owner bit */
 102#define RX_OWEN_DMA             (0x01 << 31)
 103#define RX_OWEN_CPU             (~(0x03 << 30))
 104#define TX_OWEN_DMA             (0x01 << 31)
 105#define TX_OWEN_CPU             (~(0x01 << 31))
 106
 107/* tx frame desc controller bit */
 108#define MACTXINTEN              0x04
 109#define CRCMODE                 0x02
 110#define PADDINGMODE             0x01
 111
 112/* fftcr controller bit */
 113#define TXTHD                   (0x03 << 8)
 114#define BLENGTH                 (0x01 << 20)
 115
 116/* global setting for driver */
 117#define RX_DESC_SIZE            50
 118#define TX_DESC_SIZE            10
 119#define MAX_RBUFF_SZ            0x600
 120#define MAX_TBUFF_SZ            0x600
 121#define TX_TIMEOUT              (HZ/2)
 122#define DELAY                   1000
 123#define CAM0                    0x0
 124
 125static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg);
 126
 127struct w90p910_rxbd {
 128        unsigned int sl;
 129        unsigned int buffer;
 130        unsigned int reserved;
 131        unsigned int next;
 132};
 133
 134struct w90p910_txbd {
 135        unsigned int mode;
 136        unsigned int buffer;
 137        unsigned int sl;
 138        unsigned int next;
 139};
 140
 141struct recv_pdesc {
 142        struct w90p910_rxbd desclist[RX_DESC_SIZE];
 143        char recv_buf[RX_DESC_SIZE][MAX_RBUFF_SZ];
 144};
 145
 146struct tran_pdesc {
 147        struct w90p910_txbd desclist[TX_DESC_SIZE];
 148        char tran_buf[TX_DESC_SIZE][MAX_TBUFF_SZ];
 149};
 150
 151struct  w90p910_ether {
 152        struct recv_pdesc *rdesc;
 153        struct tran_pdesc *tdesc;
 154        dma_addr_t rdesc_phys;
 155        dma_addr_t tdesc_phys;
 156        struct platform_device *pdev;
 157        struct resource *res;
 158        struct sk_buff *skb;
 159        struct clk *clk;
 160        struct clk *rmiiclk;
 161        struct mii_if_info mii;
 162        struct timer_list check_timer;
 163        void __iomem *reg;
 164        int rxirq;
 165        int txirq;
 166        unsigned int cur_tx;
 167        unsigned int cur_rx;
 168        unsigned int finish_tx;
 169        unsigned int rx_packets;
 170        unsigned int rx_bytes;
 171        unsigned int start_tx_ptr;
 172        unsigned int start_rx_ptr;
 173        unsigned int linkflag;
 174};
 175
 176static void update_linkspeed_register(struct net_device *dev,
 177                                unsigned int speed, unsigned int duplex)
 178{
 179        struct w90p910_ether *ether = netdev_priv(dev);
 180        unsigned int val;
 181
 182        val = __raw_readl(ether->reg + REG_MCMDR);
 183
 184        if (speed == SPEED_100) {
 185                /* 100 full/half duplex */
 186                if (duplex == DUPLEX_FULL) {
 187                        val |= (MCMDR_OPMOD | MCMDR_FDUP);
 188                } else {
 189                        val |= MCMDR_OPMOD;
 190                        val &= ~MCMDR_FDUP;
 191                }
 192        } else {
 193                /* 10 full/half duplex */
 194                if (duplex == DUPLEX_FULL) {
 195                        val |= MCMDR_FDUP;
 196                        val &= ~MCMDR_OPMOD;
 197                } else {
 198                        val &= ~(MCMDR_FDUP | MCMDR_OPMOD);
 199                }
 200        }
 201
 202        __raw_writel(val, ether->reg + REG_MCMDR);
 203}
 204
 205static void update_linkspeed(struct net_device *dev)
 206{
 207        struct w90p910_ether *ether = netdev_priv(dev);
 208        struct platform_device *pdev;
 209        unsigned int bmsr, bmcr, lpa, speed, duplex;
 210
 211        pdev = ether->pdev;
 212
 213        if (!mii_link_ok(&ether->mii)) {
 214                ether->linkflag = 0x0;
 215                netif_carrier_off(dev);
 216                dev_warn(&pdev->dev, "%s: Link down.\n", dev->name);
 217                return;
 218        }
 219
 220        if (ether->linkflag == 1)
 221                return;
 222
 223        bmsr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMSR);
 224        bmcr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMCR);
 225
 226        if (bmcr & BMCR_ANENABLE) {
 227                if (!(bmsr & BMSR_ANEGCOMPLETE))
 228                        return;
 229
 230                lpa = w90p910_mdio_read(dev, ether->mii.phy_id, MII_LPA);
 231
 232                if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF))
 233                        speed = SPEED_100;
 234                else
 235                        speed = SPEED_10;
 236
 237                if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL))
 238                        duplex = DUPLEX_FULL;
 239                else
 240                        duplex = DUPLEX_HALF;
 241
 242        } else {
 243                speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
 244                duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
 245        }
 246
 247        update_linkspeed_register(dev, speed, duplex);
 248
 249        dev_info(&pdev->dev, "%s: Link now %i-%s\n", dev->name, speed,
 250                        (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
 251        ether->linkflag = 0x01;
 252
 253        netif_carrier_on(dev);
 254}
 255
 256static void w90p910_check_link(unsigned long dev_id)
 257{
 258        struct net_device *dev = (struct net_device *) dev_id;
 259        struct w90p910_ether *ether = netdev_priv(dev);
 260
 261        update_linkspeed(dev);
 262        mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
 263}
 264
 265static void w90p910_write_cam(struct net_device *dev,
 266                                unsigned int x, unsigned char *pval)
 267{
 268        struct w90p910_ether *ether = netdev_priv(dev);
 269        unsigned int msw, lsw;
 270
 271        msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3];
 272
 273        lsw = (pval[4] << 24) | (pval[5] << 16);
 274
 275        __raw_writel(lsw, ether->reg + REG_CAML_BASE + x * CAM_ENTRY_SIZE);
 276        __raw_writel(msw, ether->reg + REG_CAMM_BASE + x * CAM_ENTRY_SIZE);
 277}
 278
 279static int w90p910_init_desc(struct net_device *dev)
 280{
 281        struct w90p910_ether *ether;
 282        struct w90p910_txbd  *tdesc;
 283        struct w90p910_rxbd  *rdesc;
 284        struct platform_device *pdev;
 285        unsigned int i;
 286
 287        ether = netdev_priv(dev);
 288        pdev = ether->pdev;
 289
 290        ether->tdesc = dma_alloc_coherent(&pdev->dev, sizeof(struct tran_pdesc),
 291                                          &ether->tdesc_phys, GFP_KERNEL);
 292        if (!ether->tdesc)
 293                return -ENOMEM;
 294
 295        ether->rdesc = dma_alloc_coherent(&pdev->dev, sizeof(struct recv_pdesc),
 296                                          &ether->rdesc_phys, GFP_KERNEL);
 297        if (!ether->rdesc) {
 298                dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
 299                                  ether->tdesc, ether->tdesc_phys);
 300                return -ENOMEM;
 301        }
 302
 303        for (i = 0; i < TX_DESC_SIZE; i++) {
 304                unsigned int offset;
 305
 306                tdesc = &(ether->tdesc->desclist[i]);
 307
 308                if (i == TX_DESC_SIZE - 1)
 309                        offset = offsetof(struct tran_pdesc, desclist[0]);
 310                else
 311                        offset = offsetof(struct tran_pdesc, desclist[i + 1]);
 312
 313                tdesc->next = ether->tdesc_phys + offset;
 314                tdesc->buffer = ether->tdesc_phys +
 315                        offsetof(struct tran_pdesc, tran_buf[i]);
 316                tdesc->sl = 0;
 317                tdesc->mode = 0;
 318        }
 319
 320        ether->start_tx_ptr = ether->tdesc_phys;
 321
 322        for (i = 0; i < RX_DESC_SIZE; i++) {
 323                unsigned int offset;
 324
 325                rdesc = &(ether->rdesc->desclist[i]);
 326
 327                if (i == RX_DESC_SIZE - 1)
 328                        offset = offsetof(struct recv_pdesc, desclist[0]);
 329                else
 330                        offset = offsetof(struct recv_pdesc, desclist[i + 1]);
 331
 332                rdesc->next = ether->rdesc_phys + offset;
 333                rdesc->sl = RX_OWEN_DMA;
 334                rdesc->buffer = ether->rdesc_phys +
 335                        offsetof(struct recv_pdesc, recv_buf[i]);
 336          }
 337
 338        ether->start_rx_ptr = ether->rdesc_phys;
 339
 340        return 0;
 341}
 342
 343static void w90p910_set_fifo_threshold(struct net_device *dev)
 344{
 345        struct w90p910_ether *ether = netdev_priv(dev);
 346        unsigned int val;
 347
 348        val = TXTHD | BLENGTH;
 349        __raw_writel(val, ether->reg + REG_FFTCR);
 350}
 351
 352static void w90p910_return_default_idle(struct net_device *dev)
 353{
 354        struct w90p910_ether *ether = netdev_priv(dev);
 355        unsigned int val;
 356
 357        val = __raw_readl(ether->reg + REG_MCMDR);
 358        val |= SWR;
 359        __raw_writel(val, ether->reg + REG_MCMDR);
 360}
 361
 362static void w90p910_trigger_rx(struct net_device *dev)
 363{
 364        struct w90p910_ether *ether = netdev_priv(dev);
 365
 366        __raw_writel(ENSTART, ether->reg + REG_RSDR);
 367}
 368
 369static void w90p910_trigger_tx(struct net_device *dev)
 370{
 371        struct w90p910_ether *ether = netdev_priv(dev);
 372
 373        __raw_writel(ENSTART, ether->reg + REG_TSDR);
 374}
 375
 376static void w90p910_enable_mac_interrupt(struct net_device *dev)
 377{
 378        struct w90p910_ether *ether = netdev_priv(dev);
 379        unsigned int val;
 380
 381        val = ENTXINTR | ENRXINTR | ENRXGD | ENTXCP;
 382        val |= ENTXBERR | ENRXBERR | ENTXABT;
 383
 384        __raw_writel(val, ether->reg + REG_MIEN);
 385}
 386
 387static void w90p910_get_and_clear_int(struct net_device *dev,
 388                                                        unsigned int *val)
 389{
 390        struct w90p910_ether *ether = netdev_priv(dev);
 391
 392        *val = __raw_readl(ether->reg + REG_MISTA);
 393        __raw_writel(*val, ether->reg + REG_MISTA);
 394}
 395
 396static void w90p910_set_global_maccmd(struct net_device *dev)
 397{
 398        struct w90p910_ether *ether = netdev_priv(dev);
 399        unsigned int val;
 400
 401        val = __raw_readl(ether->reg + REG_MCMDR);
 402        val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | ENMDC;
 403        __raw_writel(val, ether->reg + REG_MCMDR);
 404}
 405
 406static void w90p910_enable_cam(struct net_device *dev)
 407{
 408        struct w90p910_ether *ether = netdev_priv(dev);
 409        unsigned int val;
 410
 411        w90p910_write_cam(dev, CAM0, dev->dev_addr);
 412
 413        val = __raw_readl(ether->reg + REG_CAMEN);
 414        val |= CAM0EN;
 415        __raw_writel(val, ether->reg + REG_CAMEN);
 416}
 417
 418static void w90p910_enable_cam_command(struct net_device *dev)
 419{
 420        struct w90p910_ether *ether = netdev_priv(dev);
 421        unsigned int val;
 422
 423        val = CAMCMR_ECMP | CAMCMR_ABP | CAMCMR_AMP;
 424        __raw_writel(val, ether->reg + REG_CAMCMR);
 425}
 426
 427static void w90p910_enable_tx(struct net_device *dev, unsigned int enable)
 428{
 429        struct w90p910_ether *ether = netdev_priv(dev);
 430        unsigned int val;
 431
 432        val = __raw_readl(ether->reg + REG_MCMDR);
 433
 434        if (enable)
 435                val |= MCMDR_TXON;
 436        else
 437                val &= ~MCMDR_TXON;
 438
 439        __raw_writel(val, ether->reg + REG_MCMDR);
 440}
 441
 442static void w90p910_enable_rx(struct net_device *dev, unsigned int enable)
 443{
 444        struct w90p910_ether *ether = netdev_priv(dev);
 445        unsigned int val;
 446
 447        val = __raw_readl(ether->reg + REG_MCMDR);
 448
 449        if (enable)
 450                val |= MCMDR_RXON;
 451        else
 452                val &= ~MCMDR_RXON;
 453
 454        __raw_writel(val, ether->reg + REG_MCMDR);
 455}
 456
 457static void w90p910_set_curdest(struct net_device *dev)
 458{
 459        struct w90p910_ether *ether = netdev_priv(dev);
 460
 461        __raw_writel(ether->start_rx_ptr, ether->reg + REG_RXDLSA);
 462        __raw_writel(ether->start_tx_ptr, ether->reg + REG_TXDLSA);
 463}
 464
 465static void w90p910_reset_mac(struct net_device *dev)
 466{
 467        struct w90p910_ether *ether = netdev_priv(dev);
 468
 469        w90p910_enable_tx(dev, 0);
 470        w90p910_enable_rx(dev, 0);
 471        w90p910_set_fifo_threshold(dev);
 472        w90p910_return_default_idle(dev);
 473
 474        if (!netif_queue_stopped(dev))
 475                netif_stop_queue(dev);
 476
 477        w90p910_init_desc(dev);
 478
 479        netif_trans_update(dev); /* prevent tx timeout */
 480        ether->cur_tx = 0x0;
 481        ether->finish_tx = 0x0;
 482        ether->cur_rx = 0x0;
 483
 484        w90p910_set_curdest(dev);
 485        w90p910_enable_cam(dev);
 486        w90p910_enable_cam_command(dev);
 487        w90p910_enable_mac_interrupt(dev);
 488        w90p910_enable_tx(dev, 1);
 489        w90p910_enable_rx(dev, 1);
 490        w90p910_trigger_tx(dev);
 491        w90p910_trigger_rx(dev);
 492
 493        netif_trans_update(dev); /* prevent tx timeout */
 494
 495        if (netif_queue_stopped(dev))
 496                netif_wake_queue(dev);
 497}
 498
 499static void w90p910_mdio_write(struct net_device *dev,
 500                                        int phy_id, int reg, int data)
 501{
 502        struct w90p910_ether *ether = netdev_priv(dev);
 503        struct platform_device *pdev;
 504        unsigned int val, i;
 505
 506        pdev = ether->pdev;
 507
 508        __raw_writel(data, ether->reg + REG_MIID);
 509
 510        val = (phy_id << 0x08) | reg;
 511        val |= PHYBUSY | PHYWR | MDCCR_VAL;
 512        __raw_writel(val, ether->reg + REG_MIIDA);
 513
 514        for (i = 0; i < DELAY; i++) {
 515                if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
 516                        break;
 517        }
 518
 519        if (i == DELAY)
 520                dev_warn(&pdev->dev, "mdio write timed out\n");
 521}
 522
 523static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg)
 524{
 525        struct w90p910_ether *ether = netdev_priv(dev);
 526        struct platform_device *pdev;
 527        unsigned int val, i, data;
 528
 529        pdev = ether->pdev;
 530
 531        val = (phy_id << 0x08) | reg;
 532        val |= PHYBUSY | MDCCR_VAL;
 533        __raw_writel(val, ether->reg + REG_MIIDA);
 534
 535        for (i = 0; i < DELAY; i++) {
 536                if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
 537                        break;
 538        }
 539
 540        if (i == DELAY) {
 541                dev_warn(&pdev->dev, "mdio read timed out\n");
 542                data = 0xffff;
 543        } else {
 544                data = __raw_readl(ether->reg + REG_MIID);
 545        }
 546
 547        return data;
 548}
 549
 550static int w90p910_set_mac_address(struct net_device *dev, void *addr)
 551{
 552        struct sockaddr *address = addr;
 553
 554        if (!is_valid_ether_addr(address->sa_data))
 555                return -EADDRNOTAVAIL;
 556
 557        memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
 558        w90p910_write_cam(dev, CAM0, dev->dev_addr);
 559
 560        return 0;
 561}
 562
 563static int w90p910_ether_close(struct net_device *dev)
 564{
 565        struct w90p910_ether *ether = netdev_priv(dev);
 566        struct platform_device *pdev;
 567
 568        pdev = ether->pdev;
 569
 570        dma_free_coherent(&pdev->dev, sizeof(struct recv_pdesc),
 571                                        ether->rdesc, ether->rdesc_phys);
 572        dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
 573                                        ether->tdesc, ether->tdesc_phys);
 574
 575        netif_stop_queue(dev);
 576
 577        del_timer_sync(&ether->check_timer);
 578        clk_disable(ether->rmiiclk);
 579        clk_disable(ether->clk);
 580
 581        free_irq(ether->txirq, dev);
 582        free_irq(ether->rxirq, dev);
 583
 584        return 0;
 585}
 586
 587static int w90p910_send_frame(struct net_device *dev,
 588                                        unsigned char *data, int length)
 589{
 590        struct w90p910_ether *ether;
 591        struct w90p910_txbd *txbd;
 592        struct platform_device *pdev;
 593        unsigned char *buffer;
 594
 595        ether = netdev_priv(dev);
 596        pdev = ether->pdev;
 597
 598        txbd = &ether->tdesc->desclist[ether->cur_tx];
 599        buffer = ether->tdesc->tran_buf[ether->cur_tx];
 600
 601        if (length > 1514) {
 602                dev_err(&pdev->dev, "send data %d bytes, check it\n", length);
 603                length = 1514;
 604        }
 605
 606        txbd->sl = length & 0xFFFF;
 607
 608        memcpy(buffer, data, length);
 609
 610        txbd->mode = TX_OWEN_DMA | PADDINGMODE | CRCMODE | MACTXINTEN;
 611
 612        w90p910_enable_tx(dev, 1);
 613
 614        w90p910_trigger_tx(dev);
 615
 616        if (++ether->cur_tx >= TX_DESC_SIZE)
 617                ether->cur_tx = 0;
 618
 619        txbd = &ether->tdesc->desclist[ether->cur_tx];
 620
 621        if (txbd->mode & TX_OWEN_DMA)
 622                netif_stop_queue(dev);
 623
 624        return 0;
 625}
 626
 627static int w90p910_ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
 628{
 629        struct w90p910_ether *ether = netdev_priv(dev);
 630
 631        if (!(w90p910_send_frame(dev, skb->data, skb->len))) {
 632                ether->skb = skb;
 633                dev_kfree_skb_irq(skb);
 634                return 0;
 635        }
 636        return -EAGAIN;
 637}
 638
 639static irqreturn_t w90p910_tx_interrupt(int irq, void *dev_id)
 640{
 641        struct w90p910_ether *ether;
 642        struct w90p910_txbd  *txbd;
 643        struct platform_device *pdev;
 644        struct net_device *dev;
 645        unsigned int cur_entry, entry, status;
 646
 647        dev = dev_id;
 648        ether = netdev_priv(dev);
 649        pdev = ether->pdev;
 650
 651        w90p910_get_and_clear_int(dev, &status);
 652
 653        cur_entry = __raw_readl(ether->reg + REG_CTXDSA);
 654
 655        entry = ether->tdesc_phys +
 656                offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
 657
 658        while (entry != cur_entry) {
 659                txbd = &ether->tdesc->desclist[ether->finish_tx];
 660
 661                if (++ether->finish_tx >= TX_DESC_SIZE)
 662                        ether->finish_tx = 0;
 663
 664                if (txbd->sl & TXDS_TXCP) {
 665                        dev->stats.tx_packets++;
 666                        dev->stats.tx_bytes += txbd->sl & 0xFFFF;
 667                } else {
 668                        dev->stats.tx_errors++;
 669                }
 670
 671                txbd->sl = 0x0;
 672                txbd->mode = 0x0;
 673
 674                if (netif_queue_stopped(dev))
 675                        netif_wake_queue(dev);
 676
 677                entry = ether->tdesc_phys +
 678                        offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
 679        }
 680
 681        if (status & MISTA_EXDEF) {
 682                dev_err(&pdev->dev, "emc defer exceed interrupt\n");
 683        } else if (status & MISTA_TXBERR) {
 684                dev_err(&pdev->dev, "emc bus error interrupt\n");
 685                w90p910_reset_mac(dev);
 686        } else if (status & MISTA_TDU) {
 687                if (netif_queue_stopped(dev))
 688                        netif_wake_queue(dev);
 689        }
 690
 691        return IRQ_HANDLED;
 692}
 693
 694static void netdev_rx(struct net_device *dev)
 695{
 696        struct w90p910_ether *ether;
 697        struct w90p910_rxbd *rxbd;
 698        struct platform_device *pdev;
 699        struct sk_buff *skb;
 700        unsigned char *data;
 701        unsigned int length, status, val, entry;
 702
 703        ether = netdev_priv(dev);
 704        pdev = ether->pdev;
 705
 706        rxbd = &ether->rdesc->desclist[ether->cur_rx];
 707
 708        do {
 709                val = __raw_readl(ether->reg + REG_CRXDSA);
 710
 711                entry = ether->rdesc_phys +
 712                        offsetof(struct recv_pdesc, desclist[ether->cur_rx]);
 713
 714                if (val == entry)
 715                        break;
 716
 717                status = rxbd->sl;
 718                length = status & 0xFFFF;
 719
 720                if (status & RXDS_RXGD) {
 721                        data = ether->rdesc->recv_buf[ether->cur_rx];
 722                        skb = netdev_alloc_skb(dev, length + 2);
 723                        if (!skb) {
 724                                dev->stats.rx_dropped++;
 725                                return;
 726                        }
 727
 728                        skb_reserve(skb, 2);
 729                        skb_put(skb, length);
 730                        skb_copy_to_linear_data(skb, data, length);
 731                        skb->protocol = eth_type_trans(skb, dev);
 732                        dev->stats.rx_packets++;
 733                        dev->stats.rx_bytes += length;
 734                        netif_rx(skb);
 735                } else {
 736                        dev->stats.rx_errors++;
 737
 738                        if (status & RXDS_RP) {
 739                                dev_err(&pdev->dev, "rx runt err\n");
 740                                dev->stats.rx_length_errors++;
 741                        } else if (status & RXDS_CRCE) {
 742                                dev_err(&pdev->dev, "rx crc err\n");
 743                                dev->stats.rx_crc_errors++;
 744                        } else if (status & RXDS_ALIE) {
 745                                dev_err(&pdev->dev, "rx alignment err\n");
 746                                dev->stats.rx_frame_errors++;
 747                        } else if (status & RXDS_PTLE) {
 748                                dev_err(&pdev->dev, "rx longer err\n");
 749                                dev->stats.rx_over_errors++;
 750                        }
 751                }
 752
 753                rxbd->sl = RX_OWEN_DMA;
 754                rxbd->reserved = 0x0;
 755
 756                if (++ether->cur_rx >= RX_DESC_SIZE)
 757                        ether->cur_rx = 0;
 758
 759                rxbd = &ether->rdesc->desclist[ether->cur_rx];
 760
 761        } while (1);
 762}
 763
 764static irqreturn_t w90p910_rx_interrupt(int irq, void *dev_id)
 765{
 766        struct net_device *dev;
 767        struct w90p910_ether  *ether;
 768        struct platform_device *pdev;
 769        unsigned int status;
 770
 771        dev = dev_id;
 772        ether = netdev_priv(dev);
 773        pdev = ether->pdev;
 774
 775        w90p910_get_and_clear_int(dev, &status);
 776
 777        if (status & MISTA_RDU) {
 778                netdev_rx(dev);
 779                w90p910_trigger_rx(dev);
 780
 781                return IRQ_HANDLED;
 782        } else if (status & MISTA_RXBERR) {
 783                dev_err(&pdev->dev, "emc rx bus error\n");
 784                w90p910_reset_mac(dev);
 785        }
 786
 787        netdev_rx(dev);
 788        return IRQ_HANDLED;
 789}
 790
 791static int w90p910_ether_open(struct net_device *dev)
 792{
 793        struct w90p910_ether *ether;
 794        struct platform_device *pdev;
 795
 796        ether = netdev_priv(dev);
 797        pdev = ether->pdev;
 798
 799        w90p910_reset_mac(dev);
 800        w90p910_set_fifo_threshold(dev);
 801        w90p910_set_curdest(dev);
 802        w90p910_enable_cam(dev);
 803        w90p910_enable_cam_command(dev);
 804        w90p910_enable_mac_interrupt(dev);
 805        w90p910_set_global_maccmd(dev);
 806        w90p910_enable_rx(dev, 1);
 807
 808        clk_enable(ether->rmiiclk);
 809        clk_enable(ether->clk);
 810
 811        ether->rx_packets = 0x0;
 812        ether->rx_bytes = 0x0;
 813
 814        if (request_irq(ether->txirq, w90p910_tx_interrupt,
 815                                                0x0, pdev->name, dev)) {
 816                dev_err(&pdev->dev, "register irq tx failed\n");
 817                return -EAGAIN;
 818        }
 819
 820        if (request_irq(ether->rxirq, w90p910_rx_interrupt,
 821                                                0x0, pdev->name, dev)) {
 822                dev_err(&pdev->dev, "register irq rx failed\n");
 823                free_irq(ether->txirq, dev);
 824                return -EAGAIN;
 825        }
 826
 827        mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
 828        netif_start_queue(dev);
 829        w90p910_trigger_rx(dev);
 830
 831        dev_info(&pdev->dev, "%s is OPENED\n", dev->name);
 832
 833        return 0;
 834}
 835
 836static void w90p910_ether_set_multicast_list(struct net_device *dev)
 837{
 838        struct w90p910_ether *ether;
 839        unsigned int rx_mode;
 840
 841        ether = netdev_priv(dev);
 842
 843        if (dev->flags & IFF_PROMISC)
 844                rx_mode = CAMCMR_AUP | CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
 845        else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev))
 846                rx_mode = CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
 847        else
 848                rx_mode = CAMCMR_ECMP | CAMCMR_ABP;
 849        __raw_writel(rx_mode, ether->reg + REG_CAMCMR);
 850}
 851
 852static int w90p910_ether_ioctl(struct net_device *dev,
 853                                                struct ifreq *ifr, int cmd)
 854{
 855        struct w90p910_ether *ether = netdev_priv(dev);
 856        struct mii_ioctl_data *data = if_mii(ifr);
 857
 858        return generic_mii_ioctl(&ether->mii, data, cmd, NULL);
 859}
 860
 861static void w90p910_get_drvinfo(struct net_device *dev,
 862                                        struct ethtool_drvinfo *info)
 863{
 864        strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
 865        strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
 866}
 867
 868static int w90p910_get_link_ksettings(struct net_device *dev,
 869                                      struct ethtool_link_ksettings *cmd)
 870{
 871        struct w90p910_ether *ether = netdev_priv(dev);
 872
 873        mii_ethtool_get_link_ksettings(&ether->mii, cmd);
 874
 875        return 0;
 876}
 877
 878static int w90p910_set_link_ksettings(struct net_device *dev,
 879                                      const struct ethtool_link_ksettings *cmd)
 880{
 881        struct w90p910_ether *ether = netdev_priv(dev);
 882        return mii_ethtool_set_link_ksettings(&ether->mii, cmd);
 883}
 884
 885static int w90p910_nway_reset(struct net_device *dev)
 886{
 887        struct w90p910_ether *ether = netdev_priv(dev);
 888        return mii_nway_restart(&ether->mii);
 889}
 890
 891static u32 w90p910_get_link(struct net_device *dev)
 892{
 893        struct w90p910_ether *ether = netdev_priv(dev);
 894        return mii_link_ok(&ether->mii);
 895}
 896
 897static const struct ethtool_ops w90p910_ether_ethtool_ops = {
 898        .get_drvinfo    = w90p910_get_drvinfo,
 899        .nway_reset     = w90p910_nway_reset,
 900        .get_link       = w90p910_get_link,
 901        .get_link_ksettings = w90p910_get_link_ksettings,
 902        .set_link_ksettings = w90p910_set_link_ksettings,
 903};
 904
 905static const struct net_device_ops w90p910_ether_netdev_ops = {
 906        .ndo_open               = w90p910_ether_open,
 907        .ndo_stop               = w90p910_ether_close,
 908        .ndo_start_xmit         = w90p910_ether_start_xmit,
 909        .ndo_set_rx_mode        = w90p910_ether_set_multicast_list,
 910        .ndo_set_mac_address    = w90p910_set_mac_address,
 911        .ndo_do_ioctl           = w90p910_ether_ioctl,
 912        .ndo_validate_addr      = eth_validate_addr,
 913};
 914
 915static void __init get_mac_address(struct net_device *dev)
 916{
 917        struct w90p910_ether *ether = netdev_priv(dev);
 918        struct platform_device *pdev;
 919        char addr[ETH_ALEN];
 920
 921        pdev = ether->pdev;
 922
 923        addr[0] = 0x00;
 924        addr[1] = 0x02;
 925        addr[2] = 0xac;
 926        addr[3] = 0x55;
 927        addr[4] = 0x88;
 928        addr[5] = 0xa8;
 929
 930        if (is_valid_ether_addr(addr))
 931                memcpy(dev->dev_addr, &addr, ETH_ALEN);
 932        else
 933                dev_err(&pdev->dev, "invalid mac address\n");
 934}
 935
 936static int w90p910_ether_setup(struct net_device *dev)
 937{
 938        struct w90p910_ether *ether = netdev_priv(dev);
 939
 940        dev->netdev_ops = &w90p910_ether_netdev_ops;
 941        dev->ethtool_ops = &w90p910_ether_ethtool_ops;
 942
 943        dev->tx_queue_len = 16;
 944        dev->dma = 0x0;
 945        dev->watchdog_timeo = TX_TIMEOUT;
 946
 947        get_mac_address(dev);
 948
 949        ether->cur_tx = 0x0;
 950        ether->cur_rx = 0x0;
 951        ether->finish_tx = 0x0;
 952        ether->linkflag = 0x0;
 953        ether->mii.phy_id = 0x01;
 954        ether->mii.phy_id_mask = 0x1f;
 955        ether->mii.reg_num_mask = 0x1f;
 956        ether->mii.dev = dev;
 957        ether->mii.mdio_read = w90p910_mdio_read;
 958        ether->mii.mdio_write = w90p910_mdio_write;
 959
 960        setup_timer(&ether->check_timer, w90p910_check_link,
 961                                                (unsigned long)dev);
 962
 963        return 0;
 964}
 965
 966static int w90p910_ether_probe(struct platform_device *pdev)
 967{
 968        struct w90p910_ether *ether;
 969        struct net_device *dev;
 970        int error;
 971
 972        dev = alloc_etherdev(sizeof(struct w90p910_ether));
 973        if (!dev)
 974                return -ENOMEM;
 975
 976        ether = netdev_priv(dev);
 977
 978        ether->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 979        if (ether->res == NULL) {
 980                dev_err(&pdev->dev, "failed to get I/O memory\n");
 981                error = -ENXIO;
 982                goto failed_free;
 983        }
 984
 985        if (!request_mem_region(ether->res->start,
 986                                resource_size(ether->res), pdev->name)) {
 987                dev_err(&pdev->dev, "failed to request I/O memory\n");
 988                error = -EBUSY;
 989                goto failed_free;
 990        }
 991
 992        ether->reg = ioremap(ether->res->start, resource_size(ether->res));
 993        if (ether->reg == NULL) {
 994                dev_err(&pdev->dev, "failed to remap I/O memory\n");
 995                error = -ENXIO;
 996                goto failed_free_mem;
 997        }
 998
 999        ether->txirq = platform_get_irq(pdev, 0);
1000        if (ether->txirq < 0) {
1001                dev_err(&pdev->dev, "failed to get ether tx irq\n");
1002                error = -ENXIO;
1003                goto failed_free_io;
1004        }
1005
1006        ether->rxirq = platform_get_irq(pdev, 1);
1007        if (ether->rxirq < 0) {
1008                dev_err(&pdev->dev, "failed to get ether rx irq\n");
1009                error = -ENXIO;
1010                goto failed_free_io;
1011        }
1012
1013        platform_set_drvdata(pdev, dev);
1014
1015        ether->clk = clk_get(&pdev->dev, NULL);
1016        if (IS_ERR(ether->clk)) {
1017                dev_err(&pdev->dev, "failed to get ether clock\n");
1018                error = PTR_ERR(ether->clk);
1019                goto failed_free_io;
1020        }
1021
1022        ether->rmiiclk = clk_get(&pdev->dev, "RMII");
1023        if (IS_ERR(ether->rmiiclk)) {
1024                dev_err(&pdev->dev, "failed to get ether clock\n");
1025                error = PTR_ERR(ether->rmiiclk);
1026                goto failed_put_clk;
1027        }
1028
1029        ether->pdev = pdev;
1030
1031        w90p910_ether_setup(dev);
1032
1033        error = register_netdev(dev);
1034        if (error != 0) {
1035                dev_err(&pdev->dev, "Register EMC w90p910 FAILED\n");
1036                error = -ENODEV;
1037                goto failed_put_rmiiclk;
1038        }
1039
1040        return 0;
1041failed_put_rmiiclk:
1042        clk_put(ether->rmiiclk);
1043failed_put_clk:
1044        clk_put(ether->clk);
1045failed_free_io:
1046        iounmap(ether->reg);
1047failed_free_mem:
1048        release_mem_region(ether->res->start, resource_size(ether->res));
1049failed_free:
1050        free_netdev(dev);
1051        return error;
1052}
1053
1054static int w90p910_ether_remove(struct platform_device *pdev)
1055{
1056        struct net_device *dev = platform_get_drvdata(pdev);
1057        struct w90p910_ether *ether = netdev_priv(dev);
1058
1059        unregister_netdev(dev);
1060
1061        clk_put(ether->rmiiclk);
1062        clk_put(ether->clk);
1063
1064        iounmap(ether->reg);
1065        release_mem_region(ether->res->start, resource_size(ether->res));
1066
1067        del_timer_sync(&ether->check_timer);
1068
1069        free_netdev(dev);
1070        return 0;
1071}
1072
1073static struct platform_driver w90p910_ether_driver = {
1074        .probe          = w90p910_ether_probe,
1075        .remove         = w90p910_ether_remove,
1076        .driver         = {
1077                .name   = "nuc900-emc",
1078        },
1079};
1080
1081module_platform_driver(w90p910_ether_driver);
1082
1083MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
1084MODULE_DESCRIPTION("w90p910 MAC driver!");
1085MODULE_LICENSE("GPL");
1086MODULE_ALIAS("platform:nuc900-emc");
1087
1088