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34static const char version[] =
35"atp.c:v1.09=ac 2002/10/01 Donald Becker <becker@scyld.com>\n";
36
37
38
39
40static int debug = 1;
41#define net_debug debug
42
43
44static int max_interrupt_work = 15;
45
46#define NUM_UNITS 2
47
48static int io[NUM_UNITS];
49static int irq[NUM_UNITS];
50static int xcvr[NUM_UNITS];
51
52
53
54
55#define TX_TIMEOUT (400*HZ/1000)
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125#include <linux/kernel.h>
126#include <linux/module.h>
127#include <linux/types.h>
128#include <linux/fcntl.h>
129#include <linux/interrupt.h>
130#include <linux/ioport.h>
131#include <linux/in.h>
132#include <linux/string.h>
133#include <linux/errno.h>
134#include <linux/init.h>
135#include <linux/crc32.h>
136#include <linux/netdevice.h>
137#include <linux/etherdevice.h>
138#include <linux/skbuff.h>
139#include <linux/spinlock.h>
140#include <linux/delay.h>
141#include <linux/bitops.h>
142
143#include <asm/io.h>
144#include <asm/dma.h>
145
146#include "atp.h"
147
148MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
149MODULE_DESCRIPTION("RealTek RTL8002/8012 parallel port Ethernet driver");
150MODULE_LICENSE("GPL");
151
152module_param(max_interrupt_work, int, 0);
153module_param(debug, int, 0);
154module_param_hw_array(io, int, ioport, NULL, 0);
155module_param_hw_array(irq, int, irq, NULL, 0);
156module_param_array(xcvr, int, NULL, 0);
157MODULE_PARM_DESC(max_interrupt_work, "ATP maximum events handled per interrupt");
158MODULE_PARM_DESC(debug, "ATP debug level (0-7)");
159MODULE_PARM_DESC(io, "ATP I/O base address(es)");
160MODULE_PARM_DESC(irq, "ATP IRQ number(s)");
161MODULE_PARM_DESC(xcvr, "ATP transceiver(s) (0=internal, 1=external)");
162
163
164#define ETHERCARD_TOTAL_SIZE 3
165
166
167static char mux_8012[] = { 0xff, 0xf7, 0xff, 0xfb, 0xf3, 0xfb, 0xff, 0xf7,};
168
169struct net_local {
170 spinlock_t lock;
171 struct net_device *next_module;
172 struct timer_list timer;
173 unsigned long last_rx_time;
174 int saved_tx_size;
175 unsigned int tx_unit_busy:1;
176 unsigned char re_tx,
177 addr_mode,
178 pac_cnt_in_tx_buf;
179};
180
181
182
183
184#define TIMED_CHECKER (HZ/4)
185#ifdef TIMED_CHECKER
186#include <linux/timer.h>
187static void atp_timed_checker(unsigned long ignored);
188#endif
189
190
191
192static int atp_probe1(long ioaddr);
193static void get_node_ID(struct net_device *dev);
194static unsigned short eeprom_op(long ioaddr, unsigned int cmd);
195static int net_open(struct net_device *dev);
196static void hardware_init(struct net_device *dev);
197static void write_packet(long ioaddr, int length, unsigned char *packet, int pad, int mode);
198static void trigger_send(long ioaddr, int length);
199static netdev_tx_t atp_send_packet(struct sk_buff *skb,
200 struct net_device *dev);
201static irqreturn_t atp_interrupt(int irq, void *dev_id);
202static void net_rx(struct net_device *dev);
203static void read_block(long ioaddr, int length, unsigned char *buffer, int data_mode);
204static int net_close(struct net_device *dev);
205static void set_rx_mode(struct net_device *dev);
206static void tx_timeout(struct net_device *dev);
207
208
209
210static struct net_device *root_atp_dev;
211
212
213
214
215
216
217
218
219
220static int __init atp_init(void)
221{
222 int *port, ports[] = {0x378, 0x278, 0x3bc, 0};
223 int base_addr = io[0];
224
225 if (base_addr > 0x1ff)
226 return atp_probe1(base_addr);
227 else if (base_addr == 1)
228 return -ENXIO;
229
230 for (port = ports; *port; port++) {
231 long ioaddr = *port;
232 outb(0x57, ioaddr + PAR_DATA);
233 if (inb(ioaddr + PAR_DATA) != 0x57)
234 continue;
235 if (atp_probe1(ioaddr) == 0)
236 return 0;
237 }
238
239 return -ENODEV;
240}
241
242static const struct net_device_ops atp_netdev_ops = {
243 .ndo_open = net_open,
244 .ndo_stop = net_close,
245 .ndo_start_xmit = atp_send_packet,
246 .ndo_set_rx_mode = set_rx_mode,
247 .ndo_tx_timeout = tx_timeout,
248 .ndo_set_mac_address = eth_mac_addr,
249 .ndo_validate_addr = eth_validate_addr,
250};
251
252static int __init atp_probe1(long ioaddr)
253{
254 struct net_device *dev = NULL;
255 struct net_local *lp;
256 int saved_ctrl_reg, status, i;
257 int res;
258
259 outb(0xff, ioaddr + PAR_DATA);
260
261
262 saved_ctrl_reg = inb(ioaddr + PAR_CONTROL);
263 if (net_debug > 3)
264 printk("atp: Control register was %#2.2x.\n", saved_ctrl_reg);
265
266 outb(0x04, ioaddr + PAR_CONTROL);
267#ifndef final_version
268 if (net_debug > 3) {
269
270 for (i = 0; i < 8; i++)
271 outb(mux_8012[i], ioaddr + PAR_DATA);
272 write_reg(ioaddr, MODSEL, 0x00);
273 printk("atp: Registers are ");
274 for (i = 0; i < 32; i++)
275 printk(" %2.2x", read_nibble(ioaddr, i));
276 printk(".\n");
277 }
278#endif
279
280 for (i = 0; i < 8; i++)
281 outb(mux_8012[i], ioaddr + PAR_DATA);
282 write_reg_high(ioaddr, CMR1, CMR1h_RESET);
283
284 status = read_nibble(ioaddr, CMR1);
285
286 if (net_debug > 3) {
287 printk(KERN_DEBUG "atp: Status nibble was %#2.2x..", status);
288 for (i = 0; i < 32; i++)
289 printk(" %2.2x", read_nibble(ioaddr, i));
290 printk("\n");
291 }
292
293 if ((status & 0x78) != 0x08) {
294
295 outb(saved_ctrl_reg, ioaddr + PAR_CONTROL);
296 return -ENODEV;
297 }
298 status = read_nibble(ioaddr, CMR2_h);
299 if ((status & 0x78) != 0x10) {
300 outb(saved_ctrl_reg, ioaddr + PAR_CONTROL);
301 return -ENODEV;
302 }
303
304 dev = alloc_etherdev(sizeof(struct net_local));
305 if (!dev)
306 return -ENOMEM;
307
308
309 write_reg_byte(ioaddr, CMR2, 0x01);
310 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
311
312
313 if (irq[0])
314 dev->irq = irq[0];
315 else if (ioaddr == 0x378)
316 dev->irq = 7;
317 else
318 dev->irq = 5;
319 write_reg_high(ioaddr, CMR1, CMR1h_TxRxOFF);
320 write_reg(ioaddr, CMR2, CMR2_NULL);
321
322 dev->base_addr = ioaddr;
323
324
325 get_node_ID(dev);
326
327#ifndef MODULE
328 if (net_debug)
329 printk(KERN_INFO "%s", version);
330#endif
331
332 printk(KERN_NOTICE "%s: Pocket adapter found at %#3lx, IRQ %d, "
333 "SAPROM %pM.\n",
334 dev->name, dev->base_addr, dev->irq, dev->dev_addr);
335
336
337 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX);
338
339 lp = netdev_priv(dev);
340 lp->addr_mode = CMR2h_Normal;
341 spin_lock_init(&lp->lock);
342
343
344 if (xcvr[0])
345 dev->if_port = xcvr[0];
346 else
347 dev->if_port = (dev->mem_start & 0xf) ? (dev->mem_start & 0x7) : 4;
348 if (dev->mem_end & 0xf)
349 net_debug = dev->mem_end & 7;
350
351 dev->netdev_ops = &atp_netdev_ops;
352 dev->watchdog_timeo = TX_TIMEOUT;
353
354 res = register_netdev(dev);
355 if (res) {
356 free_netdev(dev);
357 return res;
358 }
359
360 lp->next_module = root_atp_dev;
361 root_atp_dev = dev;
362
363 return 0;
364}
365
366
367static void __init get_node_ID(struct net_device *dev)
368{
369 long ioaddr = dev->base_addr;
370 int sa_offset = 0;
371 int i;
372
373 write_reg(ioaddr, CMR2, CMR2_EEPROM);
374
375
376
377 if (eeprom_op(ioaddr, EE_READ(0)) == 0xffff)
378 sa_offset = 15;
379
380 for (i = 0; i < 3; i++)
381 ((__be16 *)dev->dev_addr)[i] =
382 cpu_to_be16(eeprom_op(ioaddr, EE_READ(sa_offset + i)));
383
384 write_reg(ioaddr, CMR2, CMR2_NULL);
385}
386
387
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391
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397
398
399static unsigned short __init eeprom_op(long ioaddr, u32 cmd)
400{
401 unsigned eedata_out = 0;
402 int num_bits = EE_CMD_SIZE;
403
404 while (--num_bits >= 0) {
405 char outval = (cmd & (1<<num_bits)) ? EE_DATA_WRITE : 0;
406 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_LOW);
407 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_HIGH);
408 eedata_out <<= 1;
409 if (read_nibble(ioaddr, PROM_DATA) & EE_DATA_READ)
410 eedata_out++;
411 }
412 write_reg_high(ioaddr, PROM_CMD, EE_CLK_LOW & ~EE_CS);
413 return eedata_out;
414}
415
416
417
418
419
420
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422
423
424
425
426
427static int net_open(struct net_device *dev)
428{
429 struct net_local *lp = netdev_priv(dev);
430 int ret;
431
432
433
434
435 ret = request_irq(dev->irq, atp_interrupt, 0, dev->name, dev);
436 if (ret)
437 return ret;
438
439 hardware_init(dev);
440
441 init_timer(&lp->timer);
442 lp->timer.expires = jiffies + TIMED_CHECKER;
443 lp->timer.data = (unsigned long)dev;
444 lp->timer.function = atp_timed_checker;
445 add_timer(&lp->timer);
446
447 netif_start_queue(dev);
448 return 0;
449}
450
451
452
453static void hardware_init(struct net_device *dev)
454{
455 struct net_local *lp = netdev_priv(dev);
456 long ioaddr = dev->base_addr;
457 int i;
458
459
460 for (i = 0; i < 8; i++)
461 outb(mux_8012[i], ioaddr + PAR_DATA);
462 write_reg_high(ioaddr, CMR1, CMR1h_RESET);
463
464 for (i = 0; i < 6; i++)
465 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]);
466
467 write_reg_high(ioaddr, CMR2, lp->addr_mode);
468
469 if (net_debug > 2) {
470 printk(KERN_DEBUG "%s: Reset: current Rx mode %d.\n", dev->name,
471 (read_nibble(ioaddr, CMR2_h) >> 3) & 0x0f);
472 }
473
474 write_reg(ioaddr, CMR2, CMR2_IRQOUT);
475 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
476
477
478 outb(Ctrl_SelData + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
479
480
481 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
482 write_reg_high(ioaddr, IMR, ISRh_RxErr);
483
484 lp->tx_unit_busy = 0;
485 lp->pac_cnt_in_tx_buf = 0;
486 lp->saved_tx_size = 0;
487}
488
489static void trigger_send(long ioaddr, int length)
490{
491 write_reg_byte(ioaddr, TxCNT0, length & 0xff);
492 write_reg(ioaddr, TxCNT1, length >> 8);
493 write_reg(ioaddr, CMR1, CMR1_Xmit);
494}
495
496static void write_packet(long ioaddr, int length, unsigned char *packet, int pad_len, int data_mode)
497{
498 if (length & 1)
499 {
500 length++;
501 pad_len++;
502 }
503
504 outb(EOC+MAR, ioaddr + PAR_DATA);
505 if ((data_mode & 1) == 0) {
506
507 outb(WrAddr+MAR, ioaddr + PAR_DATA);
508 do {
509 write_byte_mode0(ioaddr, *packet++);
510 } while (--length > pad_len) ;
511 do {
512 write_byte_mode0(ioaddr, 0);
513 } while (--length > 0) ;
514 } else {
515
516 unsigned char outbyte = *packet++;
517
518 outb(Ctrl_LNibWrite + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
519 outb(WrAddr+MAR, ioaddr + PAR_DATA);
520
521 outb((outbyte & 0x0f)|0x40, ioaddr + PAR_DATA);
522 outb(outbyte & 0x0f, ioaddr + PAR_DATA);
523 outbyte >>= 4;
524 outb(outbyte & 0x0f, ioaddr + PAR_DATA);
525 outb(Ctrl_HNibWrite + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
526 while (--length > pad_len)
527 write_byte_mode1(ioaddr, *packet++);
528 while (--length > 0)
529 write_byte_mode1(ioaddr, 0);
530 }
531
532 outb(0xff, ioaddr + PAR_DATA);
533 outb(Ctrl_HNibWrite | Ctrl_SelData | Ctrl_IRQEN, ioaddr + PAR_CONTROL);
534}
535
536static void tx_timeout(struct net_device *dev)
537{
538 long ioaddr = dev->base_addr;
539
540 printk(KERN_WARNING "%s: Transmit timed out, %s?\n", dev->name,
541 inb(ioaddr + PAR_CONTROL) & 0x10 ? "network cable problem"
542 : "IRQ conflict");
543 dev->stats.tx_errors++;
544
545 hardware_init(dev);
546 netif_trans_update(dev);
547 netif_wake_queue(dev);
548 dev->stats.tx_errors++;
549}
550
551static netdev_tx_t atp_send_packet(struct sk_buff *skb,
552 struct net_device *dev)
553{
554 struct net_local *lp = netdev_priv(dev);
555 long ioaddr = dev->base_addr;
556 int length;
557 unsigned long flags;
558
559 length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
560
561 netif_stop_queue(dev);
562
563
564
565
566 spin_lock_irqsave(&lp->lock, flags);
567 write_reg(ioaddr, IMR, 0);
568 write_reg_high(ioaddr, IMR, 0);
569 spin_unlock_irqrestore(&lp->lock, flags);
570
571 write_packet(ioaddr, length, skb->data, length-skb->len, dev->if_port);
572
573 lp->pac_cnt_in_tx_buf++;
574 if (lp->tx_unit_busy == 0) {
575 trigger_send(ioaddr, length);
576 lp->saved_tx_size = 0;
577 lp->re_tx = 0;
578 lp->tx_unit_busy = 1;
579 } else
580 lp->saved_tx_size = length;
581
582 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
583 write_reg_high(ioaddr, IMR, ISRh_RxErr);
584
585 dev_kfree_skb (skb);
586 return NETDEV_TX_OK;
587}
588
589
590
591
592static irqreturn_t atp_interrupt(int irq, void *dev_instance)
593{
594 struct net_device *dev = dev_instance;
595 struct net_local *lp;
596 long ioaddr;
597 static int num_tx_since_rx;
598 int boguscount = max_interrupt_work;
599 int handled = 0;
600
601 ioaddr = dev->base_addr;
602 lp = netdev_priv(dev);
603
604 spin_lock(&lp->lock);
605
606
607 outb(Ctrl_SelData, ioaddr + PAR_CONTROL);
608
609
610 write_reg(ioaddr, CMR2, CMR2_NULL);
611 write_reg(ioaddr, IMR, 0);
612
613 if (net_debug > 5) printk(KERN_DEBUG "%s: In interrupt ", dev->name);
614 while (--boguscount > 0) {
615 int status = read_nibble(ioaddr, ISR);
616 if (net_debug > 5) printk("loop status %02x..", status);
617
618 if (status & (ISR_RxOK<<3)) {
619 handled = 1;
620 write_reg(ioaddr, ISR, ISR_RxOK);
621 do {
622 int read_status = read_nibble(ioaddr, CMR1);
623 if (net_debug > 6)
624 printk("handling Rx packet %02x..", read_status);
625
626
627 if (read_status & (CMR1_IRQ << 3)) {
628 dev->stats.rx_over_errors++;
629
630 write_reg_high(ioaddr, CMR2, CMR2h_OFF);
631 net_rx(dev);
632
633 write_reg_high(ioaddr, ISR, ISRh_RxErr);
634 write_reg_high(ioaddr, CMR2, lp->addr_mode);
635 } else if ((read_status & (CMR1_BufEnb << 3)) == 0) {
636 net_rx(dev);
637 num_tx_since_rx = 0;
638 } else
639 break;
640 } while (--boguscount > 0);
641 } else if (status & ((ISR_TxErr + ISR_TxOK)<<3)) {
642 handled = 1;
643 if (net_debug > 6) printk("handling Tx done..");
644
645
646 write_reg(ioaddr, ISR, ISR_TxErr + ISR_TxOK);
647 if (status & (ISR_TxErr<<3)) {
648 dev->stats.collisions++;
649 if (++lp->re_tx > 15) {
650 dev->stats.tx_aborted_errors++;
651 hardware_init(dev);
652 break;
653 }
654
655 if (net_debug > 6) printk("attempting to ReTx");
656 write_reg(ioaddr, CMR1, CMR1_ReXmit + CMR1_Xmit);
657 } else {
658
659 dev->stats.tx_packets++;
660 lp->pac_cnt_in_tx_buf--;
661 if ( lp->saved_tx_size) {
662 trigger_send(ioaddr, lp->saved_tx_size);
663 lp->saved_tx_size = 0;
664 lp->re_tx = 0;
665 } else
666 lp->tx_unit_busy = 0;
667 netif_wake_queue(dev);
668 }
669 num_tx_since_rx++;
670 } else if (num_tx_since_rx > 8 &&
671 time_after(jiffies, lp->last_rx_time + HZ)) {
672 if (net_debug > 2)
673 printk(KERN_DEBUG "%s: Missed packet? No Rx after %d Tx and "
674 "%ld jiffies status %02x CMR1 %02x.\n", dev->name,
675 num_tx_since_rx, jiffies - lp->last_rx_time, status,
676 (read_nibble(ioaddr, CMR1) >> 3) & 15);
677 dev->stats.rx_missed_errors++;
678 hardware_init(dev);
679 num_tx_since_rx = 0;
680 break;
681 } else
682 break;
683 }
684
685
686
687 {
688 int i;
689 for (i = 0; i < 6; i++)
690 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]);
691#if 0 && defined(TIMED_CHECKER)
692 mod_timer(&lp->timer, jiffies + TIMED_CHECKER);
693#endif
694 }
695
696
697 write_reg(ioaddr, CMR2, CMR2_IRQOUT);
698
699 outb(Ctrl_SelData + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
700
701 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
702 write_reg_high(ioaddr, IMR, ISRh_RxErr);
703
704 spin_unlock(&lp->lock);
705
706 if (net_debug > 5) printk("exiting interrupt.\n");
707 return IRQ_RETVAL(handled);
708}
709
710#ifdef TIMED_CHECKER
711
712
713static void atp_timed_checker(unsigned long data)
714{
715 struct net_device *dev = (struct net_device *)data;
716 long ioaddr = dev->base_addr;
717 struct net_local *lp = netdev_priv(dev);
718 int tickssofar = jiffies - lp->last_rx_time;
719 int i;
720
721 spin_lock(&lp->lock);
722 if (tickssofar > 2*HZ) {
723#if 1
724 for (i = 0; i < 6; i++)
725 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]);
726 lp->last_rx_time = jiffies;
727#else
728 for (i = 0; i < 6; i++)
729 if (read_cmd_byte(ioaddr, PAR0 + i) != atp_timed_dev->dev_addr[i])
730 {
731 struct net_local *lp = netdev_priv(atp_timed_dev);
732 write_reg_byte(ioaddr, PAR0 + i, atp_timed_dev->dev_addr[i]);
733 if (i == 2)
734 dev->stats.tx_errors++;
735 else if (i == 3)
736 dev->stats.tx_dropped++;
737 else if (i == 4)
738 dev->stats.collisions++;
739 else
740 dev->stats.rx_errors++;
741 }
742#endif
743 }
744 spin_unlock(&lp->lock);
745 lp->timer.expires = jiffies + TIMED_CHECKER;
746 add_timer(&lp->timer);
747}
748#endif
749
750
751static void net_rx(struct net_device *dev)
752{
753 struct net_local *lp = netdev_priv(dev);
754 long ioaddr = dev->base_addr;
755 struct rx_header rx_head;
756
757
758 outb(EOC+MAR, ioaddr + PAR_DATA);
759 read_block(ioaddr, 8, (unsigned char*)&rx_head, dev->if_port);
760 if (net_debug > 5)
761 printk(KERN_DEBUG " rx_count %04x %04x %04x %04x..", rx_head.pad,
762 rx_head.rx_count, rx_head.rx_status, rx_head.cur_addr);
763 if ((rx_head.rx_status & 0x77) != 0x01) {
764 dev->stats.rx_errors++;
765 if (rx_head.rx_status & 0x0004) dev->stats.rx_frame_errors++;
766 else if (rx_head.rx_status & 0x0002) dev->stats.rx_crc_errors++;
767 if (net_debug > 3)
768 printk(KERN_DEBUG "%s: Unknown ATP Rx error %04x.\n",
769 dev->name, rx_head.rx_status);
770 if (rx_head.rx_status & 0x0020) {
771 dev->stats.rx_fifo_errors++;
772 write_reg_high(ioaddr, CMR1, CMR1h_TxENABLE);
773 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
774 } else if (rx_head.rx_status & 0x0050)
775 hardware_init(dev);
776 return;
777 } else {
778
779 int pkt_len = (rx_head.rx_count & 0x7ff) - 4;
780 struct sk_buff *skb;
781
782 skb = netdev_alloc_skb(dev, pkt_len + 2);
783 if (skb == NULL) {
784 dev->stats.rx_dropped++;
785 goto done;
786 }
787
788 skb_reserve(skb, 2);
789 read_block(ioaddr, pkt_len, skb_put(skb,pkt_len), dev->if_port);
790 skb->protocol = eth_type_trans(skb, dev);
791 netif_rx(skb);
792 dev->stats.rx_packets++;
793 dev->stats.rx_bytes += pkt_len;
794 }
795 done:
796 write_reg(ioaddr, CMR1, CMR1_NextPkt);
797 lp->last_rx_time = jiffies;
798}
799
800static void read_block(long ioaddr, int length, unsigned char *p, int data_mode)
801{
802 if (data_mode <= 3) {
803 outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
804 outb(length == 8 ? RdAddr | HNib | MAR : RdAddr | MAR,
805 ioaddr + PAR_DATA);
806 if (data_mode <= 1) {
807 do { *p++ = read_byte_mode0(ioaddr); } while (--length > 0);
808 } else {
809 do { *p++ = read_byte_mode2(ioaddr); } while (--length > 0);
810 }
811 } else if (data_mode <= 5) {
812 do { *p++ = read_byte_mode4(ioaddr); } while (--length > 0);
813 } else {
814 do { *p++ = read_byte_mode6(ioaddr); } while (--length > 0);
815 }
816
817 outb(EOC+HNib+MAR, ioaddr + PAR_DATA);
818 outb(Ctrl_SelData, ioaddr + PAR_CONTROL);
819}
820
821
822static int
823net_close(struct net_device *dev)
824{
825 struct net_local *lp = netdev_priv(dev);
826 long ioaddr = dev->base_addr;
827
828 netif_stop_queue(dev);
829
830 del_timer_sync(&lp->timer);
831
832
833 lp->addr_mode = CMR2h_OFF;
834 write_reg_high(ioaddr, CMR2, CMR2h_OFF);
835
836
837 outb(0x00, ioaddr + PAR_CONTROL);
838 free_irq(dev->irq, dev);
839
840
841 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX);
842 return 0;
843}
844
845
846
847
848
849static void set_rx_mode(struct net_device *dev)
850{
851 struct net_local *lp = netdev_priv(dev);
852 long ioaddr = dev->base_addr;
853
854 if (!netdev_mc_empty(dev) || (dev->flags & (IFF_ALLMULTI|IFF_PROMISC)))
855 lp->addr_mode = CMR2h_PROMISC;
856 else
857 lp->addr_mode = CMR2h_Normal;
858 write_reg_high(ioaddr, CMR2, lp->addr_mode);
859}
860
861static int __init atp_init_module(void) {
862 if (debug)
863 printk(KERN_INFO "%s", version);
864 return atp_init();
865}
866
867static void __exit atp_cleanup_module(void) {
868 struct net_device *next_dev;
869
870 while (root_atp_dev) {
871 struct net_local *atp_local = netdev_priv(root_atp_dev);
872 next_dev = atp_local->next_module;
873 unregister_netdev(root_atp_dev);
874
875 free_netdev(root_atp_dev);
876 root_atp_dev = next_dev;
877 }
878}
879
880module_init(atp_init_module);
881module_exit(atp_cleanup_module);
882