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18#include <linux/kernel.h>
19#include <linux/module.h>
20
21#include "dwc-xlgmac.h"
22#include "dwc-xlgmac-reg.h"
23
24MODULE_LICENSE("Dual BSD/GPL");
25
26static int debug = -1;
27module_param(debug, int, 0644);
28MODULE_PARM_DESC(debug, "DWC ethernet debug level (0=none,...,16=all)");
29static const u32 default_msg_level = (NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
30 NETIF_MSG_IFUP);
31
32static unsigned char dev_addr[6] = {0, 0x55, 0x7b, 0xb5, 0x7d, 0xf7};
33
34static void xlgmac_read_mac_addr(struct xlgmac_pdata *pdata)
35{
36 struct net_device *netdev = pdata->netdev;
37
38
39 memcpy(pdata->mac_addr, dev_addr, netdev->addr_len);
40}
41
42static void xlgmac_default_config(struct xlgmac_pdata *pdata)
43{
44 pdata->tx_osp_mode = DMA_OSP_ENABLE;
45 pdata->tx_sf_mode = MTL_TSF_ENABLE;
46 pdata->rx_sf_mode = MTL_RSF_DISABLE;
47 pdata->pblx8 = DMA_PBL_X8_ENABLE;
48 pdata->tx_pbl = DMA_PBL_32;
49 pdata->rx_pbl = DMA_PBL_32;
50 pdata->tx_threshold = MTL_TX_THRESHOLD_128;
51 pdata->rx_threshold = MTL_RX_THRESHOLD_128;
52 pdata->tx_pause = 1;
53 pdata->rx_pause = 1;
54 pdata->phy_speed = SPEED_25000;
55 pdata->sysclk_rate = XLGMAC_SYSCLOCK;
56
57 strlcpy(pdata->drv_name, XLGMAC_DRV_NAME, sizeof(pdata->drv_name));
58 strlcpy(pdata->drv_ver, XLGMAC_DRV_VERSION, sizeof(pdata->drv_ver));
59}
60
61static void xlgmac_init_all_ops(struct xlgmac_pdata *pdata)
62{
63 xlgmac_init_desc_ops(&pdata->desc_ops);
64 xlgmac_init_hw_ops(&pdata->hw_ops);
65}
66
67static int xlgmac_init(struct xlgmac_pdata *pdata)
68{
69 struct xlgmac_hw_ops *hw_ops = &pdata->hw_ops;
70 struct net_device *netdev = pdata->netdev;
71 unsigned int i;
72 int ret;
73
74
75 xlgmac_default_config(pdata);
76
77
78 netdev->irq = pdata->dev_irq;
79 netdev->base_addr = (unsigned long)pdata->mac_regs;
80 xlgmac_read_mac_addr(pdata);
81 memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len);
82
83
84 xlgmac_init_all_ops(pdata);
85
86
87 hw_ops->exit(pdata);
88
89
90 xlgmac_get_all_hw_features(pdata);
91 xlgmac_print_all_hw_features(pdata);
92
93
94
95
96 ret = dma_set_mask_and_coherent(pdata->dev,
97 DMA_BIT_MASK(pdata->hw_feat.dma_width));
98 if (ret) {
99 dev_err(pdata->dev, "dma_set_mask_and_coherent failed\n");
100 return ret;
101 }
102
103
104
105
106
107
108
109
110 BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_TX_DESC_CNT);
111 pdata->tx_desc_count = XLGMAC_TX_DESC_CNT;
112 if (pdata->tx_desc_count & (pdata->tx_desc_count - 1)) {
113 dev_err(pdata->dev, "tx descriptor count (%d) is not valid\n",
114 pdata->tx_desc_count);
115 ret = -EINVAL;
116 return ret;
117 }
118 BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_RX_DESC_CNT);
119 pdata->rx_desc_count = XLGMAC_RX_DESC_CNT;
120 if (pdata->rx_desc_count & (pdata->rx_desc_count - 1)) {
121 dev_err(pdata->dev, "rx descriptor count (%d) is not valid\n",
122 pdata->rx_desc_count);
123 ret = -EINVAL;
124 return ret;
125 }
126
127 pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(),
128 pdata->hw_feat.tx_ch_cnt);
129 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
130 pdata->hw_feat.tx_q_cnt);
131 pdata->tx_q_count = pdata->tx_ring_count;
132 ret = netif_set_real_num_tx_queues(netdev, pdata->tx_q_count);
133 if (ret) {
134 dev_err(pdata->dev, "error setting real tx queue count\n");
135 return ret;
136 }
137
138 pdata->rx_ring_count = min_t(unsigned int,
139 netif_get_num_default_rss_queues(),
140 pdata->hw_feat.rx_ch_cnt);
141 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
142 pdata->hw_feat.rx_q_cnt);
143 pdata->rx_q_count = pdata->rx_ring_count;
144 ret = netif_set_real_num_rx_queues(netdev, pdata->rx_q_count);
145 if (ret) {
146 dev_err(pdata->dev, "error setting real rx queue count\n");
147 return ret;
148 }
149
150 pdata->channel_count =
151 max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
152
153
154 netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key));
155
156 for (i = 0; i < XLGMAC_RSS_MAX_TABLE_SIZE; i++)
157 pdata->rss_table[i] = XLGMAC_SET_REG_BITS(
158 pdata->rss_table[i],
159 MAC_RSSDR_DMCH_POS,
160 MAC_RSSDR_DMCH_LEN,
161 i % pdata->rx_ring_count);
162
163 pdata->rss_options = XLGMAC_SET_REG_BITS(
164 pdata->rss_options,
165 MAC_RSSCR_IP2TE_POS,
166 MAC_RSSCR_IP2TE_LEN, 1);
167 pdata->rss_options = XLGMAC_SET_REG_BITS(
168 pdata->rss_options,
169 MAC_RSSCR_TCP4TE_POS,
170 MAC_RSSCR_TCP4TE_LEN, 1);
171 pdata->rss_options = XLGMAC_SET_REG_BITS(
172 pdata->rss_options,
173 MAC_RSSCR_UDP4TE_POS,
174 MAC_RSSCR_UDP4TE_LEN, 1);
175
176
177 netdev->netdev_ops = xlgmac_get_netdev_ops();
178 netdev->ethtool_ops = xlgmac_get_ethtool_ops();
179
180
181 if (pdata->hw_feat.tso) {
182 netdev->hw_features = NETIF_F_TSO;
183 netdev->hw_features |= NETIF_F_TSO6;
184 netdev->hw_features |= NETIF_F_SG;
185 netdev->hw_features |= NETIF_F_IP_CSUM;
186 netdev->hw_features |= NETIF_F_IPV6_CSUM;
187 } else if (pdata->hw_feat.tx_coe) {
188 netdev->hw_features = NETIF_F_IP_CSUM;
189 netdev->hw_features |= NETIF_F_IPV6_CSUM;
190 }
191
192 if (pdata->hw_feat.rx_coe) {
193 netdev->hw_features |= NETIF_F_RXCSUM;
194 netdev->hw_features |= NETIF_F_GRO;
195 }
196
197 if (pdata->hw_feat.rss)
198 netdev->hw_features |= NETIF_F_RXHASH;
199
200 netdev->vlan_features |= netdev->hw_features;
201
202 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
203 if (pdata->hw_feat.sa_vlan_ins)
204 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
205 if (pdata->hw_feat.vlhash)
206 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
207
208 netdev->features |= netdev->hw_features;
209 pdata->netdev_features = netdev->features;
210
211 netdev->priv_flags |= IFF_UNICAST_FLT;
212
213
214 netdev->watchdog_timeo = 0;
215
216
217 pdata->tx_usecs = XLGMAC_INIT_DMA_TX_USECS;
218 pdata->tx_frames = XLGMAC_INIT_DMA_TX_FRAMES;
219
220
221 pdata->rx_riwt = hw_ops->usec_to_riwt(pdata, XLGMAC_INIT_DMA_RX_USECS);
222 pdata->rx_usecs = XLGMAC_INIT_DMA_RX_USECS;
223 pdata->rx_frames = XLGMAC_INIT_DMA_RX_FRAMES;
224
225 return 0;
226}
227
228int xlgmac_drv_probe(struct device *dev, struct xlgmac_resources *res)
229{
230 struct xlgmac_pdata *pdata;
231 struct net_device *netdev;
232 int ret;
233
234 netdev = alloc_etherdev_mq(sizeof(struct xlgmac_pdata),
235 XLGMAC_MAX_DMA_CHANNELS);
236
237 if (!netdev) {
238 dev_err(dev, "alloc_etherdev failed\n");
239 return -ENOMEM;
240 }
241
242 SET_NETDEV_DEV(netdev, dev);
243 dev_set_drvdata(dev, netdev);
244 pdata = netdev_priv(netdev);
245 pdata->dev = dev;
246 pdata->netdev = netdev;
247
248 pdata->dev_irq = res->irq;
249 pdata->mac_regs = res->addr;
250
251 mutex_init(&pdata->rss_mutex);
252 pdata->msg_enable = netif_msg_init(debug, default_msg_level);
253
254 ret = xlgmac_init(pdata);
255 if (ret) {
256 dev_err(dev, "xlgmac init failed\n");
257 goto err_free_netdev;
258 }
259
260 ret = register_netdev(netdev);
261 if (ret) {
262 dev_err(dev, "net device registration failed\n");
263 goto err_free_netdev;
264 }
265
266 return 0;
267
268err_free_netdev:
269 free_netdev(netdev);
270
271 return ret;
272}
273
274int xlgmac_drv_remove(struct device *dev)
275{
276 struct net_device *netdev = dev_get_drvdata(dev);
277
278 unregister_netdev(netdev);
279 free_netdev(netdev);
280
281 return 0;
282}
283
284void xlgmac_dump_tx_desc(struct xlgmac_pdata *pdata,
285 struct xlgmac_ring *ring,
286 unsigned int idx,
287 unsigned int count,
288 unsigned int flag)
289{
290 struct xlgmac_desc_data *desc_data;
291 struct xlgmac_dma_desc *dma_desc;
292
293 while (count--) {
294 desc_data = XLGMAC_GET_DESC_DATA(ring, idx);
295 dma_desc = desc_data->dma_desc;
296
297 netdev_dbg(pdata->netdev, "TX: dma_desc=%p, dma_desc_addr=%pad\n",
298 desc_data->dma_desc, &desc_data->dma_desc_addr);
299 netdev_dbg(pdata->netdev,
300 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
301 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
302 le32_to_cpu(dma_desc->desc0),
303 le32_to_cpu(dma_desc->desc1),
304 le32_to_cpu(dma_desc->desc2),
305 le32_to_cpu(dma_desc->desc3));
306
307 idx++;
308 }
309}
310
311void xlgmac_dump_rx_desc(struct xlgmac_pdata *pdata,
312 struct xlgmac_ring *ring,
313 unsigned int idx)
314{
315 struct xlgmac_desc_data *desc_data;
316 struct xlgmac_dma_desc *dma_desc;
317
318 desc_data = XLGMAC_GET_DESC_DATA(ring, idx);
319 dma_desc = desc_data->dma_desc;
320
321 netdev_dbg(pdata->netdev, "RX: dma_desc=%p, dma_desc_addr=%pad\n",
322 desc_data->dma_desc, &desc_data->dma_desc_addr);
323 netdev_dbg(pdata->netdev,
324 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
325 idx,
326 le32_to_cpu(dma_desc->desc0),
327 le32_to_cpu(dma_desc->desc1),
328 le32_to_cpu(dma_desc->desc2),
329 le32_to_cpu(dma_desc->desc3));
330}
331
332void xlgmac_print_pkt(struct net_device *netdev,
333 struct sk_buff *skb, bool tx_rx)
334{
335 struct ethhdr *eth = (struct ethhdr *)skb->data;
336 unsigned char *buf = skb->data;
337 unsigned char buffer[128];
338 unsigned int i, j;
339
340 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
341
342 netdev_dbg(netdev, "%s packet of %d bytes\n",
343 (tx_rx ? "TX" : "RX"), skb->len);
344
345 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
346 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
347 netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
348
349 for (i = 0, j = 0; i < skb->len;) {
350 j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx",
351 buf[i++]);
352
353 if ((i % 32) == 0) {
354 netdev_dbg(netdev, " %#06x: %s\n", i - 32, buffer);
355 j = 0;
356 } else if ((i % 16) == 0) {
357 buffer[j++] = ' ';
358 buffer[j++] = ' ';
359 } else if ((i % 4) == 0) {
360 buffer[j++] = ' ';
361 }
362 }
363 if (i % 32)
364 netdev_dbg(netdev, " %#06x: %s\n", i - (i % 32), buffer);
365
366 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
367}
368
369void xlgmac_get_all_hw_features(struct xlgmac_pdata *pdata)
370{
371 struct xlgmac_hw_features *hw_feat = &pdata->hw_feat;
372 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
373
374 mac_hfr0 = readl(pdata->mac_regs + MAC_HWF0R);
375 mac_hfr1 = readl(pdata->mac_regs + MAC_HWF1R);
376 mac_hfr2 = readl(pdata->mac_regs + MAC_HWF2R);
377
378 memset(hw_feat, 0, sizeof(*hw_feat));
379
380 hw_feat->version = readl(pdata->mac_regs + MAC_VR);
381
382
383 hw_feat->phyifsel = XLGMAC_GET_REG_BITS(mac_hfr0,
384 MAC_HWF0R_PHYIFSEL_POS,
385 MAC_HWF0R_PHYIFSEL_LEN);
386 hw_feat->vlhash = XLGMAC_GET_REG_BITS(mac_hfr0,
387 MAC_HWF0R_VLHASH_POS,
388 MAC_HWF0R_VLHASH_LEN);
389 hw_feat->sma = XLGMAC_GET_REG_BITS(mac_hfr0,
390 MAC_HWF0R_SMASEL_POS,
391 MAC_HWF0R_SMASEL_LEN);
392 hw_feat->rwk = XLGMAC_GET_REG_BITS(mac_hfr0,
393 MAC_HWF0R_RWKSEL_POS,
394 MAC_HWF0R_RWKSEL_LEN);
395 hw_feat->mgk = XLGMAC_GET_REG_BITS(mac_hfr0,
396 MAC_HWF0R_MGKSEL_POS,
397 MAC_HWF0R_MGKSEL_LEN);
398 hw_feat->mmc = XLGMAC_GET_REG_BITS(mac_hfr0,
399 MAC_HWF0R_MMCSEL_POS,
400 MAC_HWF0R_MMCSEL_LEN);
401 hw_feat->aoe = XLGMAC_GET_REG_BITS(mac_hfr0,
402 MAC_HWF0R_ARPOFFSEL_POS,
403 MAC_HWF0R_ARPOFFSEL_LEN);
404 hw_feat->ts = XLGMAC_GET_REG_BITS(mac_hfr0,
405 MAC_HWF0R_TSSEL_POS,
406 MAC_HWF0R_TSSEL_LEN);
407 hw_feat->eee = XLGMAC_GET_REG_BITS(mac_hfr0,
408 MAC_HWF0R_EEESEL_POS,
409 MAC_HWF0R_EEESEL_LEN);
410 hw_feat->tx_coe = XLGMAC_GET_REG_BITS(mac_hfr0,
411 MAC_HWF0R_TXCOESEL_POS,
412 MAC_HWF0R_TXCOESEL_LEN);
413 hw_feat->rx_coe = XLGMAC_GET_REG_BITS(mac_hfr0,
414 MAC_HWF0R_RXCOESEL_POS,
415 MAC_HWF0R_RXCOESEL_LEN);
416 hw_feat->addn_mac = XLGMAC_GET_REG_BITS(mac_hfr0,
417 MAC_HWF0R_ADDMACADRSEL_POS,
418 MAC_HWF0R_ADDMACADRSEL_LEN);
419 hw_feat->ts_src = XLGMAC_GET_REG_BITS(mac_hfr0,
420 MAC_HWF0R_TSSTSSEL_POS,
421 MAC_HWF0R_TSSTSSEL_LEN);
422 hw_feat->sa_vlan_ins = XLGMAC_GET_REG_BITS(mac_hfr0,
423 MAC_HWF0R_SAVLANINS_POS,
424 MAC_HWF0R_SAVLANINS_LEN);
425
426
427 hw_feat->rx_fifo_size = XLGMAC_GET_REG_BITS(mac_hfr1,
428 MAC_HWF1R_RXFIFOSIZE_POS,
429 MAC_HWF1R_RXFIFOSIZE_LEN);
430 hw_feat->tx_fifo_size = XLGMAC_GET_REG_BITS(mac_hfr1,
431 MAC_HWF1R_TXFIFOSIZE_POS,
432 MAC_HWF1R_TXFIFOSIZE_LEN);
433 hw_feat->adv_ts_hi = XLGMAC_GET_REG_BITS(mac_hfr1,
434 MAC_HWF1R_ADVTHWORD_POS,
435 MAC_HWF1R_ADVTHWORD_LEN);
436 hw_feat->dma_width = XLGMAC_GET_REG_BITS(mac_hfr1,
437 MAC_HWF1R_ADDR64_POS,
438 MAC_HWF1R_ADDR64_LEN);
439 hw_feat->dcb = XLGMAC_GET_REG_BITS(mac_hfr1,
440 MAC_HWF1R_DCBEN_POS,
441 MAC_HWF1R_DCBEN_LEN);
442 hw_feat->sph = XLGMAC_GET_REG_BITS(mac_hfr1,
443 MAC_HWF1R_SPHEN_POS,
444 MAC_HWF1R_SPHEN_LEN);
445 hw_feat->tso = XLGMAC_GET_REG_BITS(mac_hfr1,
446 MAC_HWF1R_TSOEN_POS,
447 MAC_HWF1R_TSOEN_LEN);
448 hw_feat->dma_debug = XLGMAC_GET_REG_BITS(mac_hfr1,
449 MAC_HWF1R_DBGMEMA_POS,
450 MAC_HWF1R_DBGMEMA_LEN);
451 hw_feat->rss = XLGMAC_GET_REG_BITS(mac_hfr1,
452 MAC_HWF1R_RSSEN_POS,
453 MAC_HWF1R_RSSEN_LEN);
454 hw_feat->tc_cnt = XLGMAC_GET_REG_BITS(mac_hfr1,
455 MAC_HWF1R_NUMTC_POS,
456 MAC_HWF1R_NUMTC_LEN);
457 hw_feat->hash_table_size = XLGMAC_GET_REG_BITS(mac_hfr1,
458 MAC_HWF1R_HASHTBLSZ_POS,
459 MAC_HWF1R_HASHTBLSZ_LEN);
460 hw_feat->l3l4_filter_num = XLGMAC_GET_REG_BITS(mac_hfr1,
461 MAC_HWF1R_L3L4FNUM_POS,
462 MAC_HWF1R_L3L4FNUM_LEN);
463
464
465 hw_feat->rx_q_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
466 MAC_HWF2R_RXQCNT_POS,
467 MAC_HWF2R_RXQCNT_LEN);
468 hw_feat->tx_q_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
469 MAC_HWF2R_TXQCNT_POS,
470 MAC_HWF2R_TXQCNT_LEN);
471 hw_feat->rx_ch_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
472 MAC_HWF2R_RXCHCNT_POS,
473 MAC_HWF2R_RXCHCNT_LEN);
474 hw_feat->tx_ch_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
475 MAC_HWF2R_TXCHCNT_POS,
476 MAC_HWF2R_TXCHCNT_LEN);
477 hw_feat->pps_out_num = XLGMAC_GET_REG_BITS(mac_hfr2,
478 MAC_HWF2R_PPSOUTNUM_POS,
479 MAC_HWF2R_PPSOUTNUM_LEN);
480 hw_feat->aux_snap_num = XLGMAC_GET_REG_BITS(mac_hfr2,
481 MAC_HWF2R_AUXSNAPNUM_POS,
482 MAC_HWF2R_AUXSNAPNUM_LEN);
483
484
485 switch (hw_feat->hash_table_size) {
486 case 0:
487 break;
488 case 1:
489 hw_feat->hash_table_size = 64;
490 break;
491 case 2:
492 hw_feat->hash_table_size = 128;
493 break;
494 case 3:
495 hw_feat->hash_table_size = 256;
496 break;
497 }
498
499
500 switch (hw_feat->dma_width) {
501 case 0:
502 hw_feat->dma_width = 32;
503 break;
504 case 1:
505 hw_feat->dma_width = 40;
506 break;
507 case 2:
508 hw_feat->dma_width = 48;
509 break;
510 default:
511 hw_feat->dma_width = 32;
512 }
513
514
515
516
517 hw_feat->rx_q_cnt++;
518 hw_feat->tx_q_cnt++;
519 hw_feat->rx_ch_cnt++;
520 hw_feat->tx_ch_cnt++;
521 hw_feat->tc_cnt++;
522}
523
524void xlgmac_print_all_hw_features(struct xlgmac_pdata *pdata)
525{
526 char *str = NULL;
527
528 XLGMAC_PR("\n");
529 XLGMAC_PR("=====================================================\n");
530 XLGMAC_PR("\n");
531 XLGMAC_PR("HW support following features\n");
532 XLGMAC_PR("\n");
533
534 XLGMAC_PR("VLAN Hash Filter Selected : %s\n",
535 pdata->hw_feat.vlhash ? "YES" : "NO");
536 XLGMAC_PR("SMA (MDIO) Interface : %s\n",
537 pdata->hw_feat.sma ? "YES" : "NO");
538 XLGMAC_PR("PMT Remote Wake-up Packet Enable : %s\n",
539 pdata->hw_feat.rwk ? "YES" : "NO");
540 XLGMAC_PR("PMT Magic Packet Enable : %s\n",
541 pdata->hw_feat.mgk ? "YES" : "NO");
542 XLGMAC_PR("RMON/MMC Module Enable : %s\n",
543 pdata->hw_feat.mmc ? "YES" : "NO");
544 XLGMAC_PR("ARP Offload Enabled : %s\n",
545 pdata->hw_feat.aoe ? "YES" : "NO");
546 XLGMAC_PR("IEEE 1588-2008 Timestamp Enabled : %s\n",
547 pdata->hw_feat.ts ? "YES" : "NO");
548 XLGMAC_PR("Energy Efficient Ethernet Enabled : %s\n",
549 pdata->hw_feat.eee ? "YES" : "NO");
550 XLGMAC_PR("Transmit Checksum Offload Enabled : %s\n",
551 pdata->hw_feat.tx_coe ? "YES" : "NO");
552 XLGMAC_PR("Receive Checksum Offload Enabled : %s\n",
553 pdata->hw_feat.rx_coe ? "YES" : "NO");
554 XLGMAC_PR("Additional MAC Addresses 1-31 Selected : %s\n",
555 pdata->hw_feat.addn_mac ? "YES" : "NO");
556
557 switch (pdata->hw_feat.ts_src) {
558 case 0:
559 str = "RESERVED";
560 break;
561 case 1:
562 str = "INTERNAL";
563 break;
564 case 2:
565 str = "EXTERNAL";
566 break;
567 case 3:
568 str = "BOTH";
569 break;
570 }
571 XLGMAC_PR("Timestamp System Time Source : %s\n", str);
572
573 XLGMAC_PR("Source Address or VLAN Insertion Enable : %s\n",
574 pdata->hw_feat.sa_vlan_ins ? "YES" : "NO");
575
576
577 switch (pdata->hw_feat.rx_fifo_size) {
578 case 0:
579 str = "128 bytes";
580 break;
581 case 1:
582 str = "256 bytes";
583 break;
584 case 2:
585 str = "512 bytes";
586 break;
587 case 3:
588 str = "1 KBytes";
589 break;
590 case 4:
591 str = "2 KBytes";
592 break;
593 case 5:
594 str = "4 KBytes";
595 break;
596 case 6:
597 str = "8 KBytes";
598 break;
599 case 7:
600 str = "16 KBytes";
601 break;
602 case 8:
603 str = "32 kBytes";
604 break;
605 case 9:
606 str = "64 KBytes";
607 break;
608 case 10:
609 str = "128 KBytes";
610 break;
611 case 11:
612 str = "256 KBytes";
613 break;
614 default:
615 str = "RESERVED";
616 }
617 XLGMAC_PR("MTL Receive FIFO Size : %s\n", str);
618
619 switch (pdata->hw_feat.tx_fifo_size) {
620 case 0:
621 str = "128 bytes";
622 break;
623 case 1:
624 str = "256 bytes";
625 break;
626 case 2:
627 str = "512 bytes";
628 break;
629 case 3:
630 str = "1 KBytes";
631 break;
632 case 4:
633 str = "2 KBytes";
634 break;
635 case 5:
636 str = "4 KBytes";
637 break;
638 case 6:
639 str = "8 KBytes";
640 break;
641 case 7:
642 str = "16 KBytes";
643 break;
644 case 8:
645 str = "32 kBytes";
646 break;
647 case 9:
648 str = "64 KBytes";
649 break;
650 case 10:
651 str = "128 KBytes";
652 break;
653 case 11:
654 str = "256 KBytes";
655 break;
656 default:
657 str = "RESERVED";
658 }
659 XLGMAC_PR("MTL Transmit FIFO Size : %s\n", str);
660
661 XLGMAC_PR("IEEE 1588 High Word Register Enable : %s\n",
662 pdata->hw_feat.adv_ts_hi ? "YES" : "NO");
663 XLGMAC_PR("Address width : %u\n",
664 pdata->hw_feat.dma_width);
665 XLGMAC_PR("DCB Feature Enable : %s\n",
666 pdata->hw_feat.dcb ? "YES" : "NO");
667 XLGMAC_PR("Split Header Feature Enable : %s\n",
668 pdata->hw_feat.sph ? "YES" : "NO");
669 XLGMAC_PR("TCP Segmentation Offload Enable : %s\n",
670 pdata->hw_feat.tso ? "YES" : "NO");
671 XLGMAC_PR("DMA Debug Registers Enabled : %s\n",
672 pdata->hw_feat.dma_debug ? "YES" : "NO");
673 XLGMAC_PR("RSS Feature Enabled : %s\n",
674 pdata->hw_feat.rss ? "YES" : "NO");
675 XLGMAC_PR("Number of Traffic classes : %u\n",
676 (pdata->hw_feat.tc_cnt));
677 XLGMAC_PR("Hash Table Size : %u\n",
678 pdata->hw_feat.hash_table_size);
679 XLGMAC_PR("Total number of L3 or L4 Filters : %u\n",
680 pdata->hw_feat.l3l4_filter_num);
681
682
683 XLGMAC_PR("Number of MTL Receive Queues : %u\n",
684 pdata->hw_feat.rx_q_cnt);
685 XLGMAC_PR("Number of MTL Transmit Queues : %u\n",
686 pdata->hw_feat.tx_q_cnt);
687 XLGMAC_PR("Number of DMA Receive Channels : %u\n",
688 pdata->hw_feat.rx_ch_cnt);
689 XLGMAC_PR("Number of DMA Transmit Channels : %u\n",
690 pdata->hw_feat.tx_ch_cnt);
691
692 switch (pdata->hw_feat.pps_out_num) {
693 case 0:
694 str = "No PPS output";
695 break;
696 case 1:
697 str = "1 PPS output";
698 break;
699 case 2:
700 str = "2 PPS output";
701 break;
702 case 3:
703 str = "3 PPS output";
704 break;
705 case 4:
706 str = "4 PPS output";
707 break;
708 default:
709 str = "RESERVED";
710 }
711 XLGMAC_PR("Number of PPS Outputs : %s\n", str);
712
713 switch (pdata->hw_feat.aux_snap_num) {
714 case 0:
715 str = "No auxiliary input";
716 break;
717 case 1:
718 str = "1 auxiliary input";
719 break;
720 case 2:
721 str = "2 auxiliary input";
722 break;
723 case 3:
724 str = "3 auxiliary input";
725 break;
726 case 4:
727 str = "4 auxiliary input";
728 break;
729 default:
730 str = "RESERVED";
731 }
732 XLGMAC_PR("Number of Auxiliary Snapshot Inputs : %s", str);
733
734 XLGMAC_PR("\n");
735 XLGMAC_PR("=====================================================\n");
736 XLGMAC_PR("\n");
737}
738
