LXR linux/drivers/net/wireless/ath/ath10k/ce.h

   1/*
   2 * Copyright (c) 2005-2011 Atheros Communications Inc.
   3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
   4 *
   5 * Permission to use, copy, modify, and/or distribute this software for any
   6 * purpose with or without fee is hereby granted, provided that the above
   7 * copyright notice and this permission notice appear in all copies.
   8 *
   9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16 */
  17
  18#ifndef _CE_H_
  19#define _CE_H_
  20
  21#include "hif.h"
  22
  23#define CE_HTT_H2T_MSG_SRC_NENTRIES 8192
  24
  25/* Descriptor rings must be aligned to this boundary */
  26#define CE_DESC_RING_ALIGN      8
  27#define CE_SEND_FLAG_GATHER     0x00010000
  28
  29/*
  30 * Copy Engine support: low-level Target-side Copy Engine API.
  31 * This is a hardware access layer used by code that understands
  32 * how to use copy engines.
  33 */
  34
  35struct ath10k_ce_pipe;
  36
  37#define CE_DESC_FLAGS_GATHER         (1 << 0)
  38#define CE_DESC_FLAGS_BYTE_SWAP      (1 << 1)
  39
  40/* Following desc flags are used in QCA99X0 */
  41#define CE_DESC_FLAGS_HOST_INT_DIS      (1 << 2)
  42#define CE_DESC_FLAGS_TGT_INT_DIS       (1 << 3)
  43
  44#define CE_DESC_FLAGS_META_DATA_MASK ar->hw_values->ce_desc_meta_data_mask
  45#define CE_DESC_FLAGS_META_DATA_LSB  ar->hw_values->ce_desc_meta_data_lsb
  46
  47struct ce_desc {
  48        __le32 addr;
  49        __le16 nbytes;
  50        __le16 flags; /* %CE_DESC_FLAGS_ */
  51};
  52
  53struct ath10k_ce_ring {
  54        /* Number of entries in this ring; must be power of 2 */
  55        unsigned int nentries;
  56        unsigned int nentries_mask;
  57
  58        /*
  59         * For dest ring, this is the next index to be processed
  60         * by software after it was/is received into.
  61         *
  62         * For src ring, this is the last descriptor that was sent
  63         * and completion processed by software.
  64         *
  65         * Regardless of src or dest ring, this is an invariant
  66         * (modulo ring size):
  67         *     write index >= read index >= sw_index
  68         */
  69        unsigned int sw_index;
  70        /* cached copy */
  71        unsigned int write_index;
  72        /*
  73         * For src ring, this is the next index not yet processed by HW.
  74         * This is a cached copy of the real HW index (read index), used
  75         * for avoiding reading the HW index register more often than
  76         * necessary.
  77         * This extends the invariant:
  78         *     write index >= read index >= hw_index >= sw_index
  79         *
  80         * For dest ring, this is currently unused.
  81         */
  82        /* cached copy */
  83        unsigned int hw_index;
  84
  85        /* Start of DMA-coherent area reserved for descriptors */
  86        /* Host address space */
  87        void *base_addr_owner_space_unaligned;
  88        /* CE address space */
  89        u32 base_addr_ce_space_unaligned;
  90
  91        /*
  92         * Actual start of descriptors.
  93         * Aligned to descriptor-size boundary.
  94         * Points into reserved DMA-coherent area, above.
  95         */
  96        /* Host address space */
  97        void *base_addr_owner_space;
  98
  99        /* CE address space */
 100        u32 base_addr_ce_space;
 101
 102        /* keep last */
 103        void *per_transfer_context[0];
 104};
 105
 106struct ath10k_ce_pipe {
 107        struct ath10k *ar;
 108        unsigned int id;
 109
 110        unsigned int attr_flags;
 111
 112        u32 ctrl_addr;
 113
 114        void (*send_cb)(struct ath10k_ce_pipe *);
 115        void (*recv_cb)(struct ath10k_ce_pipe *);
 116
 117        unsigned int src_sz_max;
 118        struct ath10k_ce_ring *src_ring;
 119        struct ath10k_ce_ring *dest_ring;
 120};
 121
 122/* Copy Engine settable attributes */
 123struct ce_attr;
 124
 125struct ath10k_bus_ops {
 126        u32 (*read32)(struct ath10k *ar, u32 offset);
 127        void (*write32)(struct ath10k *ar, u32 offset, u32 value);
 128        int (*get_num_banks)(struct ath10k *ar);
 129};
 130
 131static inline struct ath10k_ce *ath10k_ce_priv(struct ath10k *ar)
 132{
 133        return (struct ath10k_ce *)ar->ce_priv;
 134}
 135
 136struct ath10k_ce {
 137        /* protects CE info */
 138        spinlock_t ce_lock;
 139        const struct ath10k_bus_ops *bus_ops;
 140        struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
 141};
 142
 143/*==================Send====================*/
 144
 145/* ath10k_ce_send flags */
 146#define CE_SEND_FLAG_BYTE_SWAP 1
 147
 148/*
 149 * Queue a source buffer to be sent to an anonymous destination buffer.
 150 *   ce         - which copy engine to use
 151 *   buffer          - address of buffer
 152 *   nbytes          - number of bytes to send
 153 *   transfer_id     - arbitrary ID; reflected to destination
 154 *   flags           - CE_SEND_FLAG_* values
 155 * Returns 0 on success; otherwise an error status.
 156 *
 157 * Note: If no flags are specified, use CE's default data swap mode.
 158 *
 159 * Implementation note: pushes 1 buffer to Source ring
 160 */
 161int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
 162                   void *per_transfer_send_context,
 163                   u32 buffer,
 164                   unsigned int nbytes,
 165                   /* 14 bits */
 166                   unsigned int transfer_id,
 167                   unsigned int flags);
 168
 169int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
 170                          void *per_transfer_context,
 171                          u32 buffer,
 172                          unsigned int nbytes,
 173                          unsigned int transfer_id,
 174                          unsigned int flags);
 175
 176void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe);
 177
 178int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe);
 179
 180/*==================Recv=======================*/
 181
 182int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe);
 183int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr);
 184int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr);
 185void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries);
 186
 187/* recv flags */
 188/* Data is byte-swapped */
 189#define CE_RECV_FLAG_SWAPPED    1
 190
 191/*
 192 * Supply data for the next completed unprocessed receive descriptor.
 193 * Pops buffer from Dest ring.
 194 */
 195int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
 196                                  void **per_transfer_contextp,
 197                                  unsigned int *nbytesp);
 198/*
 199 * Supply data for the next completed unprocessed send descriptor.
 200 * Pops 1 completed send buffer from Source ring.
 201 */
 202int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
 203                                  void **per_transfer_contextp);
 204
 205int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
 206                                         void **per_transfer_contextp);
 207
 208/*==================CE Engine Initialization=======================*/
 209
 210int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id,
 211                        const struct ce_attr *attr);
 212void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id);
 213int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
 214                         const struct ce_attr *attr);
 215void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id);
 216
 217/*==================CE Engine Shutdown=======================*/
 218/*
 219 * Support clean shutdown by allowing the caller to revoke
 220 * receive buffers.  Target DMA must be stopped before using
 221 * this API.
 222 */
 223int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
 224                               void **per_transfer_contextp,
 225                               u32 *bufferp);
 226
 227int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state,
 228                                         void **per_transfer_contextp,
 229                                         unsigned int *nbytesp);
 230
 231/*
 232 * Support clean shutdown by allowing the caller to cancel
 233 * pending sends.  Target DMA must be stopped before using
 234 * this API.
 235 */
 236int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
 237                               void **per_transfer_contextp,
 238                               u32 *bufferp,
 239                               unsigned int *nbytesp,
 240                               unsigned int *transfer_idp);
 241
 242/*==================CE Interrupt Handlers====================*/
 243void ath10k_ce_per_engine_service_any(struct ath10k *ar);
 244void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id);
 245int ath10k_ce_disable_interrupts(struct ath10k *ar);
 246void ath10k_ce_enable_interrupts(struct ath10k *ar);
 247void ath10k_ce_dump_registers(struct ath10k *ar,
 248                              struct ath10k_fw_crash_data *crash_data);
 249
 250/* ce_attr.flags values */
 251/* Use NonSnooping PCIe accesses? */
 252#define CE_ATTR_NO_SNOOP                1
 253
 254/* Byte swap data words */
 255#define CE_ATTR_BYTE_SWAP_DATA          2
 256
 257/* Swizzle descriptors? */
 258#define CE_ATTR_SWIZZLE_DESCRIPTORS     4
 259
 260/* no interrupt on copy completion */
 261#define CE_ATTR_DIS_INTR                8
 262
 263/* Attributes of an instance of a Copy Engine */
 264struct ce_attr {
 265        /* CE_ATTR_* values */
 266        unsigned int flags;
 267
 268        /* #entries in source ring - Must be a power of 2 */
 269        unsigned int src_nentries;
 270
 271        /*
 272         * Max source send size for this CE.
 273         * This is also the minimum size of a destination buffer.
 274         */
 275        unsigned int src_sz_max;
 276
 277        /* #entries in destination ring - Must be a power of 2 */
 278        unsigned int dest_nentries;
 279
 280        void (*send_cb)(struct ath10k_ce_pipe *);
 281        void (*recv_cb)(struct ath10k_ce_pipe *);
 282};
 283
 284static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
 285{
 286        return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
 287}
 288
 289#define CE_SRC_RING_TO_DESC(baddr, idx) \
 290        (&(((struct ce_desc *)baddr)[idx]))
 291
 292#define CE_DEST_RING_TO_DESC(baddr, idx) \
 293        (&(((struct ce_desc *)baddr)[idx]))
 294
 295/* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
 296#define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
 297        (((int)(toidx) - (int)(fromidx)) & (nentries_mask))
 298
 299#define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
 300#define CE_RING_IDX_ADD(nentries_mask, idx, num) \
 301                (((idx) + (num)) & (nentries_mask))
 302
 303#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \
 304                                ar->regs->ce_wrap_intr_sum_host_msi_lsb
 305#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \
 306                                ar->regs->ce_wrap_intr_sum_host_msi_mask
 307#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
 308        (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
 309                CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
 310#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS                    0x0000
 311
 312static inline u32 ath10k_ce_interrupt_summary(struct ath10k *ar)
 313{
 314        struct ath10k_ce *ce = ath10k_ce_priv(ar);
 315
 316        return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(
 317                ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS +
 318                CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
 319}
 320
 321#endif /* _CE_H_ */
 322