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14#include <linux/acpi.h>
15#include <linux/bcd.h>
16#include <linux/i2c.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/of_device.h>
20#include <linux/rtc/ds1307.h>
21#include <linux/rtc.h>
22#include <linux/slab.h>
23#include <linux/string.h>
24#include <linux/hwmon.h>
25#include <linux/hwmon-sysfs.h>
26#include <linux/clk-provider.h>
27#include <linux/regmap.h>
28
29
30
31
32
33
34
35enum ds_type {
36 ds_1307,
37 ds_1308,
38 ds_1337,
39 ds_1338,
40 ds_1339,
41 ds_1340,
42 ds_1341,
43 ds_1388,
44 ds_3231,
45 m41t0,
46 m41t00,
47 mcp794xx,
48 rx_8025,
49 rx_8130,
50 last_ds_type
51
52};
53
54
55#define DS1307_REG_SECS 0x00
56# define DS1307_BIT_CH 0x80
57# define DS1340_BIT_nEOSC 0x80
58# define MCP794XX_BIT_ST 0x80
59#define DS1307_REG_MIN 0x01
60# define M41T0_BIT_OF 0x80
61#define DS1307_REG_HOUR 0x02
62# define DS1307_BIT_12HR 0x40
63# define DS1307_BIT_PM 0x20
64# define DS1340_BIT_CENTURY_EN 0x80
65# define DS1340_BIT_CENTURY 0x40
66#define DS1307_REG_WDAY 0x03
67# define MCP794XX_BIT_VBATEN 0x08
68#define DS1307_REG_MDAY 0x04
69#define DS1307_REG_MONTH 0x05
70# define DS1337_BIT_CENTURY 0x80
71#define DS1307_REG_YEAR 0x06
72
73
74
75
76
77
78#define DS1307_REG_CONTROL 0x07
79# define DS1307_BIT_OUT 0x80
80# define DS1338_BIT_OSF 0x20
81# define DS1307_BIT_SQWE 0x10
82# define DS1307_BIT_RS1 0x02
83# define DS1307_BIT_RS0 0x01
84#define DS1337_REG_CONTROL 0x0e
85# define DS1337_BIT_nEOSC 0x80
86# define DS1339_BIT_BBSQI 0x20
87# define DS3231_BIT_BBSQW 0x40
88# define DS1337_BIT_RS2 0x10
89# define DS1337_BIT_RS1 0x08
90# define DS1337_BIT_INTCN 0x04
91# define DS1337_BIT_A2IE 0x02
92# define DS1337_BIT_A1IE 0x01
93#define DS1340_REG_CONTROL 0x07
94# define DS1340_BIT_OUT 0x80
95# define DS1340_BIT_FT 0x40
96# define DS1340_BIT_CALIB_SIGN 0x20
97# define DS1340_M_CALIBRATION 0x1f
98#define DS1340_REG_FLAG 0x09
99# define DS1340_BIT_OSF 0x80
100#define DS1337_REG_STATUS 0x0f
101# define DS1337_BIT_OSF 0x80
102# define DS3231_BIT_EN32KHZ 0x08
103# define DS1337_BIT_A2I 0x02
104# define DS1337_BIT_A1I 0x01
105#define DS1339_REG_ALARM1_SECS 0x07
106
107#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
108
109#define RX8025_REG_CTRL1 0x0e
110# define RX8025_BIT_2412 0x20
111#define RX8025_REG_CTRL2 0x0f
112# define RX8025_BIT_PON 0x10
113# define RX8025_BIT_VDET 0x40
114# define RX8025_BIT_XST 0x20
115
116struct ds1307 {
117 struct nvmem_config nvmem_cfg;
118 enum ds_type type;
119 unsigned long flags;
120#define HAS_NVRAM 0
121#define HAS_ALARM 1
122 struct device *dev;
123 struct regmap *regmap;
124 const char *name;
125 struct rtc_device *rtc;
126#ifdef CONFIG_COMMON_CLK
127 struct clk_hw clks[2];
128#endif
129};
130
131struct chip_desc {
132 unsigned alarm:1;
133 u16 nvram_offset;
134 u16 nvram_size;
135 u8 offset;
136 u8 century_reg;
137 u8 century_enable_bit;
138 u8 century_bit;
139 u8 bbsqi_bit;
140 irq_handler_t irq_handler;
141 const struct rtc_class_ops *rtc_ops;
142 u16 trickle_charger_reg;
143 u8 (*do_trickle_setup)(struct ds1307 *, u32,
144 bool);
145};
146
147static int ds1307_get_time(struct device *dev, struct rtc_time *t);
148static int ds1307_set_time(struct device *dev, struct rtc_time *t);
149static u8 do_trickle_setup_ds1339(struct ds1307 *, u32 ohms, bool diode);
150static irqreturn_t rx8130_irq(int irq, void *dev_id);
151static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t);
152static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t);
153static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled);
154static irqreturn_t mcp794xx_irq(int irq, void *dev_id);
155static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t);
156static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t);
157static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled);
158
159static const struct rtc_class_ops rx8130_rtc_ops = {
160 .read_time = ds1307_get_time,
161 .set_time = ds1307_set_time,
162 .read_alarm = rx8130_read_alarm,
163 .set_alarm = rx8130_set_alarm,
164 .alarm_irq_enable = rx8130_alarm_irq_enable,
165};
166
167static const struct rtc_class_ops mcp794xx_rtc_ops = {
168 .read_time = ds1307_get_time,
169 .set_time = ds1307_set_time,
170 .read_alarm = mcp794xx_read_alarm,
171 .set_alarm = mcp794xx_set_alarm,
172 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
173};
174
175static const struct chip_desc chips[last_ds_type] = {
176 [ds_1307] = {
177 .nvram_offset = 8,
178 .nvram_size = 56,
179 },
180 [ds_1308] = {
181 .nvram_offset = 8,
182 .nvram_size = 56,
183 },
184 [ds_1337] = {
185 .alarm = 1,
186 .century_reg = DS1307_REG_MONTH,
187 .century_bit = DS1337_BIT_CENTURY,
188 },
189 [ds_1338] = {
190 .nvram_offset = 8,
191 .nvram_size = 56,
192 },
193 [ds_1339] = {
194 .alarm = 1,
195 .century_reg = DS1307_REG_MONTH,
196 .century_bit = DS1337_BIT_CENTURY,
197 .bbsqi_bit = DS1339_BIT_BBSQI,
198 .trickle_charger_reg = 0x10,
199 .do_trickle_setup = &do_trickle_setup_ds1339,
200 },
201 [ds_1340] = {
202 .century_reg = DS1307_REG_HOUR,
203 .century_enable_bit = DS1340_BIT_CENTURY_EN,
204 .century_bit = DS1340_BIT_CENTURY,
205 .trickle_charger_reg = 0x08,
206 },
207 [ds_1341] = {
208 .century_reg = DS1307_REG_MONTH,
209 .century_bit = DS1337_BIT_CENTURY,
210 },
211 [ds_1388] = {
212 .offset = 1,
213 .trickle_charger_reg = 0x0a,
214 },
215 [ds_3231] = {
216 .alarm = 1,
217 .century_reg = DS1307_REG_MONTH,
218 .century_bit = DS1337_BIT_CENTURY,
219 .bbsqi_bit = DS3231_BIT_BBSQW,
220 },
221 [rx_8130] = {
222 .alarm = 1,
223
224 .nvram_offset = 0x20,
225 .nvram_size = 4,
226 .offset = 0x10,
227 .irq_handler = rx8130_irq,
228 .rtc_ops = &rx8130_rtc_ops,
229 },
230 [mcp794xx] = {
231 .alarm = 1,
232
233 .nvram_offset = 0x20,
234 .nvram_size = 0x40,
235 .irq_handler = mcp794xx_irq,
236 .rtc_ops = &mcp794xx_rtc_ops,
237 },
238};
239
240static const struct i2c_device_id ds1307_id[] = {
241 { "ds1307", ds_1307 },
242 { "ds1308", ds_1308 },
243 { "ds1337", ds_1337 },
244 { "ds1338", ds_1338 },
245 { "ds1339", ds_1339 },
246 { "ds1388", ds_1388 },
247 { "ds1340", ds_1340 },
248 { "ds1341", ds_1341 },
249 { "ds3231", ds_3231 },
250 { "m41t0", m41t0 },
251 { "m41t00", m41t00 },
252 { "mcp7940x", mcp794xx },
253 { "mcp7941x", mcp794xx },
254 { "pt7c4338", ds_1307 },
255 { "rx8025", rx_8025 },
256 { "isl12057", ds_1337 },
257 { "rx8130", rx_8130 },
258 { }
259};
260MODULE_DEVICE_TABLE(i2c, ds1307_id);
261
262#ifdef CONFIG_OF
263static const struct of_device_id ds1307_of_match[] = {
264 {
265 .compatible = "dallas,ds1307",
266 .data = (void *)ds_1307
267 },
268 {
269 .compatible = "dallas,ds1308",
270 .data = (void *)ds_1308
271 },
272 {
273 .compatible = "dallas,ds1337",
274 .data = (void *)ds_1337
275 },
276 {
277 .compatible = "dallas,ds1338",
278 .data = (void *)ds_1338
279 },
280 {
281 .compatible = "dallas,ds1339",
282 .data = (void *)ds_1339
283 },
284 {
285 .compatible = "dallas,ds1388",
286 .data = (void *)ds_1388
287 },
288 {
289 .compatible = "dallas,ds1340",
290 .data = (void *)ds_1340
291 },
292 {
293 .compatible = "dallas,ds1341",
294 .data = (void *)ds_1341
295 },
296 {
297 .compatible = "maxim,ds3231",
298 .data = (void *)ds_3231
299 },
300 {
301 .compatible = "st,m41t0",
302 .data = (void *)m41t00
303 },
304 {
305 .compatible = "st,m41t00",
306 .data = (void *)m41t00
307 },
308 {
309 .compatible = "microchip,mcp7940x",
310 .data = (void *)mcp794xx
311 },
312 {
313 .compatible = "microchip,mcp7941x",
314 .data = (void *)mcp794xx
315 },
316 {
317 .compatible = "pericom,pt7c4338",
318 .data = (void *)ds_1307
319 },
320 {
321 .compatible = "epson,rx8025",
322 .data = (void *)rx_8025
323 },
324 {
325 .compatible = "isil,isl12057",
326 .data = (void *)ds_1337
327 },
328 { }
329};
330MODULE_DEVICE_TABLE(of, ds1307_of_match);
331#endif
332
333#ifdef CONFIG_ACPI
334static const struct acpi_device_id ds1307_acpi_ids[] = {
335 { .id = "DS1307", .driver_data = ds_1307 },
336 { .id = "DS1308", .driver_data = ds_1308 },
337 { .id = "DS1337", .driver_data = ds_1337 },
338 { .id = "DS1338", .driver_data = ds_1338 },
339 { .id = "DS1339", .driver_data = ds_1339 },
340 { .id = "DS1388", .driver_data = ds_1388 },
341 { .id = "DS1340", .driver_data = ds_1340 },
342 { .id = "DS1341", .driver_data = ds_1341 },
343 { .id = "DS3231", .driver_data = ds_3231 },
344 { .id = "M41T0", .driver_data = m41t0 },
345 { .id = "M41T00", .driver_data = m41t00 },
346 { .id = "MCP7940X", .driver_data = mcp794xx },
347 { .id = "MCP7941X", .driver_data = mcp794xx },
348 { .id = "PT7C4338", .driver_data = ds_1307 },
349 { .id = "RX8025", .driver_data = rx_8025 },
350 { .id = "ISL12057", .driver_data = ds_1337 },
351 { }
352};
353MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
354#endif
355
356
357
358
359
360
361static irqreturn_t ds1307_irq(int irq, void *dev_id)
362{
363 struct ds1307 *ds1307 = dev_id;
364 struct mutex *lock = &ds1307->rtc->ops_lock;
365 int stat, ret;
366
367 mutex_lock(lock);
368 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
369 if (ret)
370 goto out;
371
372 if (stat & DS1337_BIT_A1I) {
373 stat &= ~DS1337_BIT_A1I;
374 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
375
376 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
377 DS1337_BIT_A1IE, 0);
378 if (ret)
379 goto out;
380
381 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
382 }
383
384out:
385 mutex_unlock(lock);
386
387 return IRQ_HANDLED;
388}
389
390
391
392static int ds1307_get_time(struct device *dev, struct rtc_time *t)
393{
394 struct ds1307 *ds1307 = dev_get_drvdata(dev);
395 int tmp, ret;
396 const struct chip_desc *chip = &chips[ds1307->type];
397 u8 regs[7];
398
399
400 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
401 sizeof(regs));
402 if (ret) {
403 dev_err(dev, "%s error %d\n", "read", ret);
404 return ret;
405 }
406
407 dev_dbg(dev, "%s: %7ph\n", "read", regs);
408
409
410 if (ds1307->type == m41t0 &&
411 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
412 dev_warn_once(dev, "oscillator failed, set time!\n");
413 return -EINVAL;
414 }
415
416 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
417 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
418 tmp = regs[DS1307_REG_HOUR] & 0x3f;
419 t->tm_hour = bcd2bin(tmp);
420 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
421 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
422 tmp = regs[DS1307_REG_MONTH] & 0x1f;
423 t->tm_mon = bcd2bin(tmp) - 1;
424 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
425
426 if (regs[chip->century_reg] & chip->century_bit &&
427 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
428 t->tm_year += 100;
429
430 dev_dbg(dev, "%s secs=%d, mins=%d, "
431 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
432 "read", t->tm_sec, t->tm_min,
433 t->tm_hour, t->tm_mday,
434 t->tm_mon, t->tm_year, t->tm_wday);
435
436
437 return rtc_valid_tm(t);
438}
439
440static int ds1307_set_time(struct device *dev, struct rtc_time *t)
441{
442 struct ds1307 *ds1307 = dev_get_drvdata(dev);
443 const struct chip_desc *chip = &chips[ds1307->type];
444 int result;
445 int tmp;
446 u8 regs[7];
447
448 dev_dbg(dev, "%s secs=%d, mins=%d, "
449 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
450 "write", t->tm_sec, t->tm_min,
451 t->tm_hour, t->tm_mday,
452 t->tm_mon, t->tm_year, t->tm_wday);
453
454 if (t->tm_year < 100)
455 return -EINVAL;
456
457#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
458 if (t->tm_year > (chip->century_bit ? 299 : 199))
459 return -EINVAL;
460#else
461 if (t->tm_year > 199)
462 return -EINVAL;
463#endif
464
465 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
466 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
467 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
468 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
469 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
470 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
471
472
473 tmp = t->tm_year - 100;
474 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
475
476 if (chip->century_enable_bit)
477 regs[chip->century_reg] |= chip->century_enable_bit;
478 if (t->tm_year > 199 && chip->century_bit)
479 regs[chip->century_reg] |= chip->century_bit;
480
481 if (ds1307->type == mcp794xx) {
482
483
484
485
486
487 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
488 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
489 }
490
491 dev_dbg(dev, "%s: %7ph\n", "write", regs);
492
493 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
494 sizeof(regs));
495 if (result) {
496 dev_err(dev, "%s error %d\n", "write", result);
497 return result;
498 }
499 return 0;
500}
501
502static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
503{
504 struct ds1307 *ds1307 = dev_get_drvdata(dev);
505 int ret;
506 u8 regs[9];
507
508 if (!test_bit(HAS_ALARM, &ds1307->flags))
509 return -EINVAL;
510
511
512 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
513 regs, sizeof(regs));
514 if (ret) {
515 dev_err(dev, "%s error %d\n", "alarm read", ret);
516 return ret;
517 }
518
519 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
520 ®s[0], ®s[4], ®s[7]);
521
522
523
524
525
526 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
527 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
528 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
529 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
530
531
532 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
533 t->pending = !!(regs[8] & DS1337_BIT_A1I);
534
535 dev_dbg(dev, "%s secs=%d, mins=%d, "
536 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
537 "alarm read", t->time.tm_sec, t->time.tm_min,
538 t->time.tm_hour, t->time.tm_mday,
539 t->enabled, t->pending);
540
541 return 0;
542}
543
544static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
545{
546 struct ds1307 *ds1307 = dev_get_drvdata(dev);
547 unsigned char regs[9];
548 u8 control, status;
549 int ret;
550
551 if (!test_bit(HAS_ALARM, &ds1307->flags))
552 return -EINVAL;
553
554 dev_dbg(dev, "%s secs=%d, mins=%d, "
555 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
556 "alarm set", t->time.tm_sec, t->time.tm_min,
557 t->time.tm_hour, t->time.tm_mday,
558 t->enabled, t->pending);
559
560
561 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
562 sizeof(regs));
563 if (ret) {
564 dev_err(dev, "%s error %d\n", "alarm write", ret);
565 return ret;
566 }
567 control = regs[7];
568 status = regs[8];
569
570 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
571 ®s[0], ®s[4], control, status);
572
573
574 regs[0] = bin2bcd(t->time.tm_sec);
575 regs[1] = bin2bcd(t->time.tm_min);
576 regs[2] = bin2bcd(t->time.tm_hour);
577 regs[3] = bin2bcd(t->time.tm_mday);
578
579
580 regs[4] = 0;
581 regs[5] = 0;
582 regs[6] = 0;
583
584
585 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
586 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
587
588 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
589 sizeof(regs));
590 if (ret) {
591 dev_err(dev, "can't set alarm time\n");
592 return ret;
593 }
594
595
596 if (t->enabled) {
597 dev_dbg(dev, "alarm IRQ armed\n");
598 regs[7] |= DS1337_BIT_A1IE;
599 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
600 }
601
602 return 0;
603}
604
605static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
606{
607 struct ds1307 *ds1307 = dev_get_drvdata(dev);
608
609 if (!test_bit(HAS_ALARM, &ds1307->flags))
610 return -ENOTTY;
611
612 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
613 DS1337_BIT_A1IE,
614 enabled ? DS1337_BIT_A1IE : 0);
615}
616
617static const struct rtc_class_ops ds13xx_rtc_ops = {
618 .read_time = ds1307_get_time,
619 .set_time = ds1307_set_time,
620 .read_alarm = ds1337_read_alarm,
621 .set_alarm = ds1337_set_alarm,
622 .alarm_irq_enable = ds1307_alarm_irq_enable,
623};
624
625
626
627
628
629
630
631#define RX8130_REG_ALARM_MIN 0x07
632#define RX8130_REG_ALARM_HOUR 0x08
633#define RX8130_REG_ALARM_WEEK_OR_DAY 0x09
634#define RX8130_REG_EXTENSION 0x0c
635#define RX8130_REG_EXTENSION_WADA BIT(3)
636#define RX8130_REG_FLAG 0x0d
637#define RX8130_REG_FLAG_AF BIT(3)
638#define RX8130_REG_CONTROL0 0x0e
639#define RX8130_REG_CONTROL0_AIE BIT(3)
640
641static irqreturn_t rx8130_irq(int irq, void *dev_id)
642{
643 struct ds1307 *ds1307 = dev_id;
644 struct mutex *lock = &ds1307->rtc->ops_lock;
645 u8 ctl[3];
646 int ret;
647
648 mutex_lock(lock);
649
650
651 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
652 sizeof(ctl));
653 if (ret < 0)
654 goto out;
655 if (!(ctl[1] & RX8130_REG_FLAG_AF))
656 goto out;
657 ctl[1] &= ~RX8130_REG_FLAG_AF;
658 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
659
660 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
661 sizeof(ctl));
662 if (ret < 0)
663 goto out;
664
665 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
666
667out:
668 mutex_unlock(lock);
669
670 return IRQ_HANDLED;
671}
672
673static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
674{
675 struct ds1307 *ds1307 = dev_get_drvdata(dev);
676 u8 ald[3], ctl[3];
677 int ret;
678
679 if (!test_bit(HAS_ALARM, &ds1307->flags))
680 return -EINVAL;
681
682
683 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
684 sizeof(ald));
685 if (ret < 0)
686 return ret;
687
688
689 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
690 sizeof(ctl));
691 if (ret < 0)
692 return ret;
693
694 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
695 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
696
697
698 t->time.tm_sec = -1;
699 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
700 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
701 t->time.tm_wday = -1;
702 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
703 t->time.tm_mon = -1;
704 t->time.tm_year = -1;
705 t->time.tm_yday = -1;
706 t->time.tm_isdst = -1;
707
708 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
709 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
710 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
711
712 return 0;
713}
714
715static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
716{
717 struct ds1307 *ds1307 = dev_get_drvdata(dev);
718 u8 ald[3], ctl[3];
719 int ret;
720
721 if (!test_bit(HAS_ALARM, &ds1307->flags))
722 return -EINVAL;
723
724 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
725 "enabled=%d pending=%d\n", __func__,
726 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
727 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
728 t->enabled, t->pending);
729
730
731 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
732 sizeof(ctl));
733 if (ret < 0)
734 return ret;
735
736 ctl[0] &= ~RX8130_REG_EXTENSION_WADA;
737 ctl[1] |= RX8130_REG_FLAG_AF;
738 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
739
740 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
741 sizeof(ctl));
742 if (ret < 0)
743 return ret;
744
745
746 ald[0] = bin2bcd(t->time.tm_min);
747 ald[1] = bin2bcd(t->time.tm_hour);
748 ald[2] = bin2bcd(t->time.tm_mday);
749
750 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
751 sizeof(ald));
752 if (ret < 0)
753 return ret;
754
755 if (!t->enabled)
756 return 0;
757
758 ctl[2] |= RX8130_REG_CONTROL0_AIE;
759
760 return regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
761 sizeof(ctl));
762}
763
764static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
765{
766 struct ds1307 *ds1307 = dev_get_drvdata(dev);
767 int ret, reg;
768
769 if (!test_bit(HAS_ALARM, &ds1307->flags))
770 return -EINVAL;
771
772 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®);
773 if (ret < 0)
774 return ret;
775
776 if (enabled)
777 reg |= RX8130_REG_CONTROL0_AIE;
778 else
779 reg &= ~RX8130_REG_CONTROL0_AIE;
780
781 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
782}
783
784
785
786
787
788
789
790#define MCP794XX_REG_WEEKDAY 0x3
791#define MCP794XX_REG_WEEKDAY_WDAY_MASK 0x7
792#define MCP794XX_REG_CONTROL 0x07
793# define MCP794XX_BIT_ALM0_EN 0x10
794# define MCP794XX_BIT_ALM1_EN 0x20
795#define MCP794XX_REG_ALARM0_BASE 0x0a
796#define MCP794XX_REG_ALARM0_CTRL 0x0d
797#define MCP794XX_REG_ALARM1_BASE 0x11
798#define MCP794XX_REG_ALARM1_CTRL 0x14
799# define MCP794XX_BIT_ALMX_IF BIT(3)
800# define MCP794XX_BIT_ALMX_C0 BIT(4)
801# define MCP794XX_BIT_ALMX_C1 BIT(5)
802# define MCP794XX_BIT_ALMX_C2 BIT(6)
803# define MCP794XX_BIT_ALMX_POL BIT(7)
804# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
805 MCP794XX_BIT_ALMX_C1 | \
806 MCP794XX_BIT_ALMX_C2)
807
808static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
809{
810 struct ds1307 *ds1307 = dev_id;
811 struct mutex *lock = &ds1307->rtc->ops_lock;
812 int reg, ret;
813
814 mutex_lock(lock);
815
816
817 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®);
818 if (ret)
819 goto out;
820 if (!(reg & MCP794XX_BIT_ALMX_IF))
821 goto out;
822 reg &= ~MCP794XX_BIT_ALMX_IF;
823 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
824 if (ret)
825 goto out;
826
827
828 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
829 MCP794XX_BIT_ALM0_EN, 0);
830 if (ret)
831 goto out;
832
833 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
834
835out:
836 mutex_unlock(lock);
837
838 return IRQ_HANDLED;
839}
840
841static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
842{
843 struct ds1307 *ds1307 = dev_get_drvdata(dev);
844 u8 regs[10];
845 int ret;
846
847 if (!test_bit(HAS_ALARM, &ds1307->flags))
848 return -EINVAL;
849
850
851 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
852 sizeof(regs));
853 if (ret)
854 return ret;
855
856 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
857
858
859 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
860 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
861 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
862 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
863 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
864 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
865 t->time.tm_year = -1;
866 t->time.tm_yday = -1;
867 t->time.tm_isdst = -1;
868
869 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
870 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
871 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
872 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
873 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
874 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
875 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
876
877 return 0;
878}
879
880static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
881{
882 struct ds1307 *ds1307 = dev_get_drvdata(dev);
883 unsigned char regs[10];
884 int ret;
885
886 if (!test_bit(HAS_ALARM, &ds1307->flags))
887 return -EINVAL;
888
889 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
890 "enabled=%d pending=%d\n", __func__,
891 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
892 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
893 t->enabled, t->pending);
894
895
896 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
897 sizeof(regs));
898 if (ret)
899 return ret;
900
901
902 regs[3] = bin2bcd(t->time.tm_sec);
903 regs[4] = bin2bcd(t->time.tm_min);
904 regs[5] = bin2bcd(t->time.tm_hour);
905 regs[6] = bin2bcd(t->time.tm_wday + 1);
906 regs[7] = bin2bcd(t->time.tm_mday);
907 regs[8] = bin2bcd(t->time.tm_mon + 1);
908
909
910 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
911
912 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
913
914 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
915
916 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
917 sizeof(regs));
918 if (ret)
919 return ret;
920
921 if (!t->enabled)
922 return 0;
923 regs[0] |= MCP794XX_BIT_ALM0_EN;
924 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
925}
926
927static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
928{
929 struct ds1307 *ds1307 = dev_get_drvdata(dev);
930
931 if (!test_bit(HAS_ALARM, &ds1307->flags))
932 return -EINVAL;
933
934 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
935 MCP794XX_BIT_ALM0_EN,
936 enabled ? MCP794XX_BIT_ALM0_EN : 0);
937}
938
939
940
941static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
942 size_t bytes)
943{
944 struct ds1307 *ds1307 = priv;
945 const struct chip_desc *chip = &chips[ds1307->type];
946
947 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
948 val, bytes);
949}
950
951static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
952 size_t bytes)
953{
954 struct ds1307 *ds1307 = priv;
955 const struct chip_desc *chip = &chips[ds1307->type];
956
957 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
958 val, bytes);
959}
960
961
962
963static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307,
964 u32 ohms, bool diode)
965{
966 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
967 DS1307_TRICKLE_CHARGER_NO_DIODE;
968
969 switch (ohms) {
970 case 250:
971 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
972 break;
973 case 2000:
974 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
975 break;
976 case 4000:
977 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
978 break;
979 default:
980 dev_warn(ds1307->dev,
981 "Unsupported ohm value %u in dt\n", ohms);
982 return 0;
983 }
984 return setup;
985}
986
987static u8 ds1307_trickle_init(struct ds1307 *ds1307,
988 const struct chip_desc *chip)
989{
990 u32 ohms;
991 bool diode = true;
992
993 if (!chip->do_trickle_setup)
994 return 0;
995
996 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
997 &ohms))
998 return 0;
999
1000 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
1001 diode = false;
1002
1003 return chip->do_trickle_setup(ds1307, ohms, diode);
1004}
1005
1006
1007
1008#ifdef CONFIG_RTC_DRV_DS1307_HWMON
1009
1010
1011
1012
1013
1014#define DS3231_REG_TEMPERATURE 0x11
1015
1016
1017
1018
1019
1020static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1021{
1022 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1023 u8 temp_buf[2];
1024 s16 temp;
1025 int ret;
1026
1027 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1028 temp_buf, sizeof(temp_buf));
1029 if (ret)
1030 return ret;
1031
1032
1033
1034
1035 temp = (temp_buf[0] << 8) | temp_buf[1];
1036 temp >>= 6;
1037 *mC = temp * 250;
1038
1039 return 0;
1040}
1041
1042static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1043 struct device_attribute *attr, char *buf)
1044{
1045 int ret;
1046 s32 temp;
1047
1048 ret = ds3231_hwmon_read_temp(dev, &temp);
1049 if (ret)
1050 return ret;
1051
1052 return sprintf(buf, "%d\n", temp);
1053}
1054static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1055 NULL, 0);
1056
1057static struct attribute *ds3231_hwmon_attrs[] = {
1058 &sensor_dev_attr_temp1_input.dev_attr.attr,
1059 NULL,
1060};
1061ATTRIBUTE_GROUPS(ds3231_hwmon);
1062
1063static void ds1307_hwmon_register(struct ds1307 *ds1307)
1064{
1065 struct device *dev;
1066
1067 if (ds1307->type != ds_3231)
1068 return;
1069
1070 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1071 ds1307,
1072 ds3231_hwmon_groups);
1073 if (IS_ERR(dev)) {
1074 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1075 PTR_ERR(dev));
1076 }
1077}
1078
1079#else
1080
1081static void ds1307_hwmon_register(struct ds1307 *ds1307)
1082{
1083}
1084
1085#endif
1086
1087
1088
1089
1090
1091
1092
1093#ifdef CONFIG_COMMON_CLK
1094
1095enum {
1096 DS3231_CLK_SQW = 0,
1097 DS3231_CLK_32KHZ,
1098};
1099
1100#define clk_sqw_to_ds1307(clk) \
1101 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1102#define clk_32khz_to_ds1307(clk) \
1103 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1104
1105static int ds3231_clk_sqw_rates[] = {
1106 1,
1107 1024,
1108 4096,
1109 8192,
1110};
1111
1112static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1113{
1114 struct mutex *lock = &ds1307->rtc->ops_lock;
1115 int ret;
1116
1117 mutex_lock(lock);
1118 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1119 mask, value);
1120 mutex_unlock(lock);
1121
1122 return ret;
1123}
1124
1125static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1126 unsigned long parent_rate)
1127{
1128 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1129 int control, ret;
1130 int rate_sel = 0;
1131
1132 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1133 if (ret)
1134 return ret;
1135 if (control & DS1337_BIT_RS1)
1136 rate_sel += 1;
1137 if (control & DS1337_BIT_RS2)
1138 rate_sel += 2;
1139
1140 return ds3231_clk_sqw_rates[rate_sel];
1141}
1142
1143static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1144 unsigned long *prate)
1145{
1146 int i;
1147
1148 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1149 if (ds3231_clk_sqw_rates[i] <= rate)
1150 return ds3231_clk_sqw_rates[i];
1151 }
1152
1153 return 0;
1154}
1155
1156static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1157 unsigned long parent_rate)
1158{
1159 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1160 int control = 0;
1161 int rate_sel;
1162
1163 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1164 rate_sel++) {
1165 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1166 break;
1167 }
1168
1169 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1170 return -EINVAL;
1171
1172 if (rate_sel & 1)
1173 control |= DS1337_BIT_RS1;
1174 if (rate_sel & 2)
1175 control |= DS1337_BIT_RS2;
1176
1177 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1178 control);
1179}
1180
1181static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1182{
1183 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1184
1185 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1186}
1187
1188static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1189{
1190 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1191
1192 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1193}
1194
1195static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1196{
1197 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1198 int control, ret;
1199
1200 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1201 if (ret)
1202 return ret;
1203
1204 return !(control & DS1337_BIT_INTCN);
1205}
1206
1207static const struct clk_ops ds3231_clk_sqw_ops = {
1208 .prepare = ds3231_clk_sqw_prepare,
1209 .unprepare = ds3231_clk_sqw_unprepare,
1210 .is_prepared = ds3231_clk_sqw_is_prepared,
1211 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1212 .round_rate = ds3231_clk_sqw_round_rate,
1213 .set_rate = ds3231_clk_sqw_set_rate,
1214};
1215
1216static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1217 unsigned long parent_rate)
1218{
1219 return 32768;
1220}
1221
1222static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1223{
1224 struct mutex *lock = &ds1307->rtc->ops_lock;
1225 int ret;
1226
1227 mutex_lock(lock);
1228 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1229 DS3231_BIT_EN32KHZ,
1230 enable ? DS3231_BIT_EN32KHZ : 0);
1231 mutex_unlock(lock);
1232
1233 return ret;
1234}
1235
1236static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1237{
1238 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1239
1240 return ds3231_clk_32khz_control(ds1307, true);
1241}
1242
1243static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1244{
1245 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1246
1247 ds3231_clk_32khz_control(ds1307, false);
1248}
1249
1250static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1251{
1252 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1253 int status, ret;
1254
1255 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1256 if (ret)
1257 return ret;
1258
1259 return !!(status & DS3231_BIT_EN32KHZ);
1260}
1261
1262static const struct clk_ops ds3231_clk_32khz_ops = {
1263 .prepare = ds3231_clk_32khz_prepare,
1264 .unprepare = ds3231_clk_32khz_unprepare,
1265 .is_prepared = ds3231_clk_32khz_is_prepared,
1266 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1267};
1268
1269static struct clk_init_data ds3231_clks_init[] = {
1270 [DS3231_CLK_SQW] = {
1271 .name = "ds3231_clk_sqw",
1272 .ops = &ds3231_clk_sqw_ops,
1273 },
1274 [DS3231_CLK_32KHZ] = {
1275 .name = "ds3231_clk_32khz",
1276 .ops = &ds3231_clk_32khz_ops,
1277 },
1278};
1279
1280static int ds3231_clks_register(struct ds1307 *ds1307)
1281{
1282 struct device_node *node = ds1307->dev->of_node;
1283 struct clk_onecell_data *onecell;
1284 int i;
1285
1286 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1287 if (!onecell)
1288 return -ENOMEM;
1289
1290 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1291 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1292 sizeof(onecell->clks[0]), GFP_KERNEL);
1293 if (!onecell->clks)
1294 return -ENOMEM;
1295
1296 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1297 struct clk_init_data init = ds3231_clks_init[i];
1298
1299
1300
1301
1302
1303 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1304 continue;
1305
1306
1307 of_property_read_string_index(node, "clock-output-names", i,
1308 &init.name);
1309 ds1307->clks[i].init = &init;
1310
1311 onecell->clks[i] = devm_clk_register(ds1307->dev,
1312 &ds1307->clks[i]);
1313 if (IS_ERR(onecell->clks[i]))
1314 return PTR_ERR(onecell->clks[i]);
1315 }
1316
1317 if (!node)
1318 return 0;
1319
1320 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1321
1322 return 0;
1323}
1324
1325static void ds1307_clks_register(struct ds1307 *ds1307)
1326{
1327 int ret;
1328
1329 if (ds1307->type != ds_3231)
1330 return;
1331
1332 ret = ds3231_clks_register(ds1307);
1333 if (ret) {
1334 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1335 ret);
1336 }
1337}
1338
1339#else
1340
1341static void ds1307_clks_register(struct ds1307 *ds1307)
1342{
1343}
1344
1345#endif
1346
1347static const struct regmap_config regmap_config = {
1348 .reg_bits = 8,
1349 .val_bits = 8,
1350};
1351
1352static int ds1307_probe(struct i2c_client *client,
1353 const struct i2c_device_id *id)
1354{
1355 struct ds1307 *ds1307;
1356 int err = -ENODEV;
1357 int tmp, wday;
1358 const struct chip_desc *chip;
1359 bool want_irq;
1360 bool ds1307_can_wakeup_device = false;
1361 unsigned char regs[8];
1362 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1363 struct rtc_time tm;
1364 unsigned long timestamp;
1365 u8 trickle_charger_setup = 0;
1366
1367 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1368 if (!ds1307)
1369 return -ENOMEM;
1370
1371 dev_set_drvdata(&client->dev, ds1307);
1372 ds1307->dev = &client->dev;
1373 ds1307->name = client->name;
1374
1375 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config);
1376 if (IS_ERR(ds1307->regmap)) {
1377 dev_err(ds1307->dev, "regmap allocation failed\n");
1378 return PTR_ERR(ds1307->regmap);
1379 }
1380
1381 i2c_set_clientdata(client, ds1307);
1382
1383 if (client->dev.of_node) {
1384 ds1307->type = (enum ds_type)
1385 of_device_get_match_data(&client->dev);
1386 chip = &chips[ds1307->type];
1387 } else if (id) {
1388 chip = &chips[id->driver_data];
1389 ds1307->type = id->driver_data;
1390 } else {
1391 const struct acpi_device_id *acpi_id;
1392
1393 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1394 ds1307->dev);
1395 if (!acpi_id)
1396 return -ENODEV;
1397 chip = &chips[acpi_id->driver_data];
1398 ds1307->type = acpi_id->driver_data;
1399 }
1400
1401 want_irq = client->irq > 0 && chip->alarm;
1402
1403 if (!pdata)
1404 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1405 else if (pdata->trickle_charger_setup)
1406 trickle_charger_setup = pdata->trickle_charger_setup;
1407
1408 if (trickle_charger_setup && chip->trickle_charger_reg) {
1409 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
1410 dev_dbg(ds1307->dev,
1411 "writing trickle charger info 0x%x to 0x%x\n",
1412 trickle_charger_setup, chip->trickle_charger_reg);
1413 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1414 trickle_charger_setup);
1415 }
1416
1417#ifdef CONFIG_OF
1418
1419
1420
1421
1422
1423
1424
1425
1426 if (chip->alarm && of_property_read_bool(client->dev.of_node,
1427 "wakeup-source"))
1428 ds1307_can_wakeup_device = true;
1429#endif
1430
1431 switch (ds1307->type) {
1432 case ds_1337:
1433 case ds_1339:
1434 case ds_1341:
1435 case ds_3231:
1436
1437 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1438 regs, 2);
1439 if (err) {
1440 dev_dbg(ds1307->dev, "read error %d\n", err);
1441 goto exit;
1442 }
1443
1444
1445 if (regs[0] & DS1337_BIT_nEOSC)
1446 regs[0] &= ~DS1337_BIT_nEOSC;
1447
1448
1449
1450
1451
1452
1453
1454 if (want_irq || ds1307_can_wakeup_device) {
1455 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1456 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1457 }
1458
1459 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1460 regs[0]);
1461
1462
1463 if (regs[1] & DS1337_BIT_OSF) {
1464 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1465 regs[1] & ~DS1337_BIT_OSF);
1466 dev_warn(ds1307->dev, "SET TIME!\n");
1467 }
1468 break;
1469
1470 case rx_8025:
1471 err = regmap_bulk_read(ds1307->regmap,
1472 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1473 if (err) {
1474 dev_dbg(ds1307->dev, "read error %d\n", err);
1475 goto exit;
1476 }
1477
1478
1479 if (!(regs[1] & RX8025_BIT_XST)) {
1480 regs[1] |= RX8025_BIT_XST;
1481 regmap_write(ds1307->regmap,
1482 RX8025_REG_CTRL2 << 4 | 0x08,
1483 regs[1]);
1484 dev_warn(ds1307->dev,
1485 "oscillator stop detected - SET TIME!\n");
1486 }
1487
1488 if (regs[1] & RX8025_BIT_PON) {
1489 regs[1] &= ~RX8025_BIT_PON;
1490 regmap_write(ds1307->regmap,
1491 RX8025_REG_CTRL2 << 4 | 0x08,
1492 regs[1]);
1493 dev_warn(ds1307->dev, "power-on detected\n");
1494 }
1495
1496 if (regs[1] & RX8025_BIT_VDET) {
1497 regs[1] &= ~RX8025_BIT_VDET;
1498 regmap_write(ds1307->regmap,
1499 RX8025_REG_CTRL2 << 4 | 0x08,
1500 regs[1]);
1501 dev_warn(ds1307->dev, "voltage drop detected\n");
1502 }
1503
1504
1505 if (!(regs[0] & RX8025_BIT_2412)) {
1506 u8 hour;
1507
1508
1509 regmap_write(ds1307->regmap,
1510 RX8025_REG_CTRL1 << 4 | 0x08,
1511 regs[0] | RX8025_BIT_2412);
1512
1513 err = regmap_bulk_read(ds1307->regmap,
1514 RX8025_REG_CTRL1 << 4 | 0x08,
1515 regs, 2);
1516 if (err) {
1517 dev_dbg(ds1307->dev, "read error %d\n", err);
1518 goto exit;
1519 }
1520
1521
1522 hour = bcd2bin(regs[DS1307_REG_HOUR]);
1523 if (hour == 12)
1524 hour = 0;
1525 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1526 hour += 12;
1527
1528 regmap_write(ds1307->regmap,
1529 DS1307_REG_HOUR << 4 | 0x08, hour);
1530 }
1531 break;
1532 default:
1533 break;
1534 }
1535
1536read_rtc:
1537
1538 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1539 sizeof(regs));
1540 if (err) {
1541 dev_dbg(ds1307->dev, "read error %d\n", err);
1542 goto exit;
1543 }
1544
1545
1546
1547
1548
1549
1550 tmp = regs[DS1307_REG_SECS];
1551 switch (ds1307->type) {
1552 case ds_1307:
1553 case m41t0:
1554 case m41t00:
1555
1556 if (tmp & DS1307_BIT_CH) {
1557 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1558 dev_warn(ds1307->dev, "SET TIME!\n");
1559 goto read_rtc;
1560 }
1561 break;
1562 case ds_1308:
1563 case ds_1338:
1564
1565 if (tmp & DS1307_BIT_CH)
1566 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1567
1568
1569 if (regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
1570 regmap_write(ds1307->regmap, DS1307_REG_CONTROL,
1571 regs[DS1307_REG_CONTROL] &
1572 ~DS1338_BIT_OSF);
1573 dev_warn(ds1307->dev, "SET TIME!\n");
1574 goto read_rtc;
1575 }
1576 break;
1577 case ds_1340:
1578
1579 if (tmp & DS1340_BIT_nEOSC)
1580 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1581
1582 err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
1583 if (err) {
1584 dev_dbg(ds1307->dev, "read error %d\n", err);
1585 goto exit;
1586 }
1587
1588
1589 if (tmp & DS1340_BIT_OSF) {
1590 regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0);
1591 dev_warn(ds1307->dev, "SET TIME!\n");
1592 }
1593 break;
1594 case mcp794xx:
1595
1596 if (!(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1597 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1598 regs[DS1307_REG_WDAY] |
1599 MCP794XX_BIT_VBATEN);
1600 }
1601
1602
1603 if (!(tmp & MCP794XX_BIT_ST)) {
1604 regmap_write(ds1307->regmap, DS1307_REG_SECS,
1605 MCP794XX_BIT_ST);
1606 dev_warn(ds1307->dev, "SET TIME!\n");
1607 goto read_rtc;
1608 }
1609
1610 break;
1611 default:
1612 break;
1613 }
1614
1615 tmp = regs[DS1307_REG_HOUR];
1616 switch (ds1307->type) {
1617 case ds_1340:
1618 case m41t0:
1619 case m41t00:
1620
1621
1622
1623
1624 break;
1625 case rx_8025:
1626 break;
1627 default:
1628 if (!(tmp & DS1307_BIT_12HR))
1629 break;
1630
1631
1632
1633
1634
1635 tmp = bcd2bin(tmp & 0x1f);
1636 if (tmp == 12)
1637 tmp = 0;
1638 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1639 tmp += 12;
1640 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1641 bin2bcd(tmp));
1642 }
1643
1644
1645
1646
1647
1648 ds1307_get_time(ds1307->dev, &tm);
1649 wday = tm.tm_wday;
1650 timestamp = rtc_tm_to_time64(&tm);
1651 rtc_time64_to_tm(timestamp, &tm);
1652
1653
1654
1655
1656
1657
1658 if (wday != tm.tm_wday)
1659 regmap_update_bits(ds1307->regmap, MCP794XX_REG_WEEKDAY,
1660 MCP794XX_REG_WEEKDAY_WDAY_MASK,
1661 tm.tm_wday + 1);
1662
1663 if (want_irq || ds1307_can_wakeup_device) {
1664 device_set_wakeup_capable(ds1307->dev, true);
1665 set_bit(HAS_ALARM, &ds1307->flags);
1666 }
1667
1668 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1669 if (IS_ERR(ds1307->rtc))
1670 return PTR_ERR(ds1307->rtc);
1671
1672 if (ds1307_can_wakeup_device && !want_irq) {
1673 dev_info(ds1307->dev,
1674 "'wakeup-source' is set, request for an IRQ is disabled!\n");
1675
1676 ds1307->rtc->uie_unsupported = 1;
1677 }
1678
1679 if (want_irq) {
1680 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1681 chip->irq_handler ?: ds1307_irq,
1682 IRQF_SHARED | IRQF_ONESHOT,
1683 ds1307->name, ds1307);
1684 if (err) {
1685 client->irq = 0;
1686 device_set_wakeup_capable(ds1307->dev, false);
1687 clear_bit(HAS_ALARM, &ds1307->flags);
1688 dev_err(ds1307->dev, "unable to request IRQ!\n");
1689 } else {
1690 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1691 }
1692 }
1693
1694 if (chip->nvram_size) {
1695 ds1307->nvmem_cfg.name = "ds1307_nvram";
1696 ds1307->nvmem_cfg.word_size = 1;
1697 ds1307->nvmem_cfg.stride = 1;
1698 ds1307->nvmem_cfg.size = chip->nvram_size;
1699 ds1307->nvmem_cfg.reg_read = ds1307_nvram_read;
1700 ds1307->nvmem_cfg.reg_write = ds1307_nvram_write;
1701 ds1307->nvmem_cfg.priv = ds1307;
1702
1703 ds1307->rtc->nvmem_config = &ds1307->nvmem_cfg;
1704 ds1307->rtc->nvram_old_abi = true;
1705 }
1706
1707 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1708 err = rtc_register_device(ds1307->rtc);
1709 if (err)
1710 return err;
1711
1712 ds1307_hwmon_register(ds1307);
1713 ds1307_clks_register(ds1307);
1714
1715 return 0;
1716
1717exit:
1718 return err;
1719}
1720
1721static struct i2c_driver ds1307_driver = {
1722 .driver = {
1723 .name = "rtc-ds1307",
1724 .of_match_table = of_match_ptr(ds1307_of_match),
1725 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1726 },
1727 .probe = ds1307_probe,
1728 .id_table = ds1307_id,
1729};
1730
1731module_i2c_driver(ds1307_driver);
1732
1733MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1734MODULE_LICENSE("GPL");
1735
