LXR linux/drivers/staging/most/hdm-dim2/dim2

   1/*
   2 * dim2_reg.h - Definitions for registers of DIM2
   3 * (MediaLB, Device Interface Macro IP, OS62420)
   4 *
   5 * Copyright (C) 2015, Microchip Technology Germany II GmbH & Co. KG
   6 *
   7 * This program is distributed in the hope that it will be useful,
   8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10 * GNU General Public License for more details.
  11 *
  12 * This file is licensed under GPLv2.
  13 */
  14
  15#ifndef DIM2_OS62420_H
  16#define DIM2_OS62420_H
  17
  18#include <linux/types.h>
  19
  20struct dim2_regs {
  21        /* 0x00 */ u32 MLBC0;
  22        /* 0x01 */ u32 rsvd0[1];
  23        /* 0x02 */ u32 MLBPC0;
  24        /* 0x03 */ u32 MS0;
  25        /* 0x04 */ u32 rsvd1[1];
  26        /* 0x05 */ u32 MS1;
  27        /* 0x06 */ u32 rsvd2[2];
  28        /* 0x08 */ u32 MSS;
  29        /* 0x09 */ u32 MSD;
  30        /* 0x0A */ u32 rsvd3[1];
  31        /* 0x0B */ u32 MIEN;
  32        /* 0x0C */ u32 rsvd4[1];
  33        /* 0x0D */ u32 MLBPC2;
  34        /* 0x0E */ u32 MLBPC1;
  35        /* 0x0F */ u32 MLBC1;
  36        /* 0x10 */ u32 rsvd5[0x10];
  37        /* 0x20 */ u32 HCTL;
  38        /* 0x21 */ u32 rsvd6[1];
  39        /* 0x22 */ u32 HCMR0;
  40        /* 0x23 */ u32 HCMR1;
  41        /* 0x24 */ u32 HCER0;
  42        /* 0x25 */ u32 HCER1;
  43        /* 0x26 */ u32 HCBR0;
  44        /* 0x27 */ u32 HCBR1;
  45        /* 0x28 */ u32 rsvd7[8];
  46        /* 0x30 */ u32 MDAT0;
  47        /* 0x31 */ u32 MDAT1;
  48        /* 0x32 */ u32 MDAT2;
  49        /* 0x33 */ u32 MDAT3;
  50        /* 0x34 */ u32 MDWE0;
  51        /* 0x35 */ u32 MDWE1;
  52        /* 0x36 */ u32 MDWE2;
  53        /* 0x37 */ u32 MDWE3;
  54        /* 0x38 */ u32 MCTL;
  55        /* 0x39 */ u32 MADR;
  56        /* 0x3A */ u32 rsvd8[0xB6];
  57        /* 0xF0 */ u32 ACTL;
  58        /* 0xF1 */ u32 rsvd9[3];
  59        /* 0xF4 */ u32 ACSR0;
  60        /* 0xF5 */ u32 ACSR1;
  61        /* 0xF6 */ u32 ACMR0;
  62        /* 0xF7 */ u32 ACMR1;
  63};
  64
  65#define DIM2_MASK(n)  (~((~(u32)0) << (n)))
  66
  67enum {
  68        MLBC0_MLBLK_BIT = 7,
  69
  70        MLBC0_MLBPEN_BIT = 5,
  71
  72        MLBC0_MLBCLK_SHIFT = 2,
  73        MLBC0_MLBCLK_VAL_256FS = 0,
  74        MLBC0_MLBCLK_VAL_512FS = 1,
  75        MLBC0_MLBCLK_VAL_1024FS = 2,
  76        MLBC0_MLBCLK_VAL_2048FS = 3,
  77
  78        MLBC0_FCNT_SHIFT = 15,
  79        MLBC0_FCNT_MASK = 7,
  80        MLBC0_FCNT_MAX_VAL = 6,
  81
  82        MLBC0_MLBEN_BIT = 0,
  83
  84        MIEN_CTX_BREAK_BIT = 29,
  85        MIEN_CTX_PE_BIT = 28,
  86        MIEN_CTX_DONE_BIT = 27,
  87
  88        MIEN_CRX_BREAK_BIT = 26,
  89        MIEN_CRX_PE_BIT = 25,
  90        MIEN_CRX_DONE_BIT = 24,
  91
  92        MIEN_ATX_BREAK_BIT = 22,
  93        MIEN_ATX_PE_BIT = 21,
  94        MIEN_ATX_DONE_BIT = 20,
  95
  96        MIEN_ARX_BREAK_BIT = 19,
  97        MIEN_ARX_PE_BIT = 18,
  98        MIEN_ARX_DONE_BIT = 17,
  99
 100        MIEN_SYNC_PE_BIT = 16,
 101
 102        MIEN_ISOC_BUFO_BIT = 1,
 103        MIEN_ISOC_PE_BIT = 0,
 104
 105        MLBC1_NDA_SHIFT = 8,
 106        MLBC1_NDA_MASK = 0xFF,
 107
 108        MLBC1_CLKMERR_BIT = 7,
 109        MLBC1_LOCKERR_BIT = 6,
 110
 111        ACTL_DMA_MODE_BIT = 2,
 112        ACTL_DMA_MODE_VAL_DMA_MODE_0 = 0,
 113        ACTL_DMA_MODE_VAL_DMA_MODE_1 = 1,
 114        ACTL_SCE_BIT = 0,
 115
 116        HCTL_EN_BIT = 15
 117};
 118
 119enum {
 120        CDT0_RPC_SHIFT = 16 + 11,
 121        CDT0_RPC_MASK = DIM2_MASK(5),
 122
 123        CDT1_BS_ISOC_SHIFT = 0,
 124        CDT1_BS_ISOC_MASK = DIM2_MASK(9),
 125
 126        CDT3_BD_SHIFT = 0,
 127        CDT3_BD_MASK = DIM2_MASK(12),
 128        CDT3_BD_ISOC_MASK = DIM2_MASK(13),
 129        CDT3_BA_SHIFT = 16,
 130
 131        ADT0_CE_BIT = 15,
 132        ADT0_LE_BIT = 14,
 133        ADT0_PG_BIT = 13,
 134
 135        ADT1_RDY_BIT = 15,
 136        ADT1_DNE_BIT = 14,
 137        ADT1_ERR_BIT = 13,
 138        ADT1_PS_BIT = 12,
 139        ADT1_MEP_BIT = 11,
 140        ADT1_BD_SHIFT = 0,
 141        ADT1_CTRL_ASYNC_BD_MASK = DIM2_MASK(11),
 142        ADT1_ISOC_SYNC_BD_MASK = DIM2_MASK(13),
 143
 144        CAT_FCE_BIT = 14,
 145        CAT_MFE_BIT = 14,
 146
 147        CAT_MT_BIT = 13,
 148
 149        CAT_RNW_BIT = 12,
 150
 151        CAT_CE_BIT = 11,
 152
 153        CAT_CT_SHIFT = 8,
 154        CAT_CT_VAL_SYNC = 0,
 155        CAT_CT_VAL_CONTROL = 1,
 156        CAT_CT_VAL_ASYNC = 2,
 157        CAT_CT_VAL_ISOC = 3,
 158
 159        CAT_CL_SHIFT = 0,
 160        CAT_CL_MASK = DIM2_MASK(6)
 161};
 162
 163#endif  /* DIM2_OS62420_H */
 164