1
2#ifndef WILC_WLAN_H
3#define WILC_WLAN_H
4
5#include <linux/types.h>
6
7#define ISWILC1000(id) ((id & 0xfffff000) == 0x100000 ? 1 : 0)
8
9
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12
13
14#define DRIVER_HANDLER_SIZE 4
15#define MAX_MAC_HDR_LEN 26
16#define SUB_MSDU_HEADER_LENGTH 14
17#define SNAP_HDR_LEN 8
18#define ETHERNET_HDR_LEN 14
19#define WORD_ALIGNMENT_PAD 0
20
21#define ETH_ETHERNET_HDR_OFFSET (MAX_MAC_HDR_LEN + \
22 SUB_MSDU_HEADER_LENGTH + \
23 SNAP_HDR_LEN - \
24 ETHERNET_HDR_LEN + \
25 WORD_ALIGNMENT_PAD)
26
27#define HOST_HDR_OFFSET 4
28#define ETHERNET_HDR_LEN 14
29#define IP_HDR_LEN 20
30#define IP_HDR_OFFSET ETHERNET_HDR_LEN
31#define UDP_HDR_OFFSET (IP_HDR_LEN + IP_HDR_OFFSET)
32#define UDP_HDR_LEN 8
33#define UDP_DATA_OFFSET (UDP_HDR_OFFSET + UDP_HDR_LEN)
34#define ETH_CONFIG_PKT_HDR_LEN UDP_DATA_OFFSET
35
36#define ETH_CONFIG_PKT_HDR_OFFSET (ETH_ETHERNET_HDR_OFFSET + \
37 ETH_CONFIG_PKT_HDR_LEN)
38
39
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42
43
44#define WILC_PERIPH_REG_BASE 0x1000
45#define WILC_CHANGING_VIR_IF 0x108c
46#define WILC_CHIPID WILC_PERIPH_REG_BASE
47#define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400)
48#define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408)
49#define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c)
50#define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70)
51#define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74)
52#define WILC_HOST_VMM_CTL (WILC_PERIPH_REG_BASE + 0x78)
53#define WILC_HOST_RX_CTRL (WILC_PERIPH_REG_BASE + 0x80)
54#define WILC_HOST_RX_EXTRA_SIZE (WILC_PERIPH_REG_BASE + 0x84)
55#define WILC_HOST_TX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x88)
56#define WILC_MISC (WILC_PERIPH_REG_BASE + 0x428)
57#define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00)
58#define WILC_INTR_ENABLE WILC_INTR_REG_BASE
59#define WILC_INTR2_ENABLE (WILC_INTR_REG_BASE + 4)
60
61#define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10)
62#define WILC_INTR_TYPE (WILC_INTR_REG_BASE + 0x20)
63#define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30)
64#define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40)
65
66#define WILC_VMM_TBL_SIZE 64
67#define WILC_VMM_TX_TBL_BASE 0x150400
68#define WILC_VMM_RX_TBL_BASE 0x150500
69
70#define WILC_VMM_BASE 0x150000
71#define WILC_VMM_CORE_CTL WILC_VMM_BASE
72#define WILC_VMM_TBL_CTL (WILC_VMM_BASE + 0x4)
73#define WILC_VMM_TBL_ENTRY (WILC_VMM_BASE + 0x8)
74#define WILC_VMM_TBL0_SIZE (WILC_VMM_BASE + 0xc)
75#define WILC_VMM_TO_HOST_SIZE (WILC_VMM_BASE + 0x10)
76#define WILC_VMM_CORE_CFG (WILC_VMM_BASE + 0x14)
77#define WILC_VMM_TBL_ACTIVE (WILC_VMM_BASE + 040)
78#define WILC_VMM_TBL_STATUS (WILC_VMM_BASE + 0x44)
79
80#define WILC_SPI_REG_BASE 0xe800
81#define WILC_SPI_CTL WILC_SPI_REG_BASE
82#define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4)
83#define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8)
84#define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc)
85#define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10)
86#define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20)
87#define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24)
88#define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c)
89
90#define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - \
91 WILC_SPI_REG_BASE)
92
93#define WILC_AHB_DATA_MEM_BASE 0x30000
94#define WILC_AHB_SHARE_MEM_BASE 0xd0000
95
96#define WILC_VMM_TBL_RX_SHADOW_BASE WILC_AHB_SHARE_MEM_BASE
97#define WILC_VMM_TBL_RX_SHADOW_SIZE 256
98
99#define WILC_GP_REG_0 0x149c
100#define WILC_GP_REG_1 0x14a0
101
102#define WILC_HAVE_SDIO_IRQ_GPIO BIT(0)
103#define WILC_HAVE_USE_PMU BIT(1)
104#define WILC_HAVE_SLEEP_CLK_SRC_RTC BIT(2)
105#define WILC_HAVE_SLEEP_CLK_SRC_XO BIT(3)
106#define WILC_HAVE_EXT_PA_INV_TX_RX BIT(4)
107#define WILC_HAVE_LEGACY_RF_SETTINGS BIT(5)
108#define WILC_HAVE_XTAL_24 BIT(6)
109#define WILC_HAVE_DISABLE_WILC_UART BIT(7)
110#define WILC_HAVE_USE_IRQ_AS_HOST_WAKE BIT(8)
111
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115
116
117#define WILC_CFG_PKT 1
118#define WILC_NET_PKT 0
119#define WILC_MGMT_PKT 2
120
121#define WILC_CFG_SET 1
122#define WILC_CFG_QUERY 0
123
124#define WILC_CFG_RSP 1
125#define WILC_CFG_RSP_STATUS 2
126#define WILC_CFG_RSP_SCAN 3
127
128#define WILC_PLL_TO_SDIO 4
129#define WILC_PLL_TO_SPI 2
130#define ABORT_INT BIT(31)
131
132#define LINUX_RX_SIZE (96 * 1024)
133#define LINUX_TX_SIZE (64 * 1024)
134
135#define MODALIAS "WILC_SPI"
136#define GPIO_NUM 0x44
137
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149
150
151#define IRG_FLAGS_OFFSET 16
152#define IRQ_DMA_WD_CNT_MASK ((1ul << IRG_FLAGS_OFFSET) - 1)
153#define INT_0 BIT(IRG_FLAGS_OFFSET)
154#define INT_1 BIT(IRG_FLAGS_OFFSET + 1)
155#define INT_2 BIT(IRG_FLAGS_OFFSET + 2)
156#define INT_3 BIT(IRG_FLAGS_OFFSET + 3)
157#define INT_4 BIT(IRG_FLAGS_OFFSET + 4)
158#define INT_5 BIT(IRG_FLAGS_OFFSET + 5)
159#define MAX_NUM_INT 6
160
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173
174#define CLR_INT0 BIT(0)
175#define CLR_INT1 BIT(1)
176#define CLR_INT2 BIT(2)
177#define CLR_INT3 BIT(3)
178#define CLR_INT4 BIT(4)
179#define CLR_INT5 BIT(5)
180#define SEL_VMM_TBL0 BIT(6)
181#define SEL_VMM_TBL1 BIT(7)
182#define EN_VMM BIT(8)
183
184#define DATA_INT_EXT INT_0
185#define PLL_INT_EXT INT_1
186#define SLEEP_INT_EXT INT_2
187#define ALL_INT_EXT (DATA_INT_EXT | PLL_INT_EXT | SLEEP_INT_EXT)
188#define NUM_INT_EXT 3
189
190#define DATA_INT_CLR CLR_INT0
191#define PLL_INT_CLR CLR_INT1
192#define SLEEP_INT_CLR CLR_INT2
193
194#define ENABLE_RX_VMM (SEL_VMM_TBL1 | EN_VMM)
195#define ENABLE_TX_VMM (SEL_VMM_TBL0 | EN_VMM)
196
197#define CFG_PKTS_TIMEOUT 2000
198
199
200
201
202
203typedef void (*wilc_debug_func)(u32, char *, ...);
204
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209
210
211struct txq_entry_t {
212 struct txq_entry_t *next;
213 struct txq_entry_t *prev;
214 int type;
215 int tcp_pending_ack_idx;
216 u8 *buffer;
217 int buffer_size;
218 void *priv;
219 int status;
220 void (*tx_complete_func)(void *, int);
221};
222
223struct rxq_entry_t {
224 struct rxq_entry_t *next;
225 u8 *buffer;
226 int buffer_size;
227};
228
229
230
231
232
233
234struct wilc;
235struct wilc_hif_func {
236 int (*hif_init)(struct wilc *, bool resume);
237 int (*hif_deinit)(struct wilc *);
238 int (*hif_read_reg)(struct wilc *, u32, u32 *);
239 int (*hif_write_reg)(struct wilc *, u32, u32);
240 int (*hif_block_rx)(struct wilc *, u32, u8 *, u32);
241 int (*hif_block_tx)(struct wilc *, u32, u8 *, u32);
242 int (*hif_read_int)(struct wilc *, u32 *);
243 int (*hif_clear_int_ext)(struct wilc *, u32);
244 int (*hif_read_size)(struct wilc *, u32 *);
245 int (*hif_block_tx_ext)(struct wilc *, u32, u8 *, u32);
246 int (*hif_block_rx_ext)(struct wilc *, u32, u8 *, u32);
247 int (*hif_sync_ext)(struct wilc *, int);
248 int (*enable_interrupt)(struct wilc *nic);
249 void (*disable_interrupt)(struct wilc *nic);
250};
251
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255
256
257
258#define MAX_CFG_FRAME_SIZE 1468
259
260struct wilc_cfg_frame {
261 u8 ether_header[14];
262 u8 ip_header[20];
263 u8 udp_header[8];
264 u8 wid_header[8];
265 u8 frame[MAX_CFG_FRAME_SIZE];
266};
267
268struct wilc_cfg_rsp {
269 int type;
270 u32 seq_no;
271};
272
273struct wilc;
274struct wilc_vif;
275
276int wilc_wlan_firmware_download(struct wilc *wilc, const u8 *buffer,
277 u32 buffer_size);
278int wilc_wlan_start(struct wilc *wilc);
279int wilc_wlan_stop(struct wilc *wilc);
280int wilc_wlan_txq_add_net_pkt(struct net_device *dev, void *priv, u8 *buffer,
281 u32 buffer_size, wilc_tx_complete_func_t func);
282int wilc_wlan_handle_txq(struct net_device *dev, u32 *txq_count);
283void wilc_handle_isr(struct wilc *wilc);
284void wilc_wlan_cleanup(struct net_device *dev);
285int wilc_wlan_cfg_set(struct wilc_vif *vif, int start, u16 wid, u8 *buffer,
286 u32 buffer_size, int commit, u32 drv_handler);
287int wilc_wlan_cfg_get(struct wilc_vif *vif, int start, u16 wid, int commit,
288 u32 drv_handler);
289int wilc_wlan_cfg_get_val(u16 wid, u8 *buffer, u32 buffer_size);
290int wilc_wlan_txq_add_mgmt_pkt(struct net_device *dev, void *priv, u8 *buffer,
291 u32 buffer_size, wilc_tx_complete_func_t func);
292void wilc_chip_sleep_manually(struct wilc *wilc);
293
294void wilc_enable_tcp_ack_filter(bool value);
295int wilc_wlan_get_num_conn_ifcs(struct wilc *wilc);
296int wilc_mac_xmit(struct sk_buff *skb, struct net_device *dev);
297
298void WILC_WFI_p2p_rx(struct net_device *dev, u8 *buff, u32 size);
299void host_wakeup_notify(struct wilc *wilc);
300void host_sleep_notify(struct wilc *wilc);
301extern bool wilc_enable_ps;
302void chip_allow_sleep(struct wilc *wilc);
303void chip_wakeup(struct wilc *wilc);
304int wilc_send_config_pkt(struct wilc_vif *vif, u8 mode, struct wid *wids,
305 u32 count, u32 drv);
306#endif
307
