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43#include <linux/clk.h>
44#include <linux/io.h>
45#include <linux/log2.h>
46#include <linux/module.h>
47#include <linux/platform_device.h>
48#include <linux/slab.h>
49#include <linux/watchdog.h>
50
51
52#define PDC_WDT_SOFT_RESET 0x00
53#define PDC_WDT_CONFIG 0x04
54 #define PDC_WDT_CONFIG_ENABLE BIT(31)
55 #define PDC_WDT_CONFIG_DELAY_MASK 0x1f
56
57#define PDC_WDT_TICKLE1 0x08
58#define PDC_WDT_TICKLE1_MAGIC 0xabcd1234
59#define PDC_WDT_TICKLE2 0x0c
60#define PDC_WDT_TICKLE2_MAGIC 0x4321dcba
61
62#define PDC_WDT_TICKLE_STATUS_MASK 0x7
63#define PDC_WDT_TICKLE_STATUS_SHIFT 0
64#define PDC_WDT_TICKLE_STATUS_HRESET 0x0
65#define PDC_WDT_TICKLE_STATUS_TIMEOUT 0x1
66#define PDC_WDT_TICKLE_STATUS_TICKLE 0x2
67#define PDC_WDT_TICKLE_STATUS_SRESET 0x3
68#define PDC_WDT_TICKLE_STATUS_USER 0x4
69
70
71#define PDC_WDT_MIN_TIMEOUT 1
72#define PDC_WDT_DEF_TIMEOUT 64
73
74static int heartbeat;
75module_param(heartbeat, int, 0);
76MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds "
77 "(default=" __MODULE_STRING(PDC_WDT_DEF_TIMEOUT) ")");
78
79static bool nowayout = WATCHDOG_NOWAYOUT;
80module_param(nowayout, bool, 0);
81MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
82 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
83
84struct pdc_wdt_dev {
85 struct watchdog_device wdt_dev;
86 struct clk *wdt_clk;
87 struct clk *sys_clk;
88 void __iomem *base;
89};
90
91static int pdc_wdt_keepalive(struct watchdog_device *wdt_dev)
92{
93 struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
94
95 writel(PDC_WDT_TICKLE1_MAGIC, wdt->base + PDC_WDT_TICKLE1);
96 writel(PDC_WDT_TICKLE2_MAGIC, wdt->base + PDC_WDT_TICKLE2);
97
98 return 0;
99}
100
101static int pdc_wdt_stop(struct watchdog_device *wdt_dev)
102{
103 unsigned int val;
104 struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
105
106 val = readl(wdt->base + PDC_WDT_CONFIG);
107 val &= ~PDC_WDT_CONFIG_ENABLE;
108 writel(val, wdt->base + PDC_WDT_CONFIG);
109
110
111 pdc_wdt_keepalive(wdt_dev);
112
113 return 0;
114}
115
116static void __pdc_wdt_set_timeout(struct pdc_wdt_dev *wdt)
117{
118 unsigned long clk_rate = clk_get_rate(wdt->wdt_clk);
119 unsigned int val;
120
121 val = readl(wdt->base + PDC_WDT_CONFIG) & ~PDC_WDT_CONFIG_DELAY_MASK;
122 val |= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1;
123 writel(val, wdt->base + PDC_WDT_CONFIG);
124}
125
126static int pdc_wdt_set_timeout(struct watchdog_device *wdt_dev,
127 unsigned int new_timeout)
128{
129 struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
130
131 wdt->wdt_dev.timeout = new_timeout;
132
133 __pdc_wdt_set_timeout(wdt);
134
135 return 0;
136}
137
138
139static int pdc_wdt_start(struct watchdog_device *wdt_dev)
140{
141 unsigned int val;
142 struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
143
144 __pdc_wdt_set_timeout(wdt);
145
146 val = readl(wdt->base + PDC_WDT_CONFIG);
147 val |= PDC_WDT_CONFIG_ENABLE;
148 writel(val, wdt->base + PDC_WDT_CONFIG);
149
150 return 0;
151}
152
153static int pdc_wdt_restart(struct watchdog_device *wdt_dev,
154 unsigned long action, void *data)
155{
156 struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
157
158
159 writel(0x1, wdt->base + PDC_WDT_SOFT_RESET);
160
161 return 0;
162}
163
164static const struct watchdog_info pdc_wdt_info = {
165 .identity = "IMG PDC Watchdog",
166 .options = WDIOF_SETTIMEOUT |
167 WDIOF_KEEPALIVEPING |
168 WDIOF_MAGICCLOSE,
169};
170
171static const struct watchdog_ops pdc_wdt_ops = {
172 .owner = THIS_MODULE,
173 .start = pdc_wdt_start,
174 .stop = pdc_wdt_stop,
175 .ping = pdc_wdt_keepalive,
176 .set_timeout = pdc_wdt_set_timeout,
177 .restart = pdc_wdt_restart,
178};
179
180static int pdc_wdt_probe(struct platform_device *pdev)
181{
182 u64 div;
183 int ret, val;
184 unsigned long clk_rate;
185 struct resource *res;
186 struct pdc_wdt_dev *pdc_wdt;
187
188 pdc_wdt = devm_kzalloc(&pdev->dev, sizeof(*pdc_wdt), GFP_KERNEL);
189 if (!pdc_wdt)
190 return -ENOMEM;
191
192 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
193 pdc_wdt->base = devm_ioremap_resource(&pdev->dev, res);
194 if (IS_ERR(pdc_wdt->base))
195 return PTR_ERR(pdc_wdt->base);
196
197 pdc_wdt->sys_clk = devm_clk_get(&pdev->dev, "sys");
198 if (IS_ERR(pdc_wdt->sys_clk)) {
199 dev_err(&pdev->dev, "failed to get the sys clock\n");
200 return PTR_ERR(pdc_wdt->sys_clk);
201 }
202
203 pdc_wdt->wdt_clk = devm_clk_get(&pdev->dev, "wdt");
204 if (IS_ERR(pdc_wdt->wdt_clk)) {
205 dev_err(&pdev->dev, "failed to get the wdt clock\n");
206 return PTR_ERR(pdc_wdt->wdt_clk);
207 }
208
209 ret = clk_prepare_enable(pdc_wdt->sys_clk);
210 if (ret) {
211 dev_err(&pdev->dev, "could not prepare or enable sys clock\n");
212 return ret;
213 }
214
215 ret = clk_prepare_enable(pdc_wdt->wdt_clk);
216 if (ret) {
217 dev_err(&pdev->dev, "could not prepare or enable wdt clock\n");
218 goto disable_sys_clk;
219 }
220
221
222 clk_rate = clk_get_rate(pdc_wdt->wdt_clk);
223 if (clk_rate == 0) {
224 dev_err(&pdev->dev, "failed to get clock rate\n");
225 ret = -EINVAL;
226 goto disable_wdt_clk;
227 }
228
229 if (order_base_2(clk_rate) > PDC_WDT_CONFIG_DELAY_MASK + 1) {
230 dev_err(&pdev->dev, "invalid clock rate\n");
231 ret = -EINVAL;
232 goto disable_wdt_clk;
233 }
234
235 if (order_base_2(clk_rate) == 0)
236 pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT + 1;
237 else
238 pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT;
239
240 pdc_wdt->wdt_dev.info = &pdc_wdt_info;
241 pdc_wdt->wdt_dev.ops = &pdc_wdt_ops;
242
243 div = 1ULL << (PDC_WDT_CONFIG_DELAY_MASK + 1);
244 do_div(div, clk_rate);
245 pdc_wdt->wdt_dev.max_timeout = div;
246 pdc_wdt->wdt_dev.timeout = PDC_WDT_DEF_TIMEOUT;
247 pdc_wdt->wdt_dev.parent = &pdev->dev;
248 watchdog_set_drvdata(&pdc_wdt->wdt_dev, pdc_wdt);
249
250 watchdog_init_timeout(&pdc_wdt->wdt_dev, heartbeat, &pdev->dev);
251
252 pdc_wdt_stop(&pdc_wdt->wdt_dev);
253
254
255 val = readl(pdc_wdt->base + PDC_WDT_TICKLE1);
256 val = (val & PDC_WDT_TICKLE_STATUS_MASK) >> PDC_WDT_TICKLE_STATUS_SHIFT;
257 switch (val) {
258 case PDC_WDT_TICKLE_STATUS_TICKLE:
259 case PDC_WDT_TICKLE_STATUS_TIMEOUT:
260 pdc_wdt->wdt_dev.bootstatus |= WDIOF_CARDRESET;
261 dev_info(&pdev->dev,
262 "watchdog module last reset due to timeout\n");
263 break;
264 case PDC_WDT_TICKLE_STATUS_HRESET:
265 dev_info(&pdev->dev,
266 "watchdog module last reset due to hard reset\n");
267 break;
268 case PDC_WDT_TICKLE_STATUS_SRESET:
269 dev_info(&pdev->dev,
270 "watchdog module last reset due to soft reset\n");
271 break;
272 case PDC_WDT_TICKLE_STATUS_USER:
273 dev_info(&pdev->dev,
274 "watchdog module last reset due to user reset\n");
275 break;
276 default:
277 dev_info(&pdev->dev,
278 "contains an illegal status code (%08x)\n", val);
279 break;
280 }
281
282 watchdog_set_nowayout(&pdc_wdt->wdt_dev, nowayout);
283 watchdog_set_restart_priority(&pdc_wdt->wdt_dev, 128);
284
285 platform_set_drvdata(pdev, pdc_wdt);
286
287 ret = watchdog_register_device(&pdc_wdt->wdt_dev);
288 if (ret)
289 goto disable_wdt_clk;
290
291 return 0;
292
293disable_wdt_clk:
294 clk_disable_unprepare(pdc_wdt->wdt_clk);
295disable_sys_clk:
296 clk_disable_unprepare(pdc_wdt->sys_clk);
297 return ret;
298}
299
300static void pdc_wdt_shutdown(struct platform_device *pdev)
301{
302 struct pdc_wdt_dev *pdc_wdt = platform_get_drvdata(pdev);
303
304 pdc_wdt_stop(&pdc_wdt->wdt_dev);
305}
306
307static int pdc_wdt_remove(struct platform_device *pdev)
308{
309 struct pdc_wdt_dev *pdc_wdt = platform_get_drvdata(pdev);
310
311 pdc_wdt_stop(&pdc_wdt->wdt_dev);
312 watchdog_unregister_device(&pdc_wdt->wdt_dev);
313 clk_disable_unprepare(pdc_wdt->wdt_clk);
314 clk_disable_unprepare(pdc_wdt->sys_clk);
315
316 return 0;
317}
318
319static const struct of_device_id pdc_wdt_match[] = {
320 { .compatible = "img,pdc-wdt" },
321 {}
322};
323MODULE_DEVICE_TABLE(of, pdc_wdt_match);
324
325static struct platform_driver pdc_wdt_driver = {
326 .driver = {
327 .name = "imgpdc-wdt",
328 .of_match_table = pdc_wdt_match,
329 },
330 .probe = pdc_wdt_probe,
331 .remove = pdc_wdt_remove,
332 .shutdown = pdc_wdt_shutdown,
333};
334module_platform_driver(pdc_wdt_driver);
335
336MODULE_AUTHOR("Jude Abraham <Jude.Abraham@imgtec.com>");
337MODULE_AUTHOR("Naidu Tellapati <Naidu.Tellapati@imgtec.com>");
338MODULE_DESCRIPTION("Imagination Technologies PDC Watchdog Timer Driver");
339MODULE_LICENSE("GPL v2");
340
