1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/types.h>
27#include <linux/i2c.h>
28#include <linux/delay.h>
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45#define DP_AUX_MAX_PAYLOAD_BYTES 16
46
47#define DP_AUX_I2C_WRITE 0x0
48#define DP_AUX_I2C_READ 0x1
49#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
50#define DP_AUX_I2C_MOT 0x4
51#define DP_AUX_NATIVE_WRITE 0x8
52#define DP_AUX_NATIVE_READ 0x9
53
54#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
55#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
56#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
57#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
58
59#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
60#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
61#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
62#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
63
64
65
66#define DP_DPCD_REV 0x000
67
68#define DP_MAX_LINK_RATE 0x001
69
70#define DP_MAX_LANE_COUNT 0x002
71# define DP_MAX_LANE_COUNT_MASK 0x1f
72# define DP_TPS3_SUPPORTED (1 << 6)
73# define DP_ENHANCED_FRAME_CAP (1 << 7)
74
75#define DP_MAX_DOWNSPREAD 0x003
76# define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
77# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
78
79#define DP_NORP 0x004
80
81#define DP_DOWNSTREAMPORT_PRESENT 0x005
82# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
83# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
84# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
85# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
86# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
87# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
88# define DP_FORMAT_CONVERSION (1 << 3)
89# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4)
90
91#define DP_MAIN_LINK_CHANNEL_CODING 0x006
92
93#define DP_DOWN_STREAM_PORT_COUNT 0x007
94# define DP_PORT_COUNT_MASK 0x0f
95# define DP_MSA_TIMING_PAR_IGNORED (1 << 6)
96# define DP_OUI_SUPPORT (1 << 7)
97
98#define DP_RECEIVE_PORT_0_CAP_0 0x008
99# define DP_LOCAL_EDID_PRESENT (1 << 1)
100# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
101
102#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
103
104#define DP_RECEIVE_PORT_1_CAP_0 0x00a
105#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
106
107#define DP_I2C_SPEED_CAP 0x00c
108# define DP_I2C_SPEED_1K 0x01
109# define DP_I2C_SPEED_5K 0x02
110# define DP_I2C_SPEED_10K 0x04
111# define DP_I2C_SPEED_100K 0x08
112# define DP_I2C_SPEED_400K 0x10
113# define DP_I2C_SPEED_1M 0x20
114
115#define DP_EDP_CONFIGURATION_CAP 0x00d
116# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
117# define DP_FRAMING_CHANGE_CAP (1 << 1)
118# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3)
119
120#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
121
122#define DP_ADAPTER_CAP 0x00f
123# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
124# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
125
126#define DP_SUPPORTED_LINK_RATES 0x010
127# define DP_MAX_SUPPORTED_RATES 8
128
129
130#define DP_FAUX_CAP 0x020
131# define DP_FAUX_CAP_1 (1 << 0)
132
133#define DP_MSTM_CAP 0x021
134# define DP_MST_CAP (1 << 0)
135
136#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022
137
138
139#define DP_AV_GRANULARITY 0x023
140# define DP_AG_FACTOR_MASK (0xf << 0)
141# define DP_AG_FACTOR_3MS (0 << 0)
142# define DP_AG_FACTOR_2MS (1 << 0)
143# define DP_AG_FACTOR_1MS (2 << 0)
144# define DP_AG_FACTOR_500US (3 << 0)
145# define DP_AG_FACTOR_200US (4 << 0)
146# define DP_AG_FACTOR_100US (5 << 0)
147# define DP_AG_FACTOR_10US (6 << 0)
148# define DP_AG_FACTOR_1US (7 << 0)
149# define DP_VG_FACTOR_MASK (0xf << 4)
150# define DP_VG_FACTOR_3MS (0 << 4)
151# define DP_VG_FACTOR_2MS (1 << 4)
152# define DP_VG_FACTOR_1MS (2 << 4)
153# define DP_VG_FACTOR_500US (3 << 4)
154# define DP_VG_FACTOR_200US (4 << 4)
155# define DP_VG_FACTOR_100US (5 << 4)
156
157#define DP_AUD_DEC_LAT0 0x024
158#define DP_AUD_DEC_LAT1 0x025
159
160#define DP_AUD_PP_LAT0 0x026
161#define DP_AUD_PP_LAT1 0x027
162
163#define DP_VID_INTER_LAT 0x028
164
165#define DP_VID_PROG_LAT 0x029
166
167#define DP_REP_LAT 0x02a
168
169#define DP_AUD_DEL_INS0 0x02b
170#define DP_AUD_DEL_INS1 0x02c
171#define DP_AUD_DEL_INS2 0x02d
172
173
174#define DP_RECEIVER_ALPM_CAP 0x02e
175# define DP_ALPM_CAP (1 << 0)
176
177#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f
178# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
179
180#define DP_GUID 0x030
181
182#define DP_DSC_SUPPORT 0x060
183# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
184
185#define DP_DSC_REV 0x061
186# define DP_DSC_MAJOR_MASK (0xf << 0)
187# define DP_DSC_MINOR_MASK (0xf << 4)
188# define DP_DSC_MAJOR_SHIFT 0
189# define DP_DSC_MINOR_SHIFT 4
190
191#define DP_DSC_RC_BUF_BLK_SIZE 0x062
192# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
193# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
194# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
195# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
196
197#define DP_DSC_RC_BUF_SIZE 0x063
198
199#define DP_DSC_SLICE_CAP_1 0x064
200# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
201# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
202# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
203# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
204# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
205# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
206# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
207
208#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
209# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
210# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
211# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
212# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
213# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
214# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
215# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
216# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
217# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
218# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
219
220#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
221# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
222
223#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067
224
225#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068
226
227#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
228# define DP_DSC_RGB (1 << 0)
229# define DP_DSC_YCbCr444 (1 << 1)
230# define DP_DSC_YCbCr422_Simple (1 << 2)
231# define DP_DSC_YCbCr422_Native (1 << 3)
232# define DP_DSC_YCbCr420_Native (1 << 4)
233
234#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
235# define DP_DSC_8_BPC (1 << 1)
236# define DP_DSC_10_BPC (1 << 2)
237# define DP_DSC_12_BPC (1 << 3)
238
239#define DP_DSC_PEAK_THROUGHPUT 0x06B
240# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
241# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
242# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
243# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
244# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
245# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
246# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
247# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
248# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
249# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
250# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
251# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
252# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
253# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
254# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
255# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
256# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
257# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
258# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
259# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
260# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
261# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
262# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
263# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
264# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
265# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
266# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
267# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
268# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
269# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
270# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
271# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
272
273#define DP_DSC_MAX_SLICE_WIDTH 0x06C
274
275#define DP_DSC_SLICE_CAP_2 0x06D
276# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
277# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
278# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
279
280#define DP_DSC_BITS_PER_PIXEL_INC 0x06F
281# define DP_DSC_BITS_PER_PIXEL_1_16 0x0
282# define DP_DSC_BITS_PER_PIXEL_1_8 0x1
283# define DP_DSC_BITS_PER_PIXEL_1_4 0x2
284# define DP_DSC_BITS_PER_PIXEL_1_2 0x3
285# define DP_DSC_BITS_PER_PIXEL_1 0x4
286
287#define DP_PSR_SUPPORT 0x070
288# define DP_PSR_IS_SUPPORTED 1
289# define DP_PSR2_IS_SUPPORTED 2
290
291#define DP_PSR_CAPS 0x071
292# define DP_PSR_NO_TRAIN_ON_EXIT 1
293# define DP_PSR_SETUP_TIME_330 (0 << 1)
294# define DP_PSR_SETUP_TIME_275 (1 << 1)
295# define DP_PSR_SETUP_TIME_220 (2 << 1)
296# define DP_PSR_SETUP_TIME_165 (3 << 1)
297# define DP_PSR_SETUP_TIME_110 (4 << 1)
298# define DP_PSR_SETUP_TIME_55 (5 << 1)
299# define DP_PSR_SETUP_TIME_0 (6 << 1)
300# define DP_PSR_SETUP_TIME_MASK (7 << 1)
301# define DP_PSR_SETUP_TIME_SHIFT 1
302# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4)
303# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5)
304
305
306
307
308
309
310
311
312
313#define DP_DOWNSTREAM_PORT_0 0x80
314# define DP_DS_PORT_TYPE_MASK (7 << 0)
315# define DP_DS_PORT_TYPE_DP 0
316# define DP_DS_PORT_TYPE_VGA 1
317# define DP_DS_PORT_TYPE_DVI 2
318# define DP_DS_PORT_TYPE_HDMI 3
319# define DP_DS_PORT_TYPE_NON_EDID 4
320# define DP_DS_PORT_TYPE_DP_DUALMODE 5
321# define DP_DS_PORT_TYPE_WIRELESS 6
322# define DP_DS_PORT_HPD (1 << 3)
323
324
325# define DP_DS_MAX_BPC_MASK (3 << 0)
326# define DP_DS_8BPC 0
327# define DP_DS_10BPC 1
328# define DP_DS_12BPC 2
329# define DP_DS_16BPC 3
330
331
332#define DP_LINK_BW_SET 0x100
333# define DP_LINK_RATE_TABLE 0x00
334# define DP_LINK_BW_1_62 0x06
335# define DP_LINK_BW_2_7 0x0a
336# define DP_LINK_BW_5_4 0x14
337
338#define DP_LANE_COUNT_SET 0x101
339# define DP_LANE_COUNT_MASK 0x0f
340# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
341
342#define DP_TRAINING_PATTERN_SET 0x102
343# define DP_TRAINING_PATTERN_DISABLE 0
344# define DP_TRAINING_PATTERN_1 1
345# define DP_TRAINING_PATTERN_2 2
346# define DP_TRAINING_PATTERN_3 3
347# define DP_TRAINING_PATTERN_MASK 0x3
348
349
350# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
351# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
352# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
353# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
354# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
355
356# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
357# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
358
359# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
360# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
361# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
362# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
363
364#define DP_TRAINING_LANE0_SET 0x103
365#define DP_TRAINING_LANE1_SET 0x104
366#define DP_TRAINING_LANE2_SET 0x105
367#define DP_TRAINING_LANE3_SET 0x106
368
369# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
370# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
371# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
372# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
373# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
374# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
375# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
376
377# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
378# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
379# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
380# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
381# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
382
383# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
384# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
385
386#define DP_DOWNSPREAD_CTRL 0x107
387# define DP_SPREAD_AMP_0_5 (1 << 4)
388# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7)
389
390#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
391# define DP_SET_ANSI_8B10B (1 << 0)
392
393#define DP_I2C_SPEED_CONTROL_STATUS 0x109
394
395
396#define DP_EDP_CONFIGURATION_SET 0x10a
397# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
398# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
399# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
400
401#define DP_LINK_QUAL_LANE0_SET 0x10b
402#define DP_LINK_QUAL_LANE1_SET 0x10c
403#define DP_LINK_QUAL_LANE2_SET 0x10d
404#define DP_LINK_QUAL_LANE3_SET 0x10e
405# define DP_LINK_QUAL_PATTERN_DISABLE 0
406# define DP_LINK_QUAL_PATTERN_D10_2 1
407# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
408# define DP_LINK_QUAL_PATTERN_PRBS7 3
409# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
410# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
411# define DP_LINK_QUAL_PATTERN_MASK 7
412
413#define DP_TRAINING_LANE0_1_SET2 0x10f
414#define DP_TRAINING_LANE2_3_SET2 0x110
415# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
416# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
417# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
418# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
419
420#define DP_MSTM_CTRL 0x111
421# define DP_MST_EN (1 << 0)
422# define DP_UP_REQ_EN (1 << 1)
423# define DP_UPSTREAM_IS_SRC (1 << 2)
424
425#define DP_AUDIO_DELAY0 0x112
426#define DP_AUDIO_DELAY1 0x113
427#define DP_AUDIO_DELAY2 0x114
428
429#define DP_LINK_RATE_SET 0x115
430# define DP_LINK_RATE_SET_SHIFT 0
431# define DP_LINK_RATE_SET_MASK (7 << 0)
432
433#define DP_RECEIVER_ALPM_CONFIG 0x116
434# define DP_ALPM_ENABLE (1 << 0)
435# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
436
437#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117
438# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
439# define DP_IRQ_HPD_ENABLE (1 << 1)
440
441#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118
442# define DP_PWR_NOT_NEEDED (1 << 0)
443
444#define DP_AUX_FRAME_SYNC_VALUE 0x15c
445# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
446
447#define DP_DSC_ENABLE 0x160
448
449#define DP_PSR_EN_CFG 0x170
450# define DP_PSR_ENABLE (1 << 0)
451# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
452# define DP_PSR_CRC_VERIFICATION (1 << 2)
453# define DP_PSR_FRAME_CAPTURE (1 << 3)
454# define DP_PSR_SELECTIVE_UPDATE (1 << 4)
455# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
456
457#define DP_ADAPTER_CTRL 0x1a0
458# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
459
460#define DP_BRANCH_DEVICE_CTRL 0x1a1
461# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
462
463#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
464#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
465#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
466
467#define DP_SINK_COUNT 0x200
468
469# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
470# define DP_SINK_CP_READY (1 << 6)
471
472#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
473# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
474# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
475# define DP_CP_IRQ (1 << 2)
476# define DP_MCCS_IRQ (1 << 3)
477# define DP_DOWN_REP_MSG_RDY (1 << 4)
478# define DP_UP_REQ_MSG_RDY (1 << 5)
479# define DP_SINK_SPECIFIC_IRQ (1 << 6)
480
481#define DP_LANE0_1_STATUS 0x202
482#define DP_LANE2_3_STATUS 0x203
483# define DP_LANE_CR_DONE (1 << 0)
484# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
485# define DP_LANE_SYMBOL_LOCKED (1 << 2)
486
487#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
488 DP_LANE_CHANNEL_EQ_DONE | \
489 DP_LANE_SYMBOL_LOCKED)
490
491#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
492
493#define DP_INTERLANE_ALIGN_DONE (1 << 0)
494#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
495#define DP_LINK_STATUS_UPDATED (1 << 7)
496
497#define DP_SINK_STATUS 0x205
498
499#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
500#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
501
502#define DP_ADJUST_REQUEST_LANE0_1 0x206
503#define DP_ADJUST_REQUEST_LANE2_3 0x207
504# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
505# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
506# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
507# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
508# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
509# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
510# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
511# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
512
513#define DP_TEST_REQUEST 0x218
514# define DP_TEST_LINK_TRAINING (1 << 0)
515# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
516# define DP_TEST_LINK_EDID_READ (1 << 2)
517# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3)
518# define DP_TEST_LINK_FAUX_PATTERN (1 << 4)
519
520#define DP_TEST_LINK_RATE 0x219
521# define DP_LINK_RATE_162 (0x6)
522# define DP_LINK_RATE_27 (0xa)
523
524#define DP_TEST_LANE_COUNT 0x220
525
526#define DP_TEST_PATTERN 0x221
527# define DP_NO_TEST_PATTERN 0x0
528# define DP_COLOR_RAMP 0x1
529# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
530# define DP_COLOR_SQUARE 0x3
531
532#define DP_TEST_H_TOTAL_HI 0x222
533#define DP_TEST_H_TOTAL_LO 0x223
534
535#define DP_TEST_V_TOTAL_HI 0x224
536#define DP_TEST_V_TOTAL_LO 0x225
537
538#define DP_TEST_H_START_HI 0x226
539#define DP_TEST_H_START_LO 0x227
540
541#define DP_TEST_V_START_HI 0x228
542#define DP_TEST_V_START_LO 0x229
543
544#define DP_TEST_HSYNC_HI 0x22A
545# define DP_TEST_HSYNC_POLARITY (1 << 7)
546# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
547#define DP_TEST_HSYNC_WIDTH_LO 0x22B
548
549#define DP_TEST_VSYNC_HI 0x22C
550# define DP_TEST_VSYNC_POLARITY (1 << 7)
551# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
552#define DP_TEST_VSYNC_WIDTH_LO 0x22D
553
554#define DP_TEST_H_WIDTH_HI 0x22E
555#define DP_TEST_H_WIDTH_LO 0x22F
556
557#define DP_TEST_V_HEIGHT_HI 0x230
558#define DP_TEST_V_HEIGHT_LO 0x231
559
560#define DP_TEST_MISC0 0x232
561# define DP_TEST_SYNC_CLOCK (1 << 0)
562# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
563# define DP_TEST_COLOR_FORMAT_SHIFT 1
564# define DP_COLOR_FORMAT_RGB (0 << 1)
565# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
566# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
567# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
568# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
569# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
570# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
571# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
572# define DP_TEST_BIT_DEPTH_SHIFT 5
573# define DP_TEST_BIT_DEPTH_6 (0 << 5)
574# define DP_TEST_BIT_DEPTH_8 (1 << 5)
575# define DP_TEST_BIT_DEPTH_10 (2 << 5)
576# define DP_TEST_BIT_DEPTH_12 (3 << 5)
577# define DP_TEST_BIT_DEPTH_16 (4 << 5)
578
579#define DP_TEST_MISC1 0x233
580# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
581# define DP_TEST_INTERLACED (1 << 1)
582
583#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
584
585#define DP_TEST_CRC_R_CR 0x240
586#define DP_TEST_CRC_G_Y 0x242
587#define DP_TEST_CRC_B_CB 0x244
588
589#define DP_TEST_SINK_MISC 0x246
590# define DP_TEST_CRC_SUPPORTED (1 << 5)
591# define DP_TEST_COUNT_MASK 0xf
592
593#define DP_TEST_RESPONSE 0x260
594# define DP_TEST_ACK (1 << 0)
595# define DP_TEST_NAK (1 << 1)
596# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
597
598#define DP_TEST_EDID_CHECKSUM 0x261
599
600#define DP_TEST_SINK 0x270
601# define DP_TEST_SINK_START (1 << 0)
602
603#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0
604# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
605# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
606
607#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1
608
609
610#define DP_SOURCE_OUI 0x300
611#define DP_SINK_OUI 0x400
612#define DP_BRANCH_OUI 0x500
613#define DP_BRANCH_ID 0x503
614#define DP_BRANCH_HW_REV 0x509
615#define DP_BRANCH_SW_REV 0x50A
616
617#define DP_SET_POWER 0x600
618# define DP_SET_POWER_D0 0x1
619# define DP_SET_POWER_D3 0x2
620# define DP_SET_POWER_MASK 0x3
621
622#define DP_EDP_DPCD_REV 0x700
623# define DP_EDP_11 0x00
624# define DP_EDP_12 0x01
625# define DP_EDP_13 0x02
626# define DP_EDP_14 0x03
627
628#define DP_EDP_GENERAL_CAP_1 0x701
629# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
630# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
631# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
632# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
633# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
634# define DP_EDP_FRC_ENABLE_CAP (1 << 5)
635# define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
636# define DP_EDP_SET_POWER_CAP (1 << 7)
637
638#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
639# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
640# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
641# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
642# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
643# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
644# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
645# define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
646# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
647
648#define DP_EDP_GENERAL_CAP_2 0x703
649# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
650
651#define DP_EDP_GENERAL_CAP_3 0x704
652# define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
653# define DP_EDP_X_REGION_CAP_SHIFT 0
654# define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
655# define DP_EDP_Y_REGION_CAP_SHIFT 4
656
657#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
658# define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
659# define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
660# define DP_EDP_FRC_ENABLE (1 << 2)
661# define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
662# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
663
664#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
665# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
666# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
667# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
668# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
669# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
670# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
671# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
672# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
673# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
674# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6)
675
676#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
677#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
678
679#define DP_EDP_PWMGEN_BIT_COUNT 0x724
680#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
681#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
682# define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
683
684#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
685
686#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
687# define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
688
689#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
690#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
691#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
692
693#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
694#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
695#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
696
697#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
698#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
699
700#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740
701#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741
702
703#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000
704#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200
705#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400
706#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600
707
708#define DP_SINK_COUNT_ESI 0x2002
709
710# define DP_SINK_COUNT_CP_READY (1 << 6)
711
712#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003
713
714#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004
715# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
716# define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
717# define DP_CEC_IRQ (1 << 2)
718
719#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005
720
721#define DP_PSR_ERROR_STATUS 0x2006
722# define DP_PSR_LINK_CRC_ERROR (1 << 0)
723# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
724# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2)
725
726#define DP_PSR_ESI 0x2007
727# define DP_PSR_CAPS_CHANGE (1 << 0)
728
729#define DP_PSR_STATUS 0x2008
730# define DP_PSR_SINK_INACTIVE 0
731# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
732# define DP_PSR_SINK_ACTIVE_RFB 2
733# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
734# define DP_PSR_SINK_ACTIVE_RESYNC 4
735# define DP_PSR_SINK_INTERNAL_ERROR 7
736# define DP_PSR_SINK_STATE_MASK 0x07
737
738#define DP_RECEIVER_ALPM_STATUS 0x200b
739# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
740
741#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210
742# define DP_GTC_CAP (1 << 0)
743# define DP_SST_SPLIT_SDP_CAP (1 << 1)
744# define DP_AV_SYNC_CAP (1 << 2)
745# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3)
746# define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4)
747# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5)
748# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6)
749# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7)
750
751
752#define DP_CEC_TUNNELING_CAPABILITY 0x3000
753# define DP_CEC_TUNNELING_CAPABLE (1 << 0)
754# define DP_CEC_SNOOPING_CAPABLE (1 << 1)
755# define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
756
757#define DP_CEC_TUNNELING_CONTROL 0x3001
758# define DP_CEC_TUNNELING_ENABLE (1 << 0)
759# define DP_CEC_SNOOPING_ENABLE (1 << 1)
760
761#define DP_CEC_RX_MESSAGE_INFO 0x3002
762# define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
763# define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
764# define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
765# define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
766# define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
767# define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
768
769#define DP_CEC_TX_MESSAGE_INFO 0x3003
770# define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
771# define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
772# define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
773# define DP_CEC_TX_RETRY_COUNT_SHIFT 4
774# define DP_CEC_TX_MESSAGE_SEND (1 << 7)
775
776#define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
777# define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
778# define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
779# define DP_CEC_TX_MESSAGE_SENT (1 << 4)
780# define DP_CEC_TX_LINE_ERROR (1 << 5)
781# define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
782# define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
783
784#define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E
785# define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
786# define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
787# define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
788# define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
789# define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
790# define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
791# define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
792# define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
793#define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F
794# define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
795# define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
796# define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
797# define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
798# define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
799# define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
800# define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
801# define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
802
803#define DP_CEC_RX_MESSAGE_BUFFER 0x3010
804#define DP_CEC_TX_MESSAGE_BUFFER 0x3020
805#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
806
807
808
809#define DP_PEER_DEVICE_NONE 0x0
810#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
811#define DP_PEER_DEVICE_MST_BRANCHING 0x2
812#define DP_PEER_DEVICE_SST_SINK 0x3
813#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
814
815
816#define DP_LINK_ADDRESS 0x01
817#define DP_CONNECTION_STATUS_NOTIFY 0x02
818#define DP_ENUM_PATH_RESOURCES 0x10
819#define DP_ALLOCATE_PAYLOAD 0x11
820#define DP_QUERY_PAYLOAD 0x12
821#define DP_RESOURCE_STATUS_NOTIFY 0x13
822#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
823#define DP_REMOTE_DPCD_READ 0x20
824#define DP_REMOTE_DPCD_WRITE 0x21
825#define DP_REMOTE_I2C_READ 0x22
826#define DP_REMOTE_I2C_WRITE 0x23
827#define DP_POWER_UP_PHY 0x24
828#define DP_POWER_DOWN_PHY 0x25
829#define DP_SINK_EVENT_NOTIFY 0x30
830#define DP_QUERY_STREAM_ENC_STATUS 0x38
831
832
833#define DP_NAK_WRITE_FAILURE 0x01
834#define DP_NAK_INVALID_READ 0x02
835#define DP_NAK_CRC_FAILURE 0x03
836#define DP_NAK_BAD_PARAM 0x04
837#define DP_NAK_DEFER 0x05
838#define DP_NAK_LINK_FAILURE 0x06
839#define DP_NAK_NO_RESOURCES 0x07
840#define DP_NAK_DPCD_FAIL 0x08
841#define DP_NAK_I2C_NAK 0x09
842#define DP_NAK_ALLOCATE_FAIL 0x0a
843
844#define MODE_I2C_START 1
845#define MODE_I2C_WRITE 2
846#define MODE_I2C_READ 4
847#define MODE_I2C_STOP 8
848
849
850#define DP_MST_PHYSICAL_PORT_0 0
851#define DP_MST_LOGICAL_PORT_0 8
852
853#define DP_LINK_STATUS_SIZE 6
854bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
855 int lane_count);
856bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
857 int lane_count);
858u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
859 int lane);
860u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
861 int lane);
862
863#define DP_BRANCH_OUI_HEADER_SIZE 0xc
864#define DP_RECEIVER_CAP_SIZE 0xf
865#define EDP_PSR_RECEIVER_CAP_SIZE 2
866#define EDP_DISPLAY_CTL_CAP_SIZE 3
867
868void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
869void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
870
871u8 drm_dp_link_rate_to_bw_code(int link_rate);
872int drm_dp_bw_code_to_link_rate(u8 link_bw);
873
874struct edp_sdp_header {
875 u8 HB0;
876 u8 HB1;
877 u8 HB2;
878 u8 HB3;
879} __packed;
880
881#define EDP_SDP_HEADER_REVISION_MASK 0x1F
882#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
883
884struct edp_vsc_psr {
885 struct edp_sdp_header sdp_header;
886 u8 DB0;
887 u8 DB1;
888 u8 DB2;
889 u8 DB3;
890 u8 DB4;
891 u8 DB5;
892 u8 DB6;
893 u8 DB7;
894 u8 DB8_31[24];
895} __packed;
896
897#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
898#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
899#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
900
901int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
902
903static inline int
904drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
905{
906 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
907}
908
909static inline u8
910drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
911{
912 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
913}
914
915static inline bool
916drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
917{
918 return dpcd[DP_DPCD_REV] >= 0x11 &&
919 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
920}
921
922static inline bool
923drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
924{
925 return dpcd[DP_DPCD_REV] >= 0x12 &&
926 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
927}
928
929static inline bool
930drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
931{
932 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
933}
934
935
936
937
938
939
940
941
942
943
944
945
946
947struct drm_dp_aux_msg {
948 unsigned int address;
949 u8 request;
950 u8 reply;
951 void *buffer;
952 size_t size;
953};
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995struct drm_dp_aux {
996 const char *name;
997 struct i2c_adapter ddc;
998 struct device *dev;
999 struct drm_crtc *crtc;
1000 struct mutex hw_mutex;
1001 struct work_struct crc_work;
1002 u8 crc_count;
1003 ssize_t (*transfer)(struct drm_dp_aux *aux,
1004 struct drm_dp_aux_msg *msg);
1005
1006
1007
1008 unsigned i2c_nack_count;
1009
1010
1011
1012 unsigned i2c_defer_count;
1013};
1014
1015ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
1016 void *buffer, size_t size);
1017ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
1018 void *buffer, size_t size);
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
1030 unsigned int offset, u8 *valuep)
1031{
1032 return drm_dp_dpcd_read(aux, offset, valuep, 1);
1033}
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
1045 unsigned int offset, u8 value)
1046{
1047 return drm_dp_dpcd_write(aux, offset, &value, 1);
1048}
1049
1050int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
1051 u8 status[DP_LINK_STATUS_SIZE]);
1052
1053
1054
1055
1056#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
1057
1058struct drm_dp_link {
1059 unsigned char revision;
1060 unsigned int rate;
1061 unsigned int num_lanes;
1062 unsigned long capabilities;
1063};
1064
1065int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
1066int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
1067int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
1068int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
1069int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1070 const u8 port_cap[4]);
1071int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1072 const u8 port_cap[4]);
1073int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
1074void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1075 const u8 port_cap[4], struct drm_dp_aux *aux);
1076
1077void drm_dp_aux_init(struct drm_dp_aux *aux);
1078int drm_dp_aux_register(struct drm_dp_aux *aux);
1079void drm_dp_aux_unregister(struct drm_dp_aux *aux);
1080
1081int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
1082int drm_dp_stop_crc(struct drm_dp_aux *aux);
1083
1084struct drm_dp_dpcd_ident {
1085 u8 oui[3];
1086 u8 device_id[6];
1087 u8 hw_rev;
1088 u8 sw_major_rev;
1089 u8 sw_minor_rev;
1090} __packed;
1091
1092
1093
1094
1095
1096
1097struct drm_dp_desc {
1098 struct drm_dp_dpcd_ident ident;
1099 u32 quirks;
1100};
1101
1102int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1103 bool is_branch);
1104
1105
1106
1107
1108
1109
1110
1111
1112enum drm_dp_quirk {
1113
1114
1115
1116
1117
1118
1119 DP_DPCD_QUIRK_LIMITED_M_N,
1120};
1121
1122
1123
1124
1125
1126
1127
1128
1129static inline bool
1130drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
1131{
1132 return desc->quirks & BIT(quirk);
1133}
1134
1135#endif
1136