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17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
20
21#include <linux/mod_devicetable.h>
22
23#include <linux/types.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/list.h>
27#include <linux/compiler.h>
28#include <linux/errno.h>
29#include <linux/kobject.h>
30#include <linux/atomic.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/io.h>
34#include <linux/resource_ext.h>
35#include <uapi/linux/pci.h>
36
37#include <linux/pci_ids.h>
38
39
40
41
42
43
44
45
46
47
48
49
50
51#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52
53#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
54
55
56struct pci_slot {
57 struct pci_bus *bus;
58 struct list_head list;
59 struct hotplug_slot *hotplug;
60 unsigned char number;
61 struct kobject kobj;
62};
63
64static inline const char *pci_slot_name(const struct pci_slot *slot)
65{
66 return kobject_name(&slot->kobj);
67}
68
69
70enum pci_mmap_state {
71 pci_mmap_io,
72 pci_mmap_mem
73};
74
75
76
77
78enum {
79
80 PCI_STD_RESOURCES,
81 PCI_STD_RESOURCE_END = 5,
82
83
84 PCI_ROM_RESOURCE,
85
86
87#ifdef CONFIG_PCI_IOV
88 PCI_IOV_RESOURCES,
89 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90#endif
91
92
93#define PCI_BRIDGE_RESOURCE_NUM 4
94
95 PCI_BRIDGE_RESOURCES,
96 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
97 PCI_BRIDGE_RESOURCE_NUM - 1,
98
99
100 PCI_NUM_RESOURCES,
101
102
103 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
104};
105
106
107
108
109
110
111
112
113
114
115
116
117enum pci_interrupt_pin {
118 PCI_INTERRUPT_UNKNOWN,
119 PCI_INTERRUPT_INTA,
120 PCI_INTERRUPT_INTB,
121 PCI_INTERRUPT_INTC,
122 PCI_INTERRUPT_INTD,
123};
124
125
126#define PCI_NUM_INTX 4
127
128
129
130
131
132typedef int __bitwise pci_power_t;
133
134#define PCI_D0 ((pci_power_t __force) 0)
135#define PCI_D1 ((pci_power_t __force) 1)
136#define PCI_D2 ((pci_power_t __force) 2)
137#define PCI_D3hot ((pci_power_t __force) 3)
138#define PCI_D3cold ((pci_power_t __force) 4)
139#define PCI_UNKNOWN ((pci_power_t __force) 5)
140#define PCI_POWER_ERROR ((pci_power_t __force) -1)
141
142
143extern const char *pci_power_names[];
144
145static inline const char *pci_power_name(pci_power_t state)
146{
147 return pci_power_names[1 + (__force int) state];
148}
149
150#define PCI_PM_D2_DELAY 200
151#define PCI_PM_D3_WAIT 10
152#define PCI_PM_D3COLD_WAIT 100
153#define PCI_PM_BUS_WAIT 50
154
155
156
157
158
159typedef unsigned int __bitwise pci_channel_state_t;
160
161enum pci_channel_state {
162
163 pci_channel_io_normal = (__force pci_channel_state_t) 1,
164
165
166 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
167
168
169 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
170};
171
172typedef unsigned int __bitwise pcie_reset_state_t;
173
174enum pcie_reset_state {
175
176 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
177
178
179 pcie_warm_reset = (__force pcie_reset_state_t) 2,
180
181
182 pcie_hot_reset = (__force pcie_reset_state_t) 3
183};
184
185typedef unsigned short __bitwise pci_dev_flags_t;
186enum pci_dev_flags {
187
188
189
190 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
191
192 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
193
194 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
195
196 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
197
198 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
199
200 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
201
202 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
203
204 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
205
206 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
207
208 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
209
210
211
212
213 PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11),
214
215 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 12),
216};
217
218enum pci_irq_reroute_variant {
219 INTEL_IRQ_REROUTE_VARIANT = 1,
220 MAX_IRQ_REROUTE_VARIANTS = 3
221};
222
223typedef unsigned short __bitwise pci_bus_flags_t;
224enum pci_bus_flags {
225 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
226 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
227 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
228};
229
230
231enum pcie_link_width {
232 PCIE_LNK_WIDTH_RESRV = 0x00,
233 PCIE_LNK_X1 = 0x01,
234 PCIE_LNK_X2 = 0x02,
235 PCIE_LNK_X4 = 0x04,
236 PCIE_LNK_X8 = 0x08,
237 PCIE_LNK_X12 = 0x0C,
238 PCIE_LNK_X16 = 0x10,
239 PCIE_LNK_X32 = 0x20,
240 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
241};
242
243
244enum pci_bus_speed {
245 PCI_SPEED_33MHz = 0x00,
246 PCI_SPEED_66MHz = 0x01,
247 PCI_SPEED_66MHz_PCIX = 0x02,
248 PCI_SPEED_100MHz_PCIX = 0x03,
249 PCI_SPEED_133MHz_PCIX = 0x04,
250 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
251 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
252 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
253 PCI_SPEED_66MHz_PCIX_266 = 0x09,
254 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
255 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
256 AGP_UNKNOWN = 0x0c,
257 AGP_1X = 0x0d,
258 AGP_2X = 0x0e,
259 AGP_4X = 0x0f,
260 AGP_8X = 0x10,
261 PCI_SPEED_66MHz_PCIX_533 = 0x11,
262 PCI_SPEED_100MHz_PCIX_533 = 0x12,
263 PCI_SPEED_133MHz_PCIX_533 = 0x13,
264 PCIE_SPEED_2_5GT = 0x14,
265 PCIE_SPEED_5_0GT = 0x15,
266 PCIE_SPEED_8_0GT = 0x16,
267 PCI_SPEED_UNKNOWN = 0xff,
268};
269
270struct pci_cap_saved_data {
271 u16 cap_nr;
272 bool cap_extended;
273 unsigned int size;
274 u32 data[0];
275};
276
277struct pci_cap_saved_state {
278 struct hlist_node next;
279 struct pci_cap_saved_data cap;
280};
281
282struct irq_affinity;
283struct pcie_link_state;
284struct pci_vpd;
285struct pci_sriov;
286struct pci_ats;
287
288
289
290
291struct pci_dev {
292 struct list_head bus_list;
293 struct pci_bus *bus;
294 struct pci_bus *subordinate;
295
296 void *sysdata;
297 struct proc_dir_entry *procent;
298 struct pci_slot *slot;
299
300 unsigned int devfn;
301 unsigned short vendor;
302 unsigned short device;
303 unsigned short subsystem_vendor;
304 unsigned short subsystem_device;
305 unsigned int class;
306 u8 revision;
307 u8 hdr_type;
308#ifdef CONFIG_PCIEAER
309 u16 aer_cap;
310#endif
311 u8 pcie_cap;
312 u8 msi_cap;
313 u8 msix_cap;
314 u8 pcie_mpss:3;
315 u8 rom_base_reg;
316 u8 pin;
317 u16 pcie_flags_reg;
318 unsigned long *dma_alias_mask;
319
320 struct pci_driver *driver;
321 u64 dma_mask;
322
323
324
325
326
327 struct device_dma_parameters dma_parms;
328
329 pci_power_t current_state;
330
331
332 u8 pm_cap;
333 unsigned int pme_support:5;
334
335 unsigned int pme_poll:1;
336 unsigned int d1_support:1;
337 unsigned int d2_support:1;
338 unsigned int no_d1d2:1;
339 unsigned int no_d3cold:1;
340 unsigned int bridge_d3:1;
341 unsigned int d3cold_allowed:1;
342 unsigned int mmio_always_on:1;
343
344 unsigned int wakeup_prepared:1;
345 unsigned int runtime_d3cold:1;
346
347
348
349 unsigned int ignore_hotplug:1;
350 unsigned int hotplug_user_indicators:1;
351
352
353 unsigned int d3_delay;
354 unsigned int d3cold_delay;
355
356#ifdef CONFIG_PCIEASPM
357 struct pcie_link_state *link_state;
358#endif
359
360 pci_channel_state_t error_state;
361 struct device dev;
362
363 int cfg_size;
364
365
366
367
368
369 unsigned int irq;
370 struct resource resource[DEVICE_COUNT_RESOURCE];
371
372 bool match_driver;
373
374 unsigned int transparent:1;
375 unsigned int multifunction:1;
376
377 unsigned int is_added:1;
378 unsigned int is_busmaster:1;
379 unsigned int no_msi:1;
380 unsigned int no_64bit_msi:1;
381 unsigned int block_cfg_access:1;
382 unsigned int broken_parity_status:1;
383 unsigned int irq_reroute_variant:2;
384 unsigned int msi_enabled:1;
385 unsigned int msix_enabled:1;
386 unsigned int ari_enabled:1;
387 unsigned int ats_enabled:1;
388 unsigned int pasid_enabled:1;
389 unsigned int pri_enabled:1;
390 unsigned int is_managed:1;
391 unsigned int needs_freset:1;
392 unsigned int state_saved:1;
393 unsigned int is_physfn:1;
394 unsigned int is_virtfn:1;
395 unsigned int reset_fn:1;
396 unsigned int is_hotplug_bridge:1;
397 unsigned int is_thunderbolt:1;
398 unsigned int __aer_firmware_first_valid:1;
399 unsigned int __aer_firmware_first:1;
400 unsigned int broken_intx_masking:1;
401 unsigned int io_window_1k:1;
402 unsigned int irq_managed:1;
403 unsigned int has_secondary_link:1;
404 unsigned int non_compliant_bars:1;
405 unsigned int is_probed:1;
406 pci_dev_flags_t dev_flags;
407 atomic_t enable_cnt;
408
409 u32 saved_config_space[16];
410 struct hlist_head saved_cap_space;
411 struct bin_attribute *rom_attr;
412 int rom_attr_enabled;
413 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE];
414 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE];
415
416#ifdef CONFIG_PCIE_PTM
417 unsigned int ptm_root:1;
418 unsigned int ptm_enabled:1;
419 u8 ptm_granularity;
420#endif
421#ifdef CONFIG_PCI_MSI
422 const struct attribute_group **msi_irq_groups;
423#endif
424 struct pci_vpd *vpd;
425#ifdef CONFIG_PCI_ATS
426 union {
427 struct pci_sriov *sriov;
428 struct pci_dev *physfn;
429 };
430 u16 ats_cap;
431 u8 ats_stu;
432 atomic_t ats_ref_cnt;
433#endif
434#ifdef CONFIG_PCI_PRI
435 u32 pri_reqs_alloc;
436#endif
437#ifdef CONFIG_PCI_PASID
438 u16 pasid_features;
439#endif
440 phys_addr_t rom;
441 size_t romlen;
442 char *driver_override;
443
444 unsigned long priv_flags;
445};
446
447static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
448{
449#ifdef CONFIG_PCI_IOV
450 if (dev->is_virtfn)
451 dev = dev->physfn;
452#endif
453 return dev;
454}
455
456struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
457
458#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
459#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
460
461static inline int pci_channel_offline(struct pci_dev *pdev)
462{
463 return (pdev->error_state != pci_channel_io_normal);
464}
465
466struct pci_host_bridge {
467 struct device dev;
468 struct pci_bus *bus;
469 struct pci_ops *ops;
470 void *sysdata;
471 int busnr;
472 struct list_head windows;
473 u8 (*swizzle_irq)(struct pci_dev *, u8 *);
474 int (*map_irq)(const struct pci_dev *, u8, u8);
475 void (*release_fn)(struct pci_host_bridge *);
476 void *release_data;
477 struct msi_controller *msi;
478 unsigned int ignore_reset_delay:1;
479 unsigned int no_ext_tags:1;
480
481 resource_size_t (*align_resource)(struct pci_dev *dev,
482 const struct resource *res,
483 resource_size_t start,
484 resource_size_t size,
485 resource_size_t align);
486 unsigned long private[0] ____cacheline_aligned;
487};
488
489#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
490
491static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
492{
493 return (void *)bridge->private;
494}
495
496static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
497{
498 return container_of(priv, struct pci_host_bridge, private);
499}
500
501struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
502struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
503 size_t priv);
504void pci_free_host_bridge(struct pci_host_bridge *bridge);
505struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
506
507void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
508 void (*release_fn)(struct pci_host_bridge *),
509 void *release_data);
510
511int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
512
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525
526#define PCI_SUBTRACTIVE_DECODE 0x1
527
528struct pci_bus_resource {
529 struct list_head list;
530 struct resource *res;
531 unsigned int flags;
532};
533
534#define PCI_REGION_FLAG_MASK 0x0fU
535
536struct pci_bus {
537 struct list_head node;
538 struct pci_bus *parent;
539 struct list_head children;
540 struct list_head devices;
541 struct pci_dev *self;
542 struct list_head slots;
543
544 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
545 struct list_head resources;
546 struct resource busn_res;
547
548 struct pci_ops *ops;
549 struct msi_controller *msi;
550 void *sysdata;
551 struct proc_dir_entry *procdir;
552
553 unsigned char number;
554 unsigned char primary;
555 unsigned char max_bus_speed;
556 unsigned char cur_bus_speed;
557#ifdef CONFIG_PCI_DOMAINS_GENERIC
558 int domain_nr;
559#endif
560
561 char name[48];
562
563 unsigned short bridge_ctl;
564 pci_bus_flags_t bus_flags;
565 struct device *bridge;
566 struct device dev;
567 struct bin_attribute *legacy_io;
568 struct bin_attribute *legacy_mem;
569 unsigned int is_added:1;
570};
571
572#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
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581
582static inline bool pci_is_root_bus(struct pci_bus *pbus)
583{
584 return !(pbus->parent);
585}
586
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592
593
594static inline bool pci_is_bridge(struct pci_dev *dev)
595{
596 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
597 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
598}
599
600static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
601{
602 dev = pci_physfn(dev);
603 if (pci_is_root_bus(dev->bus))
604 return NULL;
605
606 return dev->bus->self;
607}
608
609struct device *pci_get_host_bridge_device(struct pci_dev *dev);
610void pci_put_host_bridge_device(struct device *dev);
611
612#ifdef CONFIG_PCI_MSI
613static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
614{
615 return pci_dev->msi_enabled || pci_dev->msix_enabled;
616}
617#else
618static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
619#endif
620
621
622
623
624#define PCIBIOS_SUCCESSFUL 0x00
625#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
626#define PCIBIOS_BAD_VENDOR_ID 0x83
627#define PCIBIOS_DEVICE_NOT_FOUND 0x86
628#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
629#define PCIBIOS_SET_FAILED 0x88
630#define PCIBIOS_BUFFER_TOO_SMALL 0x89
631
632
633
634
635static inline int pcibios_err_to_errno(int err)
636{
637 if (err <= PCIBIOS_SUCCESSFUL)
638 return err;
639
640 switch (err) {
641 case PCIBIOS_FUNC_NOT_SUPPORTED:
642 return -ENOENT;
643 case PCIBIOS_BAD_VENDOR_ID:
644 return -ENOTTY;
645 case PCIBIOS_DEVICE_NOT_FOUND:
646 return -ENODEV;
647 case PCIBIOS_BAD_REGISTER_NUMBER:
648 return -EFAULT;
649 case PCIBIOS_SET_FAILED:
650 return -EIO;
651 case PCIBIOS_BUFFER_TOO_SMALL:
652 return -ENOSPC;
653 }
654
655 return -ERANGE;
656}
657
658
659
660struct pci_ops {
661 int (*add_bus)(struct pci_bus *bus);
662 void (*remove_bus)(struct pci_bus *bus);
663 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
664 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
665 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
666};
667
668
669
670
671
672int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
673 int reg, int len, u32 *val);
674int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
675 int reg, int len, u32 val);
676
677#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
678typedef u64 pci_bus_addr_t;
679#else
680typedef u32 pci_bus_addr_t;
681#endif
682
683struct pci_bus_region {
684 pci_bus_addr_t start;
685 pci_bus_addr_t end;
686};
687
688struct pci_dynids {
689 spinlock_t lock;
690 struct list_head list;
691};
692
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699
700
701typedef unsigned int __bitwise pci_ers_result_t;
702
703enum pci_ers_result {
704
705 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
706
707
708 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
709
710
711 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
712
713
714 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
715
716
717 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
718
719
720 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
721};
722
723
724struct pci_error_handlers {
725
726 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
727 enum pci_channel_state error);
728
729
730 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
731
732
733 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
734
735
736 void (*reset_prepare)(struct pci_dev *dev);
737 void (*reset_done)(struct pci_dev *dev);
738
739
740 void (*resume)(struct pci_dev *dev);
741};
742
743
744struct module;
745struct pci_driver {
746 struct list_head node;
747 const char *name;
748 const struct pci_device_id *id_table;
749 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id);
750 void (*remove) (struct pci_dev *dev);
751 int (*suspend) (struct pci_dev *dev, pm_message_t state);
752 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
753 int (*resume_early) (struct pci_dev *dev);
754 int (*resume) (struct pci_dev *dev);
755 void (*shutdown) (struct pci_dev *dev);
756 int (*sriov_configure) (struct pci_dev *dev, int num_vfs);
757 const struct pci_error_handlers *err_handler;
758 const struct attribute_group **groups;
759 struct device_driver driver;
760 struct pci_dynids dynids;
761};
762
763#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
764
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773
774#define PCI_DEVICE(vend,dev) \
775 .vendor = (vend), .device = (dev), \
776 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
777
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787
788#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
789 .vendor = (vend), .device = (dev), \
790 .subvendor = (subvend), .subdevice = (subdev)
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800
801#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
802 .class = (dev_class), .class_mask = (dev_class_mask), \
803 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
804 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
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816
817#define PCI_VDEVICE(vend, dev) \
818 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
819 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
820
821enum {
822 PCI_REASSIGN_ALL_RSRC = 0x00000001,
823 PCI_REASSIGN_ALL_BUS = 0x00000002,
824 PCI_PROBE_ONLY = 0x00000004,
825 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
826 PCI_ENABLE_PROC_DOMAINS = 0x00000010,
827 PCI_COMPAT_DOMAIN_0 = 0x00000020,
828 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040,
829};
830
831
832#ifdef CONFIG_PCI
833
834extern unsigned int pci_flags;
835
836static inline void pci_set_flags(int flags) { pci_flags = flags; }
837static inline void pci_add_flags(int flags) { pci_flags |= flags; }
838static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
839static inline int pci_has_flag(int flag) { return pci_flags & flag; }
840
841void pcie_bus_configure_settings(struct pci_bus *bus);
842
843enum pcie_bus_config_types {
844 PCIE_BUS_TUNE_OFF,
845 PCIE_BUS_DEFAULT,
846 PCIE_BUS_SAFE,
847 PCIE_BUS_PERFORMANCE,
848 PCIE_BUS_PEER2PEER,
849};
850
851extern enum pcie_bus_config_types pcie_bus_config;
852
853extern struct bus_type pci_bus_type;
854
855
856
857extern struct list_head pci_root_buses;
858
859int no_pci_devices(void);
860
861void pcibios_resource_survey_bus(struct pci_bus *bus);
862void pcibios_bus_add_device(struct pci_dev *pdev);
863void pcibios_add_bus(struct pci_bus *bus);
864void pcibios_remove_bus(struct pci_bus *bus);
865void pcibios_fixup_bus(struct pci_bus *);
866int __must_check pcibios_enable_device(struct pci_dev *, int mask);
867
868char *pcibios_setup(char *str);
869
870
871resource_size_t pcibios_align_resource(void *, const struct resource *,
872 resource_size_t,
873 resource_size_t);
874
875
876void pci_fixup_cardbus(struct pci_bus *);
877
878
879
880void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
881 struct resource *res);
882void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
883 struct pci_bus_region *region);
884void pcibios_scan_specific_bus(int busn);
885struct pci_bus *pci_find_bus(int domain, int busnr);
886void pci_bus_add_devices(const struct pci_bus *bus);
887struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
888struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
889 struct pci_ops *ops, void *sysdata,
890 struct list_head *resources);
891int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
892int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
893void pci_bus_release_busn_res(struct pci_bus *b);
894struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
895 struct pci_ops *ops, void *sysdata,
896 struct list_head *resources);
897int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
898struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
899 int busnr);
900void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
901struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
902 const char *name,
903 struct hotplug_slot *hotplug);
904void pci_destroy_slot(struct pci_slot *slot);
905#ifdef CONFIG_SYSFS
906void pci_dev_assign_slot(struct pci_dev *dev);
907#else
908static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
909#endif
910int pci_scan_slot(struct pci_bus *bus, int devfn);
911struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
912void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
913unsigned int pci_scan_child_bus(struct pci_bus *bus);
914void pci_bus_add_device(struct pci_dev *dev);
915void pci_read_bridge_bases(struct pci_bus *child);
916struct resource *pci_find_parent_resource(const struct pci_dev *dev,
917 struct resource *res);
918struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
919u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
920int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
921u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
922struct pci_dev *pci_dev_get(struct pci_dev *dev);
923void pci_dev_put(struct pci_dev *dev);
924void pci_remove_bus(struct pci_bus *b);
925void pci_stop_and_remove_bus_device(struct pci_dev *dev);
926void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
927void pci_stop_root_bus(struct pci_bus *bus);
928void pci_remove_root_bus(struct pci_bus *bus);
929void pci_setup_cardbus(struct pci_bus *bus);
930void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
931void pci_sort_breadthfirst(void);
932#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
933#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
934
935
936
937enum pci_lost_interrupt_reason {
938 PCI_LOST_IRQ_NO_INFORMATION = 0,
939 PCI_LOST_IRQ_DISABLE_MSI,
940 PCI_LOST_IRQ_DISABLE_MSIX,
941 PCI_LOST_IRQ_DISABLE_ACPI,
942};
943enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
944int pci_find_capability(struct pci_dev *dev, int cap);
945int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
946int pci_find_ext_capability(struct pci_dev *dev, int cap);
947int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
948int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
949int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
950struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
951
952struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
953 struct pci_dev *from);
954struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
955 unsigned int ss_vendor, unsigned int ss_device,
956 struct pci_dev *from);
957struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
958struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
959 unsigned int devfn);
960static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
961 unsigned int devfn)
962{
963 return pci_get_domain_bus_and_slot(0, bus, devfn);
964}
965struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
966int pci_dev_present(const struct pci_device_id *ids);
967
968int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
969 int where, u8 *val);
970int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
971 int where, u16 *val);
972int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
973 int where, u32 *val);
974int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
975 int where, u8 val);
976int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
977 int where, u16 val);
978int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
979 int where, u32 val);
980
981int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
982 int where, int size, u32 *val);
983int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
984 int where, int size, u32 val);
985int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
986 int where, int size, u32 *val);
987int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
988 int where, int size, u32 val);
989
990struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
991
992int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
993int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
994int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
995int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
996int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
997int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
998
999int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1000int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1001int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1002int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1003int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1004 u16 clear, u16 set);
1005int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1006 u32 clear, u32 set);
1007
1008static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1009 u16 set)
1010{
1011 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1012}
1013
1014static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1015 u32 set)
1016{
1017 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1018}
1019
1020static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1021 u16 clear)
1022{
1023 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1024}
1025
1026static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1027 u32 clear)
1028{
1029 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1030}
1031
1032
1033int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1034int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1035int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1036int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1037int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1038int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1039
1040int __must_check pci_enable_device(struct pci_dev *dev);
1041int __must_check pci_enable_device_io(struct pci_dev *dev);
1042int __must_check pci_enable_device_mem(struct pci_dev *dev);
1043int __must_check pci_reenable_device(struct pci_dev *);
1044int __must_check pcim_enable_device(struct pci_dev *pdev);
1045void pcim_pin_device(struct pci_dev *pdev);
1046
1047static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1048{
1049
1050
1051
1052
1053 return !pdev->broken_intx_masking;
1054}
1055
1056static inline int pci_is_enabled(struct pci_dev *pdev)
1057{
1058 return (atomic_read(&pdev->enable_cnt) > 0);
1059}
1060
1061static inline int pci_is_managed(struct pci_dev *pdev)
1062{
1063 return pdev->is_managed;
1064}
1065
1066void pci_disable_device(struct pci_dev *dev);
1067
1068extern unsigned int pcibios_max_latency;
1069void pci_set_master(struct pci_dev *dev);
1070void pci_clear_master(struct pci_dev *dev);
1071
1072int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1073int pci_set_cacheline_size(struct pci_dev *dev);
1074#define HAVE_PCI_SET_MWI
1075int __must_check pci_set_mwi(struct pci_dev *dev);
1076int pci_try_set_mwi(struct pci_dev *dev);
1077void pci_clear_mwi(struct pci_dev *dev);
1078void pci_intx(struct pci_dev *dev, int enable);
1079bool pci_check_and_mask_intx(struct pci_dev *dev);
1080bool pci_check_and_unmask_intx(struct pci_dev *dev);
1081int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1082int pci_wait_for_pending_transaction(struct pci_dev *dev);
1083int pcix_get_max_mmrbc(struct pci_dev *dev);
1084int pcix_get_mmrbc(struct pci_dev *dev);
1085int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1086int pcie_get_readrq(struct pci_dev *dev);
1087int pcie_set_readrq(struct pci_dev *dev, int rq);
1088int pcie_get_mps(struct pci_dev *dev);
1089int pcie_set_mps(struct pci_dev *dev, int mps);
1090int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1091 enum pcie_link_width *width);
1092void pcie_flr(struct pci_dev *dev);
1093int __pci_reset_function(struct pci_dev *dev);
1094int __pci_reset_function_locked(struct pci_dev *dev);
1095int pci_reset_function(struct pci_dev *dev);
1096int pci_reset_function_locked(struct pci_dev *dev);
1097int pci_try_reset_function(struct pci_dev *dev);
1098int pci_probe_reset_slot(struct pci_slot *slot);
1099int pci_reset_slot(struct pci_slot *slot);
1100int pci_try_reset_slot(struct pci_slot *slot);
1101int pci_probe_reset_bus(struct pci_bus *bus);
1102int pci_reset_bus(struct pci_bus *bus);
1103int pci_try_reset_bus(struct pci_bus *bus);
1104void pci_reset_secondary_bus(struct pci_dev *dev);
1105void pcibios_reset_secondary_bus(struct pci_dev *dev);
1106void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1107void pci_update_resource(struct pci_dev *dev, int resno);
1108int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1109int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1110int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1111bool pci_device_is_present(struct pci_dev *pdev);
1112void pci_ignore_hotplug(struct pci_dev *dev);
1113
1114int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1115 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1116 const char *fmt, ...);
1117void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1118
1119
1120int pci_enable_rom(struct pci_dev *pdev);
1121void pci_disable_rom(struct pci_dev *pdev);
1122void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1123void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1124size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1125void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1126
1127
1128int pci_save_state(struct pci_dev *dev);
1129void pci_restore_state(struct pci_dev *dev);
1130struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1131int pci_load_saved_state(struct pci_dev *dev,
1132 struct pci_saved_state *state);
1133int pci_load_and_free_saved_state(struct pci_dev *dev,
1134 struct pci_saved_state **state);
1135struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1136struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1137 u16 cap);
1138int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1139int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1140 u16 cap, unsigned int size);
1141int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1142int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1143pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1144bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1145void pci_pme_active(struct pci_dev *dev, bool enable);
1146int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1147int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1148int pci_prepare_to_sleep(struct pci_dev *dev);
1149int pci_back_from_sleep(struct pci_dev *dev);
1150bool pci_dev_run_wake(struct pci_dev *dev);
1151bool pci_check_pme_status(struct pci_dev *dev);
1152void pci_pme_wakeup_bus(struct pci_bus *bus);
1153void pci_d3cold_enable(struct pci_dev *dev);
1154void pci_d3cold_disable(struct pci_dev *dev);
1155bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1156
1157
1158int pci_save_vc_state(struct pci_dev *dev);
1159void pci_restore_vc_state(struct pci_dev *dev);
1160void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1161
1162
1163void set_pcie_port_type(struct pci_dev *pdev);
1164void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1165
1166
1167int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1168unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1169unsigned int pci_rescan_bus(struct pci_bus *bus);
1170void pci_lock_rescan_remove(void);
1171void pci_unlock_rescan_remove(void);
1172
1173
1174ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1175ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1176int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1177
1178
1179resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1180void pci_bus_assign_resources(const struct pci_bus *bus);
1181void pci_bus_claim_resources(struct pci_bus *bus);
1182void pci_bus_size_bridges(struct pci_bus *bus);
1183int pci_claim_resource(struct pci_dev *, int);
1184int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1185void pci_assign_unassigned_resources(void);
1186void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1187void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1188void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1189void pdev_enable_device(struct pci_dev *);
1190int pci_enable_resources(struct pci_dev *, int mask);
1191void pci_assign_irq(struct pci_dev *dev);
1192struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1193#define HAVE_PCI_REQ_REGIONS 2
1194int __must_check pci_request_regions(struct pci_dev *, const char *);
1195int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1196void pci_release_regions(struct pci_dev *);
1197int __must_check pci_request_region(struct pci_dev *, int, const char *);
1198int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1199void pci_release_region(struct pci_dev *, int);
1200int pci_request_selected_regions(struct pci_dev *, int, const char *);
1201int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1202void pci_release_selected_regions(struct pci_dev *, int);
1203
1204
1205struct pci_bus *pci_bus_get(struct pci_bus *bus);
1206void pci_bus_put(struct pci_bus *bus);
1207void pci_add_resource(struct list_head *resources, struct resource *res);
1208void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1209 resource_size_t offset);
1210void pci_free_resource_list(struct list_head *resources);
1211void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1212 unsigned int flags);
1213struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1214void pci_bus_remove_resources(struct pci_bus *bus);
1215int devm_request_pci_bus_resources(struct device *dev,
1216 struct list_head *resources);
1217
1218#define pci_bus_for_each_resource(bus, res, i) \
1219 for (i = 0; \
1220 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1221 i++)
1222
1223int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1224 struct resource *res, resource_size_t size,
1225 resource_size_t align, resource_size_t min,
1226 unsigned long type_mask,
1227 resource_size_t (*alignf)(void *,
1228 const struct resource *,
1229 resource_size_t,
1230 resource_size_t),
1231 void *alignf_data);
1232
1233
1234int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1235unsigned long pci_address_to_pio(phys_addr_t addr);
1236phys_addr_t pci_pio_to_address(unsigned long pio);
1237int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1238void pci_unmap_iospace(struct resource *res);
1239void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1240 resource_size_t offset,
1241 resource_size_t size);
1242void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1243 struct resource *res);
1244
1245static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1246{
1247 struct pci_bus_region region;
1248
1249 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1250 return region.start;
1251}
1252
1253
1254int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1255 const char *mod_name);
1256
1257
1258
1259
1260#define pci_register_driver(driver) \
1261 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1262
1263void pci_unregister_driver(struct pci_driver *dev);
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273#define module_pci_driver(__pci_driver) \
1274 module_driver(__pci_driver, pci_register_driver, \
1275 pci_unregister_driver)
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285#define builtin_pci_driver(__pci_driver) \
1286 builtin_driver(__pci_driver, pci_register_driver)
1287
1288struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1289int pci_add_dynid(struct pci_driver *drv,
1290 unsigned int vendor, unsigned int device,
1291 unsigned int subvendor, unsigned int subdevice,
1292 unsigned int class, unsigned int class_mask,
1293 unsigned long driver_data);
1294const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1295 struct pci_dev *dev);
1296int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1297 int pass);
1298
1299void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1300 void *userdata);
1301int pci_cfg_space_size(struct pci_dev *dev);
1302unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1303void pci_setup_bridge(struct pci_bus *bus);
1304resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1305 unsigned long type);
1306resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1307
1308#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1309#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1310
1311int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1312 unsigned int command_bits, u32 flags);
1313
1314#define PCI_IRQ_LEGACY (1 << 0)
1315#define PCI_IRQ_MSI (1 << 1)
1316#define PCI_IRQ_MSIX (1 << 2)
1317#define PCI_IRQ_AFFINITY (1 << 3)
1318#define PCI_IRQ_ALL_TYPES \
1319 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1320
1321
1322
1323#include <linux/pci-dma.h>
1324#include <linux/dmapool.h>
1325
1326#define pci_pool dma_pool
1327#define pci_pool_create(name, pdev, size, align, allocation) \
1328 dma_pool_create(name, &pdev->dev, size, align, allocation)
1329#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1330#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1331#define pci_pool_zalloc(pool, flags, handle) \
1332 dma_pool_zalloc(pool, flags, handle)
1333#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1334
1335struct msix_entry {
1336 u32 vector;
1337 u16 entry;
1338};
1339
1340#ifdef CONFIG_PCI_MSI
1341int pci_msi_vec_count(struct pci_dev *dev);
1342void pci_disable_msi(struct pci_dev *dev);
1343int pci_msix_vec_count(struct pci_dev *dev);
1344void pci_disable_msix(struct pci_dev *dev);
1345void pci_restore_msi_state(struct pci_dev *dev);
1346int pci_msi_enabled(void);
1347int pci_enable_msi(struct pci_dev *dev);
1348int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1349 int minvec, int maxvec);
1350static inline int pci_enable_msix_exact(struct pci_dev *dev,
1351 struct msix_entry *entries, int nvec)
1352{
1353 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1354 if (rc < 0)
1355 return rc;
1356 return 0;
1357}
1358int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1359 unsigned int max_vecs, unsigned int flags,
1360 const struct irq_affinity *affd);
1361
1362void pci_free_irq_vectors(struct pci_dev *dev);
1363int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1364const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1365int pci_irq_get_node(struct pci_dev *pdev, int vec);
1366
1367#else
1368static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1369static inline void pci_disable_msi(struct pci_dev *dev) { }
1370static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1371static inline void pci_disable_msix(struct pci_dev *dev) { }
1372static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1373static inline int pci_msi_enabled(void) { return 0; }
1374static inline int pci_enable_msi(struct pci_dev *dev)
1375{ return -ENOSYS; }
1376static inline int pci_enable_msix_range(struct pci_dev *dev,
1377 struct msix_entry *entries, int minvec, int maxvec)
1378{ return -ENOSYS; }
1379static inline int pci_enable_msix_exact(struct pci_dev *dev,
1380 struct msix_entry *entries, int nvec)
1381{ return -ENOSYS; }
1382
1383static inline int
1384pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1385 unsigned int max_vecs, unsigned int flags,
1386 const struct irq_affinity *aff_desc)
1387{
1388 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1389 return 1;
1390 return -ENOSPC;
1391}
1392
1393static inline void pci_free_irq_vectors(struct pci_dev *dev)
1394{
1395}
1396
1397static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1398{
1399 if (WARN_ON_ONCE(nr > 0))
1400 return -EINVAL;
1401 return dev->irq;
1402}
1403static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1404 int vec)
1405{
1406 return cpu_possible_mask;
1407}
1408
1409static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1410{
1411 return first_online_node;
1412}
1413#endif
1414
1415static inline int
1416pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1417 unsigned int max_vecs, unsigned int flags)
1418{
1419 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1420 NULL);
1421}
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1440 struct device_node *node,
1441 const u32 *intspec,
1442 unsigned int intsize,
1443 unsigned long *out_hwirq,
1444 unsigned int *out_type)
1445{
1446 const u32 intx = intspec[0];
1447
1448 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1449 return -EINVAL;
1450
1451 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1452 return 0;
1453}
1454
1455#ifdef CONFIG_PCIEPORTBUS
1456extern bool pcie_ports_disabled;
1457extern bool pcie_ports_auto;
1458#else
1459#define pcie_ports_disabled true
1460#define pcie_ports_auto false
1461#endif
1462
1463#ifdef CONFIG_PCIEASPM
1464bool pcie_aspm_support_enabled(void);
1465#else
1466static inline bool pcie_aspm_support_enabled(void) { return false; }
1467#endif
1468
1469#ifdef CONFIG_PCIEAER
1470void pci_no_aer(void);
1471bool pci_aer_available(void);
1472int pci_aer_init(struct pci_dev *dev);
1473#else
1474static inline void pci_no_aer(void) { }
1475static inline bool pci_aer_available(void) { return false; }
1476static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
1477#endif
1478
1479#ifdef CONFIG_PCIE_ECRC
1480void pcie_set_ecrc_checking(struct pci_dev *dev);
1481void pcie_ecrc_get_policy(char *str);
1482#else
1483static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1484static inline void pcie_ecrc_get_policy(char *str) { }
1485#endif
1486
1487#ifdef CONFIG_HT_IRQ
1488
1489int ht_create_irq(struct pci_dev *dev, int idx);
1490void ht_destroy_irq(unsigned int irq);
1491#endif
1492
1493#ifdef CONFIG_PCI_ATS
1494
1495void pci_ats_init(struct pci_dev *dev);
1496int pci_enable_ats(struct pci_dev *dev, int ps);
1497void pci_disable_ats(struct pci_dev *dev);
1498int pci_ats_queue_depth(struct pci_dev *dev);
1499#else
1500static inline void pci_ats_init(struct pci_dev *d) { }
1501static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1502static inline void pci_disable_ats(struct pci_dev *d) { }
1503static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1504#endif
1505
1506#ifdef CONFIG_PCIE_PTM
1507int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1508#else
1509static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1510{ return -EINVAL; }
1511#endif
1512
1513void pci_cfg_access_lock(struct pci_dev *dev);
1514bool pci_cfg_access_trylock(struct pci_dev *dev);
1515void pci_cfg_access_unlock(struct pci_dev *dev);
1516
1517
1518
1519
1520
1521
1522#ifdef CONFIG_PCI_DOMAINS
1523extern int pci_domains_supported;
1524int pci_get_new_domain_nr(void);
1525#else
1526enum { pci_domains_supported = 0 };
1527static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1528static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1529static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1530#endif
1531
1532
1533
1534
1535
1536
1537#ifdef CONFIG_PCI_DOMAINS_GENERIC
1538static inline int pci_domain_nr(struct pci_bus *bus)
1539{
1540 return bus->domain_nr;
1541}
1542#ifdef CONFIG_ACPI
1543int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1544#else
1545static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1546{ return 0; }
1547#endif
1548int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1549#endif
1550
1551
1552typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1553 unsigned int command_bits, u32 flags);
1554void pci_register_set_vga_state(arch_set_vga_state_t func);
1555
1556static inline int
1557pci_request_io_regions(struct pci_dev *pdev, const char *name)
1558{
1559 return pci_request_selected_regions(pdev,
1560 pci_select_bars(pdev, IORESOURCE_IO), name);
1561}
1562
1563static inline void
1564pci_release_io_regions(struct pci_dev *pdev)
1565{
1566 return pci_release_selected_regions(pdev,
1567 pci_select_bars(pdev, IORESOURCE_IO));
1568}
1569
1570static inline int
1571pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1572{
1573 return pci_request_selected_regions(pdev,
1574 pci_select_bars(pdev, IORESOURCE_MEM), name);
1575}
1576
1577static inline void
1578pci_release_mem_regions(struct pci_dev *pdev)
1579{
1580 return pci_release_selected_regions(pdev,
1581 pci_select_bars(pdev, IORESOURCE_MEM));
1582}
1583
1584#else
1585
1586static inline void pci_set_flags(int flags) { }
1587static inline void pci_add_flags(int flags) { }
1588static inline void pci_clear_flags(int flags) { }
1589static inline int pci_has_flag(int flag) { return 0; }
1590
1591
1592
1593
1594
1595
1596#define _PCI_NOP(o, s, t) \
1597 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1598 int where, t val) \
1599 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1600
1601#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1602 _PCI_NOP(o, word, u16 x) \
1603 _PCI_NOP(o, dword, u32 x)
1604_PCI_NOP_ALL(read, *)
1605_PCI_NOP_ALL(write,)
1606
1607static inline struct pci_dev *pci_get_device(unsigned int vendor,
1608 unsigned int device,
1609 struct pci_dev *from)
1610{ return NULL; }
1611
1612static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1613 unsigned int device,
1614 unsigned int ss_vendor,
1615 unsigned int ss_device,
1616 struct pci_dev *from)
1617{ return NULL; }
1618
1619static inline struct pci_dev *pci_get_class(unsigned int class,
1620 struct pci_dev *from)
1621{ return NULL; }
1622
1623#define pci_dev_present(ids) (0)
1624#define no_pci_devices() (1)
1625#define pci_dev_put(dev) do { } while (0)
1626
1627static inline void pci_set_master(struct pci_dev *dev) { }
1628static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1629static inline void pci_disable_device(struct pci_dev *dev) { }
1630static inline int pci_assign_resource(struct pci_dev *dev, int i)
1631{ return -EBUSY; }
1632static inline int __pci_register_driver(struct pci_driver *drv,
1633 struct module *owner)
1634{ return 0; }
1635static inline int pci_register_driver(struct pci_driver *drv)
1636{ return 0; }
1637static inline void pci_unregister_driver(struct pci_driver *drv) { }
1638static inline int pci_find_capability(struct pci_dev *dev, int cap)
1639{ return 0; }
1640static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1641 int cap)
1642{ return 0; }
1643static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1644{ return 0; }
1645
1646
1647static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1648static inline void pci_restore_state(struct pci_dev *dev) { }
1649static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1650{ return 0; }
1651static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1652{ return 0; }
1653static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1654 pm_message_t state)
1655{ return PCI_D0; }
1656static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1657 int enable)
1658{ return 0; }
1659
1660static inline struct resource *pci_find_resource(struct pci_dev *dev,
1661 struct resource *res)
1662{ return NULL; }
1663static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1664{ return -EIO; }
1665static inline void pci_release_regions(struct pci_dev *dev) { }
1666
1667static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1668
1669static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1670static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1671{ return 0; }
1672static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1673
1674static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1675{ return NULL; }
1676static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1677 unsigned int devfn)
1678{ return NULL; }
1679static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1680 unsigned int devfn)
1681{ return NULL; }
1682
1683static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1684static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1685static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1686
1687#define dev_is_pci(d) (false)
1688#define dev_is_pf(d) (false)
1689static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1690{ return false; }
1691#endif
1692
1693
1694
1695#include <asm/pci.h>
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1710 struct vm_area_struct *vma,
1711 enum pci_mmap_state mmap_state, int write_combine);
1712int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1713 struct vm_area_struct *vma,
1714 enum pci_mmap_state mmap_state, int write_combine);
1715
1716#ifndef arch_can_pci_mmap_wc
1717#define arch_can_pci_mmap_wc() 0
1718#endif
1719
1720#ifndef arch_can_pci_mmap_io
1721#define arch_can_pci_mmap_io() 0
1722#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1723#else
1724int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1725#endif
1726
1727#ifndef pci_root_bus_fwnode
1728#define pci_root_bus_fwnode(bus) NULL
1729#endif
1730
1731
1732
1733#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1734#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1735#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1736#define pci_resource_len(dev,bar) \
1737 ((pci_resource_start((dev), (bar)) == 0 && \
1738 pci_resource_end((dev), (bar)) == \
1739 pci_resource_start((dev), (bar))) ? 0 : \
1740 \
1741 (pci_resource_end((dev), (bar)) - \
1742 pci_resource_start((dev), (bar)) + 1))
1743
1744
1745
1746
1747
1748static inline void *pci_get_drvdata(struct pci_dev *pdev)
1749{
1750 return dev_get_drvdata(&pdev->dev);
1751}
1752
1753static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1754{
1755 dev_set_drvdata(&pdev->dev, data);
1756}
1757
1758
1759
1760
1761static inline const char *pci_name(const struct pci_dev *pdev)
1762{
1763 return dev_name(&pdev->dev);
1764}
1765
1766
1767
1768
1769
1770#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1771void pci_resource_to_user(const struct pci_dev *dev, int bar,
1772 const struct resource *rsrc,
1773 resource_size_t *start, resource_size_t *end);
1774#else
1775static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1776 const struct resource *rsrc, resource_size_t *start,
1777 resource_size_t *end)
1778{
1779 *start = rsrc->start;
1780 *end = rsrc->end;
1781}
1782#endif
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792struct pci_fixup {
1793 u16 vendor;
1794 u16 device;
1795 u32 class;
1796 unsigned int class_shift;
1797 void (*hook)(struct pci_dev *dev);
1798};
1799
1800enum pci_fixup_pass {
1801 pci_fixup_early,
1802 pci_fixup_header,
1803 pci_fixup_final,
1804 pci_fixup_enable,
1805 pci_fixup_resume,
1806 pci_fixup_suspend,
1807 pci_fixup_resume_early,
1808 pci_fixup_suspend_late,
1809};
1810
1811
1812#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1813 class_shift, hook) \
1814 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1815 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1816 = { vendor, device, class, class_shift, hook };
1817
1818#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1819 class_shift, hook) \
1820 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1821 hook, vendor, device, class, class_shift, hook)
1822#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1823 class_shift, hook) \
1824 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1825 hook, vendor, device, class, class_shift, hook)
1826#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1827 class_shift, hook) \
1828 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1829 hook, vendor, device, class, class_shift, hook)
1830#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1831 class_shift, hook) \
1832 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1833 hook, vendor, device, class, class_shift, hook)
1834#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1835 class_shift, hook) \
1836 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1837 resume##hook, vendor, device, class, \
1838 class_shift, hook)
1839#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1840 class_shift, hook) \
1841 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1842 resume_early##hook, vendor, device, \
1843 class, class_shift, hook)
1844#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1845 class_shift, hook) \
1846 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1847 suspend##hook, vendor, device, class, \
1848 class_shift, hook)
1849#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1850 class_shift, hook) \
1851 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1852 suspend_late##hook, vendor, device, \
1853 class, class_shift, hook)
1854
1855#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1856 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1857 hook, vendor, device, PCI_ANY_ID, 0, hook)
1858#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1859 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1860 hook, vendor, device, PCI_ANY_ID, 0, hook)
1861#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1862 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1863 hook, vendor, device, PCI_ANY_ID, 0, hook)
1864#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1865 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1866 hook, vendor, device, PCI_ANY_ID, 0, hook)
1867#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1868 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1869 resume##hook, vendor, device, \
1870 PCI_ANY_ID, 0, hook)
1871#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1872 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1873 resume_early##hook, vendor, device, \
1874 PCI_ANY_ID, 0, hook)
1875#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1876 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1877 suspend##hook, vendor, device, \
1878 PCI_ANY_ID, 0, hook)
1879#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1880 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1881 suspend_late##hook, vendor, device, \
1882 PCI_ANY_ID, 0, hook)
1883
1884#ifdef CONFIG_PCI_QUIRKS
1885void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1886int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1887int pci_dev_specific_enable_acs(struct pci_dev *dev);
1888#else
1889static inline void pci_fixup_device(enum pci_fixup_pass pass,
1890 struct pci_dev *dev) { }
1891static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1892 u16 acs_flags)
1893{
1894 return -ENOTTY;
1895}
1896static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1897{
1898 return -ENOTTY;
1899}
1900#endif
1901
1902void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1903void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1904void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1905int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1906int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1907 const char *name);
1908void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1909
1910extern int pci_pci_problems;
1911#define PCIPCI_FAIL 1
1912#define PCIPCI_TRITON 2
1913#define PCIPCI_NATOMA 4
1914#define PCIPCI_VIAETBF 8
1915#define PCIPCI_VSFX 16
1916#define PCIPCI_ALIMAGIK 32
1917#define PCIAGP_FAIL 64
1918
1919extern unsigned long pci_cardbus_io_size;
1920extern unsigned long pci_cardbus_mem_size;
1921extern u8 pci_dfl_cache_line_size;
1922extern u8 pci_cache_line_size;
1923
1924extern unsigned long pci_hotplug_io_size;
1925extern unsigned long pci_hotplug_mem_size;
1926extern unsigned long pci_hotplug_bus_size;
1927
1928
1929void pcibios_disable_device(struct pci_dev *dev);
1930void pcibios_set_master(struct pci_dev *dev);
1931int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1932 enum pcie_reset_state state);
1933int pcibios_add_device(struct pci_dev *dev);
1934void pcibios_release_device(struct pci_dev *dev);
1935void pcibios_penalize_isa_irq(int irq, int active);
1936int pcibios_alloc_irq(struct pci_dev *dev);
1937void pcibios_free_irq(struct pci_dev *dev);
1938
1939#ifdef CONFIG_HIBERNATE_CALLBACKS
1940extern struct dev_pm_ops pcibios_pm_ops;
1941#endif
1942
1943#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1944void __init pci_mmcfg_early_init(void);
1945void __init pci_mmcfg_late_init(void);
1946#else
1947static inline void pci_mmcfg_early_init(void) { }
1948static inline void pci_mmcfg_late_init(void) { }
1949#endif
1950
1951int pci_ext_cfg_avail(void);
1952
1953void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1954void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1955
1956#ifdef CONFIG_PCI_IOV
1957int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1958int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1959
1960int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1961void pci_disable_sriov(struct pci_dev *dev);
1962int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1963void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1964int pci_num_vf(struct pci_dev *dev);
1965int pci_vfs_assigned(struct pci_dev *dev);
1966int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1967int pci_sriov_get_totalvfs(struct pci_dev *dev);
1968resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1969#else
1970static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1971{
1972 return -ENOSYS;
1973}
1974static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1975{
1976 return -ENOSYS;
1977}
1978static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1979{ return -ENODEV; }
1980static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1981{
1982 return -ENOSYS;
1983}
1984static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1985 int id, int reset) { }
1986static inline void pci_disable_sriov(struct pci_dev *dev) { }
1987static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1988static inline int pci_vfs_assigned(struct pci_dev *dev)
1989{ return 0; }
1990static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1991{ return 0; }
1992static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1993{ return 0; }
1994static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1995{ return 0; }
1996#endif
1997
1998#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1999void pci_hp_create_module_link(struct pci_slot *pci_slot);
2000void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2001#endif
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014static inline int pci_pcie_cap(struct pci_dev *dev)
2015{
2016 return dev->pcie_cap;
2017}
2018
2019
2020
2021
2022
2023
2024
2025static inline bool pci_is_pcie(struct pci_dev *dev)
2026{
2027 return pci_pcie_cap(dev);
2028}
2029
2030
2031
2032
2033
2034static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2035{
2036 return dev->pcie_flags_reg;
2037}
2038
2039
2040
2041
2042
2043static inline int pci_pcie_type(const struct pci_dev *dev)
2044{
2045 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2046}
2047
2048static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2049{
2050 while (1) {
2051 if (!pci_is_pcie(dev))
2052 break;
2053 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2054 return dev;
2055 if (!dev->bus->self)
2056 break;
2057 dev = dev->bus->self;
2058 }
2059 return NULL;
2060}
2061
2062void pci_request_acs(void);
2063bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2064bool pci_acs_path_enabled(struct pci_dev *start,
2065 struct pci_dev *end, u16 acs_flags);
2066
2067#define PCI_VPD_LRDT 0x80
2068#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2069
2070
2071#define PCI_VPD_LTIN_ID_STRING 0x02
2072#define PCI_VPD_LTIN_RO_DATA 0x10
2073#define PCI_VPD_LTIN_RW_DATA 0x11
2074
2075#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2076#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2077#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2078
2079
2080#define PCI_VPD_STIN_END 0x0f
2081
2082#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2083
2084#define PCI_VPD_SRDT_TIN_MASK 0x78
2085#define PCI_VPD_SRDT_LEN_MASK 0x07
2086#define PCI_VPD_LRDT_TIN_MASK 0x7f
2087
2088#define PCI_VPD_LRDT_TAG_SIZE 3
2089#define PCI_VPD_SRDT_TAG_SIZE 1
2090
2091#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2092
2093#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2094#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2095#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2096#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2097
2098
2099
2100
2101
2102
2103
2104static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2105{
2106 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2107}
2108
2109
2110
2111
2112
2113
2114
2115static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2116{
2117 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2118}
2119
2120
2121
2122
2123
2124
2125
2126static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2127{
2128 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2129}
2130
2131
2132
2133
2134
2135
2136
2137static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2138{
2139 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2140}
2141
2142
2143
2144
2145
2146
2147
2148static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2149{
2150 return info_field[2];
2151}
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2176 unsigned int len, const char *kw);
2177
2178
2179#ifdef CONFIG_OF
2180struct device_node;
2181struct irq_domain;
2182void pci_set_of_node(struct pci_dev *dev);
2183void pci_release_of_node(struct pci_dev *dev);
2184void pci_set_bus_of_node(struct pci_bus *bus);
2185void pci_release_bus_of_node(struct pci_bus *bus);
2186struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2187
2188
2189struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2190
2191static inline struct device_node *
2192pci_device_to_OF_node(const struct pci_dev *pdev)
2193{
2194 return pdev ? pdev->dev.of_node : NULL;
2195}
2196
2197static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2198{
2199 return bus ? bus->dev.of_node : NULL;
2200}
2201
2202#else
2203static inline void pci_set_of_node(struct pci_dev *dev) { }
2204static inline void pci_release_of_node(struct pci_dev *dev) { }
2205static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2206static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2207static inline struct device_node *
2208pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2209static inline struct irq_domain *
2210pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2211#endif
2212
2213#ifdef CONFIG_ACPI
2214struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2215
2216void
2217pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2218#else
2219static inline struct irq_domain *
2220pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2221#endif
2222
2223#ifdef CONFIG_EEH
2224static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2225{
2226 return pdev->dev.archdata.edev;
2227}
2228#endif
2229
2230void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2231bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2232int pci_for_each_dma_alias(struct pci_dev *pdev,
2233 int (*fn)(struct pci_dev *pdev,
2234 u16 alias, void *data), void *data);
2235
2236
2237static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2238{
2239 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2240}
2241static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2242{
2243 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2244}
2245static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2246{
2247 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2248}
2249
2250
2251
2252
2253
2254
2255
2256static inline bool pci_ari_enabled(struct pci_bus *bus)
2257{
2258 return bus->self && bus->self->ari_enabled;
2259}
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2270{
2271 struct pci_dev *parent = pdev;
2272
2273 if (pdev->is_thunderbolt)
2274 return true;
2275
2276 while ((parent = pci_upstream_bridge(parent)))
2277 if (parent->is_thunderbolt)
2278 return true;
2279
2280 return false;
2281}
2282
2283
2284#include <linux/pci-dma-compat.h>
2285
2286#endif
2287