1#ifndef XAXIPMON_H
2#define XAXIPMON_H
3
4#ifdef __cplusplus
5extern "C" {
6#endif
7
8#include <stdint.h>
9#include <stdbool.h>
10
11
12#define XST_SUCCESS 0
13#define XST_FAILURE 1
14
15#ifndef TRUE
16#define TRUE 1
17#endif
18
19#ifndef FALSE
20#define FALSE 0
21#endif
22
23#ifndef NULL
24#define NULL 0
25#endif
26
27#define XAPM_GCC_HIGH_OFFSET 0x0000
28
29#define XAPM_GCC_LOW_OFFSET 0x0004
30
31#define XAPM_SI_HIGH_OFFSET 0x0020
32#define XAPM_SI_LOW_OFFSET 0x0024
33#define XAPM_SICR_OFFSET 0x0028
34
35#define XAPM_SR_OFFSET 0x002C
36#define XAPM_GIE_OFFSET 0x0030
37
38#define XAPM_IE_OFFSET 0x0034
39#define XAPM_IS_OFFSET 0x0038
40
41#define XAPM_MSR0_OFFSET 0x0044
42#define XAPM_MSR1_OFFSET 0x0048
43#define XAPM_MSR2_OFFSET 0x004C
44
45#define XAPM_MC0_OFFSET 0x0100
46#define XAPM_INC0_OFFSET 0x0104
47#define XAPM_RANGE0_OFFSET 0x0108
48#define XAPM_MC0LOGEN_OFFSET 0x010C
49
50#define XAPM_MC1_OFFSET 0x0110
51#define XAPM_INC1_OFFSET 0x0114
52#define XAPM_RANGE1_OFFSET 0x0118
53#define XAPM_MC1LOGEN_OFFSET 0x011C
54
55#define XAPM_MC2_OFFSET 0x0120
56#define XAPM_INC2_OFFSET 0x0124
57#define XAPM_RANGE2_OFFSET 0x0128
58#define XAPM_MC2LOGEN_OFFSET 0x012C
59
60#define XAPM_MC3_OFFSET 0x0130
61#define XAPM_INC3_OFFSET 0x0134
62#define XAPM_RANGE3_OFFSET 0x0138
63#define XAPM_MC3LOGEN_OFFSET 0x013C
64
65#define XAPM_MC4_OFFSET 0x0140
66#define XAPM_INC4_OFFSET 0x0144
67#define XAPM_RANGE4_OFFSET 0x0148
68#define XAPM_MC4LOGEN_OFFSET 0x014C
69
70#define XAPM_MC5_OFFSET 0x0150
71
72#define XAPM_INC5_OFFSET 0x0154
73#define XAPM_RANGE5_OFFSET 0x0158
74#define XAPM_MC5LOGEN_OFFSET 0x015C
75
76#define XAPM_MC6_OFFSET 0x0160
77
78#define XAPM_INC6_OFFSET 0x0164
79#define XAPM_RANGE6_OFFSET 0x0168
80#define XAPM_MC6LOGEN_OFFSET 0x016C
81
82#define XAPM_MC7_OFFSET 0x0170
83
84#define XAPM_INC7_OFFSET 0x0174
85#define XAPM_RANGE7_OFFSET 0x0178
86#define XAPM_MC7LOGEN_OFFSET 0x017C
87
88#define XAPM_MC8_OFFSET 0x0180
89
90#define XAPM_INC8_OFFSET 0x0184
91#define XAPM_RANGE8_OFFSET 0x0188
92#define XAPM_MC8LOGEN_OFFSET 0x018C
93
94#define XAPM_MC9_OFFSET 0x0190
95
96#define XAPM_INC9_OFFSET 0x0194
97#define XAPM_RANGE9_OFFSET 0x0198
98#define XAPM_MC9LOGEN_OFFSET 0x019C
99
100
101#define XAPM_MC10_OFFSET 0x01A0
102
103#define XAPM_MC11_OFFSET 0x01B0
104
105#define XAPM_MC12_OFFSET 0x0500
106
107#define XAPM_MC13_OFFSET 0x0510
108
109#define XAPM_MC14_OFFSET 0x0520
110
111#define XAPM_MC15_OFFSET 0x0530
112
113#define XAPM_MC16_OFFSET 0x0540
114
115#define XAPM_MC17_OFFSET 0x0550
116
117#define XAPM_MC18_OFFSET 0x0560
118
119#define XAPM_MC19_OFFSET 0x0570
120
121#define XAPM_MC20_OFFSET 0x0580
122
123#define XAPM_MC21_OFFSET 0x0590
124
125#define XAPM_MC22_OFFSET 0x05A0
126
127#define XAPM_MC23_OFFSET 0x05B0
128
129#define XAPM_MC24_OFFSET 0x0700
130
131#define XAPM_MC25_OFFSET 0x0710
132
133#define XAPM_MC26_OFFSET 0x0720
134
135#define XAPM_MC27_OFFSET 0x0730
136
137#define XAPM_MC28_OFFSET 0x0740
138
139#define XAPM_MC29_OFFSET 0x0750
140
141#define XAPM_MC30_OFFSET 0x0760
142
143#define XAPM_MC31_OFFSET 0x0770
144
145#define XAPM_MC32_OFFSET 0x0780
146
147#define XAPM_MC33_OFFSET 0x0790
148
149#define XAPM_MC34_OFFSET 0x07A0
150
151#define XAPM_MC35_OFFSET 0x07B0
152
153#define XAPM_MC36_OFFSET 0x0900
154
155#define XAPM_MC37_OFFSET 0x0910
156
157#define XAPM_MC38_OFFSET 0x0920
158
159#define XAPM_MC39_OFFSET 0x0930
160
161#define XAPM_MC40_OFFSET 0x0940
162
163#define XAPM_MC41_OFFSET 0x0950
164
165#define XAPM_MC42_OFFSET 0x0960
166
167#define XAPM_MC43_OFFSET 0x0970
168
169#define XAPM_MC44_OFFSET 0x0980
170
171#define XAPM_MC45_OFFSET 0x0990
172
173#define XAPM_MC46_OFFSET 0x09A0
174
175#define XAPM_MC47_OFFSET 0x09B0
176
177
178#define XAPM_SMC0_OFFSET 0x0200
179
180#define XAPM_SINC0_OFFSET 0x0204
181
182#define XAPM_SMC1_OFFSET 0x0210
183
184#define XAPM_SINC1_OFFSET 0x0214
185
186#define XAPM_SMC2_OFFSET 0x0220
187
188#define XAPM_SINC2_OFFSET 0x0224
189
190#define XAPM_SMC3_OFFSET 0x0230
191
192#define XAPM_SINC3_OFFSET 0x0234
193
194#define XAPM_SMC4_OFFSET 0x0240
195
196#define XAPM_SINC4_OFFSET 0x0244
197
198#define XAPM_SMC5_OFFSET 0x0250
199
200#define XAPM_SINC5_OFFSET 0x0254
201
202#define XAPM_SMC6_OFFSET 0x0260
203
204#define XAPM_SINC6_OFFSET 0x0264
205
206#define XAPM_SMC7_OFFSET 0x0270
207
208#define XAPM_SINC7_OFFSET 0x0274
209
210#define XAPM_SMC8_OFFSET 0x0280
211
212#define XAPM_SINC8_OFFSET 0x0284
213
214#define XAPM_SMC9_OFFSET 0x0290
215
216#define XAPM_SINC9_OFFSET 0x0294
217
218#define XAPM_SMC10_OFFSET 0x02A0
219
220#define XAPM_SMC11_OFFSET 0x02B0
221
222#define XAPM_SMC12_OFFSET 0x0600
223
224#define XAPM_SMC13_OFFSET 0x0610
225
226#define XAPM_SMC14_OFFSET 0x0620
227
228#define XAPM_SMC15_OFFSET 0x0630
229
230#define XAPM_SMC16_OFFSET 0x0640
231
232#define XAPM_SMC17_OFFSET 0x0650
233
234#define XAPM_SMC18_OFFSET 0x0660
235
236#define XAPM_SMC19_OFFSET 0x0670
237
238#define XAPM_SMC20_OFFSET 0x0680
239
240#define XAPM_SMC21_OFFSET 0x0690
241
242#define XAPM_SMC22_OFFSET 0x06A0
243
244#define XAPM_SMC23_OFFSET 0x06B0
245
246#define XAPM_SMC24_OFFSET 0x0800
247
248#define XAPM_SMC25_OFFSET 0x0810
249
250#define XAPM_SMC26_OFFSET 0x0820
251
252#define XAPM_SMC27_OFFSET 0x0830
253
254#define XAPM_SMC28_OFFSET 0x0840
255
256#define XAPM_SMC29_OFFSET 0x0850
257
258#define XAPM_SMC30_OFFSET 0x0860
259
260#define XAPM_SMC31_OFFSET 0x0870
261
262#define XAPM_SMC32_OFFSET 0x0880
263
264#define XAPM_SMC33_OFFSET 0x0890
265
266#define XAPM_SMC34_OFFSET 0x08A0
267
268#define XAPM_SMC35_OFFSET 0x08B0
269
270#define XAPM_SMC36_OFFSET 0x0A00
271
272#define XAPM_SMC37_OFFSET 0x0A10
273
274#define XAPM_SMC38_OFFSET 0x0A20
275
276#define XAPM_SMC39_OFFSET 0x0A30
277
278#define XAPM_SMC40_OFFSET 0x0A40
279
280#define XAPM_SMC41_OFFSET 0x0A50
281
282#define XAPM_SMC42_OFFSET 0x0A60
283
284#define XAPM_SMC43_OFFSET 0x0A70
285
286#define XAPM_SMC44_OFFSET 0x0A80
287
288#define XAPM_SMC45_OFFSET 0x0A90
289
290#define XAPM_SMC46_OFFSET 0x0AA0
291
292#define XAPM_SMC47_OFFSET 0x0AB0
293
294
295#define XAPM_CTL_OFFSET 0x0300
296
297#define XAPM_ID_OFFSET 0x0304
298
299#define XAPM_IDMASK_OFFSET 0x0308
300
301#define XAPM_RID_OFFSET 0x030C
302
303#define XAPM_RIDMASK_OFFSET 0x0310
304
305#define XAPM_FEC_OFFSET 0x0400
306
307
308#define XAPM_SWD_OFFSET 0x0404
309
310
311#define XAPM_SICR_MCNTR_RST_MASK 0x00000100
312
313#define XAPM_SICR_LOAD_MASK 0x00000002
314
315
316#define XAPM_SICR_ENABLE_MASK 0x00000001
317
318#define XAPM_IXR_MC9_OVERFLOW_MASK 0x00001000
319
320#define XAPM_IXR_MC8_OVERFLOW_MASK 0x00000800
321
322#define XAPM_IXR_MC7_OVERFLOW_MASK 0x00000400
323
324#define XAPM_IXR_MC6_OVERFLOW_MASK 0x00000200
325
326#define XAPM_IXR_MC5_OVERFLOW_MASK 0x00000100
327
328#define XAPM_IXR_MC4_OVERFLOW_MASK 0x00000080
329
330#define XAPM_IXR_MC3_OVERFLOW_MASK 0x00000040
331
332#define XAPM_IXR_MC2_OVERFLOW_MASK 0x00000020
333
334#define XAPM_IXR_MC1_OVERFLOW_MASK 0x00000010
335
336#define XAPM_IXR_MC0_OVERFLOW_MASK 0x00000008
337
338#define XAPM_IXR_FIFO_FULL_MASK 0x00000004
339
340#define XAPM_IXR_SIC_OVERFLOW_MASK 0x00000002
341
342#define XAPM_IXR_GCC_OVERFLOW_MASK 0x00000001
343
344#define XAPM_IXR_ALL_MASK (XAPM_IXR_SIC_OVERFLOW_MASK | \
345 XAPM_IXR_GCC_OVERFLOW_MASK | \
346 XAPM_IXR_FIFO_FULL_MASK | \
347 XAPM_IXR_MC0_OVERFLOW_MASK | \
348 XAPM_IXR_MC1_OVERFLOW_MASK | \
349 XAPM_IXR_MC2_OVERFLOW_MASK | \
350 XAPM_IXR_MC3_OVERFLOW_MASK | \
351 XAPM_IXR_MC4_OVERFLOW_MASK | \
352 XAPM_IXR_MC5_OVERFLOW_MASK | \
353 XAPM_IXR_MC6_OVERFLOW_MASK | \
354 XAPM_IXR_MC7_OVERFLOW_MASK | \
355 XAPM_IXR_MC8_OVERFLOW_MASK | \
356 XAPM_IXR_MC9_OVERFLOW_MASK)
357
358#define XAPM_CR_FIFO_RESET_MASK 0x02000000
359
360#define XAPM_CR_MUXSEL_MASK 0x01000000
361
362#define XAPM_CR_GCC_RESET_MASK 0x00020000
363
364
365#define XAPM_CR_GCC_ENABLE_MASK 0x00010000
366
367
368#define XAPM_CR_EVTLOG_EXTTRIGGER_MASK 0x00000200
369
370
371#define XAPM_CR_EVENTLOG_ENABLE_MASK 0x00000100
372
373#define XAPM_CR_RDLATENCY_END_MASK 0x00000080
374
375
376#define XAPM_CR_RDLATENCY_START_MASK 0x00000040
377
378
379#define XAPM_CR_WRLATENCY_END_MASK 0x00000020
380
381
382#define XAPM_CR_WRLATENCY_START_MASK 0x00000010
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384
385#define XAPM_CR_IDFILTER_ENABLE_MASK 0x00000008
386
387#define XAPM_CR_MCNTR_EXTTRIGGER_MASK 0x00000004
388
389
390
391#define XAPM_CR_MCNTR_RESET_MASK 0x00000002
392
393
394#define XAPM_CR_MCNTR_ENABLE_MASK 0x00000001
395
396
397
398#define XAPM_ID_RID_MASK 0xFFFF0000
399
400#define XAPM_ID_WID_MASK 0x0000FFFF
401
402#define XAPM_MASKID_RID_MASK 0xFFFF0000
403
404#define XAPM_MASKID_WID_MASK 0x0000FFFF
405
406
407#define XAPM_MAX_COUNTERS 10
408#define XAPM_MAX_COUNTERS_PROFILE 48
409
410
411#define XAPM_METRIC_COUNTER_0 0
412#define XAPM_METRIC_COUNTER_1 1
413#define XAPM_METRIC_COUNTER_2 2
414#define XAPM_METRIC_COUNTER_3 3
415#define XAPM_METRIC_COUNTER_4 4
416#define XAPM_METRIC_COUNTER_5 5
417#define XAPM_METRIC_COUNTER_6 6
418#define XAPM_METRIC_COUNTER_7 7
419#define XAPM_METRIC_COUNTER_8 8
420#define XAPM_METRIC_COUNTER_9 9
421
422#define XAPM_INCREMENTER_0 0
423#define XAPM_INCREMENTER_1 1
424#define XAPM_INCREMENTER_2 2
425#define XAPM_INCREMENTER_3 3
426#define XAPM_INCREMENTER_4 4
427#define XAPM_INCREMENTER_5 5
428#define XAPM_INCREMENTER_6 6
429#define XAPM_INCREMENTER_7 7
430#define XAPM_INCREMENTER_8 8
431#define XAPM_INCREMENTER_9 9
432
433#define XAPM_METRIC_SET_0 0
434#define XAPM_METRIC_SET_1 1
435#define XAPM_METRIC_SET_2 2
436#define XAPM_METRIC_SET_3 3
437#define XAPM_METRIC_SET_4 4
438#define XAPM_METRIC_SET_5 5
439#define XAPM_METRIC_SET_6 6
440#define XAPM_METRIC_SET_7 7
441#define XAPM_METRIC_SET_8 8
442#define XAPM_METRIC_SET_9 9
443#define XAPM_METRIC_SET_10 10
444#define XAPM_METRIC_SET_11 11
445#define XAPM_METRIC_SET_12 12
446#define XAPM_METRIC_SET_13 13
447#define XAPM_METRIC_SET_14 14
448#define XAPM_METRIC_SET_15 15
449#define XAPM_METRIC_SET_16 16
450#define XAPM_METRIC_SET_17 17
451#define XAPM_METRIC_SET_18 18
452#define XAPM_METRIC_SET_19 19
453#define XAPM_METRIC_SET_20 20
454#define XAPM_METRIC_SET_21 21
455#define XAPM_METRIC_SET_22 22
456#define XAPM_METRIC_SET_30 30
457
458#define XAPM_MAX_AGENTS 8
459
460#define XAPM_FLAG_WRADDR 0x00000001
461#define XAPM_FLAG_FIRSTWR 0x00000002
462#define XAPM_FLAG_LASTWR 0x00000004
463#define XAPM_FLAG_RESPONSE 0x00000008
464#define XAPM_FLAG_RDADDR 0x00000010
465#define XAPM_FLAG_FIRSTRD 0x00000020
466#define XAPM_FLAG_LASTRD 0x00000040
467#define XAPM_FLAG_SWDATA 0x00010000
468#define XAPM_FLAG_EVENT 0x00020000
469#define XAPM_FLAG_EVNTSTOP 0x00040000
470#define XAPM_FLAG_EVNTSTART 0x00080000
471#define XAPM_FLAG_GCCOVF 0x00100000
472
473#define XAPM_FLAG_SCLAPSE 0x00200000
474#define XAPM_FLAG_MC0 0x00400000
475#define XAPM_FLAG_MC1 0x00800000
476#define XAPM_FLAG_MC2 0x01000000
477#define XAPM_FLAG_MC3 0x02000000
478#define XAPM_FLAG_MC4 0x04000000
479#define XAPM_FLAG_MC5 0x08000000
480#define XAPM_FLAG_MC6 0x10000000
481#define XAPM_FLAG_MC7 0x20000000
482#define XAPM_FLAG_MC8 0x40000000
483#define XAPM_FLAG_MC9 0x80000000
484
485#define XAPM_LATENCY_ADDR_ISSUE 0
486
487#define XAPM_LATENCY_ADDR_ACCEPT 1
488
489#define XAPM_LATENCY_LASTRD 0
490
491#define XAPM_LATENCY_LASTWR 0
492
493#define XAPM_LATENCY_FIRSTRD 1
494
495#define XAPM_LATENCY_FIRSTWR 1
496
497
498#define XAPM_MODE_TRACE 2
499
500#define XAPM_MODE_PROFILE 1
501
502#define XAPM_MODE_ADVANCED 0
503
504typedef unsigned char u8;
505typedef uint16_t u16;
506typedef uint32_t u32;
507typedef unsigned long ulong;
508
509ulong baseaddr;
510
511struct xapm_param {
512 u32 mode;
513 u32 maxslots;
514 u32 eventcnt;
515 u32 eventlog;
516 u32 sampledcnt;
517 u32 numcounters;
518 u32 metricwidth;
519 u32 sampledwidth;
520 u32 globalcntwidth;
521 u32 scalefactor;
522 u32 isr;
523 bool is_32bit_filter;
524};
525
526static struct xapm_param *params;
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542
543#define readreg(baseaddr, regoffset) \
544 (*(u32 *)(baseaddr + regoffset))
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563#define writereg(baseaddr, regoffset, data) \
564 (*(u32 *)(baseaddr + regoffset) = data)
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574
575#define intrglobalenable() \
576 writereg(baseaddr, XAPM_GIE_OFFSET, 1)
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588#define intrglobaldisable() \
589 writereg(baseaddr, XAPM_GIE_OFFSET, 0)
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607#define intrenable(mask) \
608 writereg(baseaddr, XAPM_IE_OFFSET, readreg(baseaddr, \
609 XAPM_IE_OFFSET) | mask);
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629#define intrdisable(mask) \
630 writereg(baseaddr, XAPM_IE_OFFSET, readreg(baseaddr, \
631 XAPM_IE_OFFSET) | mask);
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648#define intrclear(mask) \
649 writereg(baseaddr, XAPM_IS_OFFSET, readreg(baseaddr, \
650 XAPM_IS_OFFSET) | mask);
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664#define intrgetstatus() (params->isr)
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677#define intrhwgetstatus() (params->isr)
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688#define enablegcc() \
689 writereg(baseaddr, XAPM_CTL_OFFSET, readreg(baseaddr, \
690 XAPM_CTL_OFFSET) | XAPM_CR_GCC_ENABLE_MASK);
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701#define disablegcc() \
702 writereg(baseaddr, XAPM_CTL_OFFSET, readreg(baseaddr, \
703 XAPM_CTL_OFFSET) & ~(XAPM_CR_GCC_ENABLE_MASK));
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718#define enableflag(flag) \
719 writereg(baseaddr, XAPM_FEC_OFFSET, \
720 readreg(baseaddr, XAPM_FEC_OFFSET) | flag);
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734#define disableflag(flag) \
735 writereg(baseaddr, XAPM_FEC_OFFSET, \
736 readreg(baseaddr, XAPM_FEC_OFFSET) & ~(flag));
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748#define loadsic() \
749 writereg(baseaddr, XAPM_SICR_OFFSET, XAPM_SICR_LOAD_MASK)
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761#define enablesic() \
762 writereg(baseaddr, XAPM_SICR_OFFSET, XAPM_SICR_ENABLE_MASK)
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773#define disablesic() \
774 writereg(baseaddr, XAPM_SICR_OFFSET, \
775 readreg(baseaddr, XAPM_SICR_OFFSET) & ~(XAPM_SICR_ENABLE_MASK));
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786#define enablemcreset() \
787 writereg(baseaddr, XAPM_SICR_OFFSET, XAPM_SICR_MCNTR_RST_MASK);
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798#define disablemcreset() \
799 writereg(baseaddr, XAPM_SICR_OFFSET, \
800 readreg(baseaddr, XAPM_SICR_OFFSET) & ~(XAPM_SICR_MCNTR_RST_MASK));
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811#define enableidfilter() \
812 writereg(baseaddr, XAPM_CTL_OFFSET, readreg(baseaddr, \
813 XAPM_CTL_OFFSET) | XAPM_CR_IDFILTER_ENABLE_MASK);
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824#define disableidfilter() \
825 writereg(baseaddr, XAPM_CTL_OFFSET, readreg(baseaddr, \
826 XAPM_CTL_OFFSET) & ~(XAPM_CR_IDFILTER_ENABLE_MASK));
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842#define samplemetrics() readreg(baseaddr, XAPM_SR_OFFSET);
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847int resetmetriccounter(void);
848
849void resetglobalclkcounter(void);
850
851int resetfifo(void);
852
853void setincrementerrange(u8 incrementer, u16 rangehigh, u16 rangelow);
854
855void getincrementerrange(u8 incrementer, u16 *rangehigh, u16 *rangelow);
856
857void setsampleinterval(u32 sampleinterval);
858
859void getsampleinterval(u32 *sampleinterval);
860
861int setmetrics(u8 slot, u8 metrics, u8 counter);
862
863int getmetrics(u8 counter, u8 *metrics, u8 *slot);
864void getglobalclkcounter(u32 *cnthigh, u32 *cntlow);
865
866u32 getmetriccounter(u32 counter);
867
868u32 getsampledmetriccounter(u32 counter);
869
870u32 getincrementer(u32 incrementer);
871
872u32 getsampledincrementer(u32 incrementer);
873
874void setswdatareg(u32 swdata);
875
876u32 getswdatareg(void);
877
878int starteventlog(u32 flagenables);
879
880int stopeventlog(void);
881
882int startcounters(u32 sampleinterval);
883
884int stopcounters(void);
885
886void enablemetricscounter(void);
887
888void disablemetricscounter(void);
889
890void setlogenableranges(u32 counter, u16 rangehigh, u16 rangelow);
891
892void getlogenableranges(u32 counter, u16 *rangehigh, u16 *rangelow);
893
894void enableeventlog(void);
895
896void enablemctrigger(void);
897
898void disablemctrigger(void);
899
900void enableeventlogtrigger(void);
901
902void disableeventlogtrigger(void);
903
904const char *getmetricname(u8 metrics);
905
906void setwriteid(u32 writeid);
907
908void setreadid(u32 readid);
909
910u32 getwriteid(void);
911
912u32 getreadid(void);
913
914void setwrlatencystart(u8 param);
915
916void setwrlatencyend(u8 param);
917
918void setrdlatencystart(u8 param);
919
920void setrdlatencyend(u8 param);
921
922u8 getwrlatencystart(void);
923
924u8 getwrlatencyend(void);
925
926u8 getrdlatencystart(void);
927
928u8 getrdlatencyend(void);
929
930void setwriteidmask(u32 wrmask);
931
932void setreadidmask(u32 rdmask);
933
934u32 getwriteidmask(void);
935
936u32 getreadidmask(void);
937
938
939#ifdef __cplusplus
940}
941#endif
942
943#endif
944