LXR linux/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

   1/***********************license start***************
   2 * Author: Cavium Networks
   3 *
   4 * Contact: support@caviumnetworks.com
   5 * This file is part of the OCTEON SDK
   6 *
   7 * Copyright (C) 2003-2018 Cavium, Inc.
   8 *
   9 * This file is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License, Version 2, as
  11 * published by the Free Software Foundation.
  12 *
  13 * This file is distributed in the hope that it will be useful, but
  14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16 * NONINFRINGEMENT.  See the GNU General Public License for more
  17 * details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this file; if not, write to the Free Software
  21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22 * or visit http://www.gnu.org/licenses/.
  23 *
  24 * This file may also be available under a different license from Cavium.
  25 * Contact Cavium Networks for more information
  26 ***********************license end**************************************/
  27
  28/*
  29 * Functions for RGMII/GMII/MII initialization, configuration,
  30 * and monitoring.
  31 */
  32#include <asm/octeon/octeon.h>
  33
  34#include <asm/octeon/cvmx-config.h>
  35
  36#include <asm/octeon/cvmx-pko.h>
  37#include <asm/octeon/cvmx-helper.h>
  38#include <asm/octeon/cvmx-helper-board.h>
  39
  40#include <asm/octeon/cvmx-npi-defs.h>
  41#include <asm/octeon/cvmx-gmxx-defs.h>
  42#include <asm/octeon/cvmx-asxx-defs.h>
  43#include <asm/octeon/cvmx-dbg-defs.h>
  44
  45/**
  46 * Probe RGMII ports and determine the number present
  47 *
  48 * @interface: Interface to probe
  49 *
  50 * Returns Number of RGMII/GMII/MII ports (0-4).
  51 */
  52int __cvmx_helper_rgmii_probe(int interface)
  53{
  54        int num_ports = 0;
  55        union cvmx_gmxx_inf_mode mode;
  56        mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
  57
  58        if (mode.s.type) {
  59                if (OCTEON_IS_MODEL(OCTEON_CN38XX)
  60                    || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
  61                        cvmx_dprintf("ERROR: RGMII initialize called in "
  62                                     "SPI interface\n");
  63                } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
  64                           || OCTEON_IS_MODEL(OCTEON_CN30XX)
  65                           || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
  66                        /*
  67                         * On these chips "type" says we're in
  68                         * GMII/MII mode. This limits us to 2 ports
  69                         */
  70                        num_ports = 2;
  71                } else {
  72                        cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
  73                                     __func__);
  74                }
  75        } else {
  76                if (OCTEON_IS_MODEL(OCTEON_CN38XX)
  77                    || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
  78                        num_ports = 4;
  79                } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
  80                           || OCTEON_IS_MODEL(OCTEON_CN30XX)
  81                           || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
  82                        num_ports = 3;
  83                } else {
  84                        cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
  85                                     __func__);
  86                }
  87        }
  88        return num_ports;
  89}
  90
  91/**
  92 * Put an RGMII interface in loopback mode. Internal packets sent
  93 * out will be received back again on the same port. Externally
  94 * received packets will echo back out.
  95 *
  96 * @port:   IPD port number to loop.
  97 */
  98void cvmx_helper_rgmii_internal_loopback(int port)
  99{
 100        int interface = (port >> 4) & 1;
 101        int index = port & 0xf;
 102        uint64_t tmp;
 103
 104        union cvmx_gmxx_prtx_cfg gmx_cfg;
 105        gmx_cfg.u64 = 0;
 106        gmx_cfg.s.duplex = 1;
 107        gmx_cfg.s.slottime = 1;
 108        gmx_cfg.s.speed = 1;
 109        cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
 110        cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
 111        cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
 112        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
 113        tmp = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
 114        cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp);
 115        tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface));
 116        cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp);
 117        tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface));
 118        cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp);
 119        gmx_cfg.s.en = 1;
 120        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
 121}
 122
 123/**
 124 * Workaround ASX setup errata with CN38XX pass1
 125 *
 126 * @interface: Interface to setup
 127 * @port:      Port to setup (0..3)
 128 * @cpu_clock_hz:
 129 *                  Chip frequency in Hertz
 130 *
 131 * Returns Zero on success, negative on failure
 132 */
 133static int __cvmx_helper_errata_asx_pass1(int interface, int port,
 134                                          int cpu_clock_hz)
 135{
 136        /* Set hi water mark as per errata GMX-4 */
 137        if (cpu_clock_hz >= 325000000 && cpu_clock_hz < 375000000)
 138                cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12);
 139        else if (cpu_clock_hz >= 375000000 && cpu_clock_hz < 437000000)
 140                cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11);
 141        else if (cpu_clock_hz >= 437000000 && cpu_clock_hz < 550000000)
 142                cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10);
 143        else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000)
 144                cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9);
 145        else
 146                cvmx_dprintf("Illegal clock frequency (%d). "
 147                        "CVMX_ASXX_TX_HI_WATERX not set\n", cpu_clock_hz);
 148        return 0;
 149}
 150
 151/**
 152 * Configure all of the ASX, GMX, and PKO registers required
 153 * to get RGMII to function on the supplied interface.
 154 *
 155 * @interface: PKO Interface to configure (0 or 1)
 156 *
 157 * Returns Zero on success
 158 */
 159int __cvmx_helper_rgmii_enable(int interface)
 160{
 161        int num_ports = cvmx_helper_ports_on_interface(interface);
 162        int port;
 163        struct cvmx_sysinfo *sys_info_ptr = cvmx_sysinfo_get();
 164        union cvmx_gmxx_inf_mode mode;
 165        union cvmx_asxx_tx_prt_en asx_tx;
 166        union cvmx_asxx_rx_prt_en asx_rx;
 167
 168        mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
 169
 170        if (mode.s.en == 0)
 171                return -1;
 172        if ((OCTEON_IS_MODEL(OCTEON_CN38XX) ||
 173             OCTEON_IS_MODEL(OCTEON_CN58XX)) && mode.s.type == 1)
 174                /* Ignore SPI interfaces */
 175                return -1;
 176
 177        /* Configure the ASX registers needed to use the RGMII ports */
 178        asx_tx.u64 = 0;
 179        asx_tx.s.prt_en = cvmx_build_mask(num_ports);
 180        cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64);
 181
 182        asx_rx.u64 = 0;
 183        asx_rx.s.prt_en = cvmx_build_mask(num_ports);
 184        cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64);
 185
 186        /* Configure the GMX registers needed to use the RGMII ports */
 187        for (port = 0; port < num_ports; port++) {
 188                /* Setting of CVMX_GMXX_TXX_THRESH has been moved to
 189                   __cvmx_helper_setup_gmx() */
 190
 191                if (cvmx_octeon_is_pass1())
 192                        __cvmx_helper_errata_asx_pass1(interface, port,
 193                                                       sys_info_ptr->
 194                                                       cpu_clock_hz);
 195                else {
 196                        /*
 197                         * Configure more flexible RGMII preamble
 198                         * checking. Pass 1 doesn't support this
 199                         * feature.
 200                         */
 201                        union cvmx_gmxx_rxx_frm_ctl frm_ctl;
 202                        frm_ctl.u64 =
 203                            cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL
 204                                          (port, interface));
 205                        /* New field, so must be compile time */
 206                        frm_ctl.s.pre_free = 1;
 207                        cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface),
 208                                       frm_ctl.u64);
 209                }
 210
 211                /*
 212                 * Each pause frame transmitted will ask for about 10M
 213                 * bit times before resume.  If buffer space comes
 214                 * available before that time has expired, an XON
 215                 * pause frame (0 time) will be transmitted to restart
 216                 * the flow.
 217                 */
 218                cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface),
 219                               20000);
 220                cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL
 221                               (port, interface), 19000);
 222
 223                if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
 224                        cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface),
 225                                       16);
 226                        cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface),
 227                                       16);
 228                } else {
 229                        cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface),
 230                                       24);
 231                        cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface),
 232                                       24);
 233                }
 234        }
 235
 236        __cvmx_helper_setup_gmx(interface, num_ports);
 237
 238        /* enable the ports now */
 239        for (port = 0; port < num_ports; port++) {
 240                union cvmx_gmxx_prtx_cfg gmx_cfg;
 241
 242                gmx_cfg.u64 =
 243                    cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface));
 244                gmx_cfg.s.en = 1;
 245                cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface),
 246                               gmx_cfg.u64);
 247        }
 248        __cvmx_interrupt_asxx_enable(interface);
 249        __cvmx_interrupt_gmxx_enable(interface);
 250
 251        return 0;
 252}
 253
 254/**
 255 * Return the link state of an IPD/PKO port as returned by
 256 * auto negotiation. The result of this function may not match
 257 * Octeon's link config if auto negotiation has changed since
 258 * the last call to cvmx_helper_link_set().
 259 *
 260 * @ipd_port: IPD/PKO port to query
 261 *
 262 * Returns Link state
 263 */
 264cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port)
 265{
 266        int interface = cvmx_helper_get_interface_num(ipd_port);
 267        int index = cvmx_helper_get_interface_index_num(ipd_port);
 268        union cvmx_asxx_prt_loop asxx_prt_loop;
 269
 270        asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
 271        if (asxx_prt_loop.s.int_loop & (1 << index)) {
 272                /* Force 1Gbps full duplex on internal loopback */
 273                cvmx_helper_link_info_t result;
 274                result.u64 = 0;
 275                result.s.full_duplex = 1;
 276                result.s.link_up = 1;
 277                result.s.speed = 1000;
 278                return result;
 279        } else
 280                return __cvmx_helper_board_link_get(ipd_port);
 281}
 282
 283/**
 284 * Configure an IPD/PKO port for the specified link state. This
 285 * function does not influence auto negotiation at the PHY level.
 286 * The passed link state must always match the link state returned
 287 * by cvmx_helper_link_get().
 288 *
 289 * @ipd_port:  IPD/PKO port to configure
 290 * @link_info: The new link state
 291 *
 292 * Returns Zero on success, negative on failure
 293 */
 294int __cvmx_helper_rgmii_link_set(int ipd_port,
 295                                 cvmx_helper_link_info_t link_info)
 296{
 297        int result = 0;
 298        int interface = cvmx_helper_get_interface_num(ipd_port);
 299        int index = cvmx_helper_get_interface_index_num(ipd_port);
 300        union cvmx_gmxx_prtx_cfg original_gmx_cfg;
 301        union cvmx_gmxx_prtx_cfg new_gmx_cfg;
 302        union cvmx_pko_mem_queue_qos pko_mem_queue_qos;
 303        union cvmx_pko_mem_queue_qos pko_mem_queue_qos_save[16];
 304        union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp;
 305        union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp_save;
 306        int i;
 307
 308        /* Ignore speed sets in the simulator */
 309        if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
 310                return 0;
 311
 312        /* Read the current settings so we know the current enable state */
 313        original_gmx_cfg.u64 =
 314            cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
 315        new_gmx_cfg = original_gmx_cfg;
 316
 317        /* Disable the lowest level RX */
 318        cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
 319                       cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) &
 320                                     ~(1 << index));
 321
 322        memset(pko_mem_queue_qos_save, 0, sizeof(pko_mem_queue_qos_save));
 323        /* Disable all queues so that TX should become idle */
 324        for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) {
 325                int queue = cvmx_pko_get_base_queue(ipd_port) + i;
 326                cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);
 327                pko_mem_queue_qos.u64 = cvmx_read_csr(CVMX_PKO_MEM_QUEUE_QOS);
 328                pko_mem_queue_qos.s.pid = ipd_port;
 329                pko_mem_queue_qos.s.qid = queue;
 330                pko_mem_queue_qos_save[i] = pko_mem_queue_qos;
 331                pko_mem_queue_qos.s.qos_mask = 0;
 332                cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos.u64);
 333        }
 334
 335        /* Disable backpressure */
 336        gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
 337        gmx_tx_ovr_bp_save = gmx_tx_ovr_bp;
 338        gmx_tx_ovr_bp.s.bp &= ~(1 << index);
 339        gmx_tx_ovr_bp.s.en |= 1 << index;
 340        cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64);
 341        cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
 342
 343        /*
 344         * Poll the GMX state machine waiting for it to become
 345         * idle. Preferably we should only change speed when it is
 346         * idle. If it doesn't become idle we will still do the speed
 347         * change, but there is a slight chance that GMX will
 348         * lockup.
 349         */
 350        cvmx_write_csr(CVMX_NPI_DBG_SELECT,
 351                       interface * 0x800 + index * 0x100 + 0x880);
 352        CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 7,
 353                        ==, 0, 10000);
 354        CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 0xf,
 355                        ==, 0, 10000);
 356
 357        /* Disable the port before we make any changes */
 358        new_gmx_cfg.s.en = 0;
 359        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
 360        cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
 361
 362        /* Set full/half duplex */
 363        if (cvmx_octeon_is_pass1())
 364                /* Half duplex is broken for 38XX Pass 1 */
 365                new_gmx_cfg.s.duplex = 1;
 366        else if (!link_info.s.link_up)
 367                /* Force full duplex on down links */
 368                new_gmx_cfg.s.duplex = 1;
 369        else
 370                new_gmx_cfg.s.duplex = link_info.s.full_duplex;
 371
 372        /* Set the link speed. Anything unknown is set to 1Gbps */
 373        if (link_info.s.speed == 10) {
 374                new_gmx_cfg.s.slottime = 0;
 375                new_gmx_cfg.s.speed = 0;
 376        } else if (link_info.s.speed == 100) {
 377                new_gmx_cfg.s.slottime = 0;
 378                new_gmx_cfg.s.speed = 0;
 379        } else {
 380                new_gmx_cfg.s.slottime = 1;
 381                new_gmx_cfg.s.speed = 1;
 382        }
 383
 384        /* Adjust the clocks */
 385        if (link_info.s.speed == 10) {
 386                cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 50);
 387                cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);
 388                cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
 389        } else if (link_info.s.speed == 100) {
 390                cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 5);
 391                cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);
 392                cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
 393        } else {
 394                cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
 395                cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
 396                cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
 397        }
 398
 399        if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
 400                if ((link_info.s.speed == 10) || (link_info.s.speed == 100)) {
 401                        union cvmx_gmxx_inf_mode mode;
 402                        mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
 403
 404        /*
 405         * Port  .en  .type  .p0mii  Configuration
 406         * ----  ---  -----  ------  -----------------------------------------
 407         *  X      0     X      X    All links are disabled.
 408         *  0      1     X      0    Port 0 is RGMII
 409         *  0      1     X      1    Port 0 is MII
 410         *  1      1     0      X    Ports 1 and 2 are configured as RGMII ports.
 411         *  1      1     1      X    Port 1: GMII/MII; Port 2: disabled. GMII or
 412         *                           MII port is selected by GMX_PRT1_CFG[SPEED].
 413         */
 414
 415                        /* In MII mode, CLK_CNT = 1. */
 416                        if (((index == 0) && (mode.s.p0mii == 1))
 417                            || ((index != 0) && (mode.s.type == 1))) {
 418                                cvmx_write_csr(CVMX_GMXX_TXX_CLK
 419                                               (index, interface), 1);
 420                        }
 421                }
 422        }
 423
 424        /* Do a read to make sure all setup stuff is complete */
 425        cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
 426
 427        /* Save the new GMX setting without enabling the port */
 428        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
 429
 430        /* Enable the lowest level RX */
 431        cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
 432                       cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) | (1 <<
 433                                                                        index));
 434
 435        /* Re-enable the TX path */
 436        for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) {
 437                int queue = cvmx_pko_get_base_queue(ipd_port) + i;
 438                cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);
 439                cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS,
 440                               pko_mem_queue_qos_save[i].u64);
 441        }
 442
 443        /* Restore backpressure */
 444        cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp_save.u64);
 445
 446        /* Restore the GMX enable state. Port config is complete */
 447        new_gmx_cfg.s.en = original_gmx_cfg.s.en;
 448        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
 449
 450        return result;
 451}
 452
 453/**
 454 * Configure a port for internal and/or external loopback. Internal loopback
 455 * causes packets sent by the port to be received by Octeon. External loopback
 456 * causes packets received from the wire to sent out again.
 457 *
 458 * @ipd_port: IPD/PKO port to loopback.
 459 * @enable_internal:
 460 *                 Non zero if you want internal loopback
 461 * @enable_external:
 462 *                 Non zero if you want external loopback
 463 *
 464 * Returns Zero on success, negative on failure.
 465 */
 466int __cvmx_helper_rgmii_configure_loopback(int ipd_port, int enable_internal,
 467                                           int enable_external)
 468{
 469        int interface = cvmx_helper_get_interface_num(ipd_port);
 470        int index = cvmx_helper_get_interface_index_num(ipd_port);
 471        int original_enable;
 472        union cvmx_gmxx_prtx_cfg gmx_cfg;
 473        union cvmx_asxx_prt_loop asxx_prt_loop;
 474
 475        /* Read the current enable state and save it */
 476        gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
 477        original_enable = gmx_cfg.s.en;
 478        /* Force port to be disabled */
 479        gmx_cfg.s.en = 0;
 480        if (enable_internal) {
 481                /* Force speed if we're doing internal loopback */
 482                gmx_cfg.s.duplex = 1;
 483                gmx_cfg.s.slottime = 1;
 484                gmx_cfg.s.speed = 1;
 485                cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
 486                cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
 487                cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
 488        }
 489        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
 490
 491        /* Set the loopback bits */
 492        asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
 493        if (enable_internal)
 494                asxx_prt_loop.s.int_loop |= 1 << index;
 495        else
 496                asxx_prt_loop.s.int_loop &= ~(1 << index);
 497        if (enable_external)
 498                asxx_prt_loop.s.ext_loop |= 1 << index;
 499        else
 500                asxx_prt_loop.s.ext_loop &= ~(1 << index);
 501        cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), asxx_prt_loop.u64);
 502
 503        /* Force enables in internal loopback */
 504        if (enable_internal) {
 505                uint64_t tmp;
 506                tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface));
 507                cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface),
 508                               (1 << index) | tmp);
 509                tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface));
 510                cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
 511                               (1 << index) | tmp);
 512                original_enable = 1;
 513        }
 514
 515        /* Restore the enable state */
 516        gmx_cfg.s.en = original_enable;
 517        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
 518        return 0;
 519}
 520