1
2
3
4
5
6
7
8
9
10#ifndef _ASM_POWERPC_REG_H
11#define _ASM_POWERPC_REG_H
12#ifdef __KERNEL__
13
14#include <linux/stringify.h>
15#include <asm/cputable.h>
16#include <asm/asm-const.h>
17#include <asm/feature-fixups.h>
18
19
20#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
21#include <asm/reg_booke.h>
22#endif
23
24#ifdef CONFIG_FSL_EMB_PERFMON
25#include <asm/reg_fsl_emb.h>
26#endif
27
28#ifdef CONFIG_PPC_8xx
29#include <asm/reg_8xx.h>
30#endif
31
32#define MSR_SF_LG 63
33#define MSR_ISF_LG 61
34#define MSR_HV_LG 60
35#define MSR_TS_T_LG 34
36#define MSR_TS_S_LG 33
37#define MSR_TS_LG 33
38#define MSR_TM_LG 32
39#define MSR_VEC_LG 25
40#define MSR_VSX_LG 23
41#define MSR_POW_LG 18
42#define MSR_WE_LG 18
43#define MSR_TGPR_LG 17
44#define MSR_CE_LG 17
45#define MSR_ILE_LG 16
46#define MSR_EE_LG 15
47#define MSR_PR_LG 14
48#define MSR_FP_LG 13
49#define MSR_ME_LG 12
50#define MSR_FE0_LG 11
51#define MSR_SE_LG 10
52#define MSR_BE_LG 9
53#define MSR_DE_LG 9
54#define MSR_FE1_LG 8
55#define MSR_IP_LG 6
56#define MSR_IR_LG 5
57#define MSR_DR_LG 4
58#define MSR_PE_LG 3
59#define MSR_PX_LG 2
60#define MSR_PMM_LG 2
61#define MSR_RI_LG 1
62#define MSR_LE_LG 0
63
64#ifdef __ASSEMBLY__
65#define __MASK(X) (1<<(X))
66#else
67#define __MASK(X) (1UL<<(X))
68#endif
69
70#ifdef CONFIG_PPC64
71#define MSR_SF __MASK(MSR_SF_LG)
72#define MSR_ISF __MASK(MSR_ISF_LG)
73#define MSR_HV __MASK(MSR_HV_LG)
74#else
75
76#define MSR_SF 0
77#define MSR_ISF 0
78#define MSR_HV 0
79#endif
80
81
82
83
84
85#ifndef MSR_SPE
86#define MSR_SPE 0
87#endif
88
89#define MSR_VEC __MASK(MSR_VEC_LG)
90#define MSR_VSX __MASK(MSR_VSX_LG)
91#define MSR_POW __MASK(MSR_POW_LG)
92#define MSR_WE __MASK(MSR_WE_LG)
93#define MSR_TGPR __MASK(MSR_TGPR_LG)
94#define MSR_CE __MASK(MSR_CE_LG)
95#define MSR_ILE __MASK(MSR_ILE_LG)
96#define MSR_EE __MASK(MSR_EE_LG)
97#define MSR_PR __MASK(MSR_PR_LG)
98#define MSR_FP __MASK(MSR_FP_LG)
99#define MSR_ME __MASK(MSR_ME_LG)
100#define MSR_FE0 __MASK(MSR_FE0_LG)
101#define MSR_SE __MASK(MSR_SE_LG)
102#define MSR_BE __MASK(MSR_BE_LG)
103#define MSR_DE __MASK(MSR_DE_LG)
104#define MSR_FE1 __MASK(MSR_FE1_LG)
105#define MSR_IP __MASK(MSR_IP_LG)
106#define MSR_IR __MASK(MSR_IR_LG)
107#define MSR_DR __MASK(MSR_DR_LG)
108#define MSR_PE __MASK(MSR_PE_LG)
109#define MSR_PX __MASK(MSR_PX_LG)
110#ifndef MSR_PMM
111#define MSR_PMM __MASK(MSR_PMM_LG)
112#endif
113#define MSR_RI __MASK(MSR_RI_LG)
114#define MSR_LE __MASK(MSR_LE_LG)
115
116#define MSR_TM __MASK(MSR_TM_LG)
117#define MSR_TS_N 0
118#define MSR_TS_S __MASK(MSR_TS_S_LG)
119#define MSR_TS_T __MASK(MSR_TS_T_LG)
120#define MSR_TS_MASK (MSR_TS_T | MSR_TS_S)
121#define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0)
122#define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK)
123#define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T)
124#define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S)
125
126#if defined(CONFIG_PPC_BOOK3S_64)
127#define MSR_64BIT MSR_SF
128
129
130#define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV)
131#ifdef __BIG_ENDIAN__
132#define MSR_ __MSR
133#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV)
134#else
135#define MSR_ (__MSR | MSR_LE)
136#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV | MSR_LE)
137#endif
138#define MSR_KERNEL (MSR_ | MSR_64BIT)
139#define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
140#define MSR_USER64 (MSR_USER32 | MSR_64BIT)
141#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_8xx)
142
143#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
144#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
145#endif
146
147#ifndef MSR_64BIT
148#define MSR_64BIT 0
149#endif
150
151
152#define CR0_SHIFT 28
153#define CR0_MASK 0xF
154#define CR0_TBEGIN_FAILURE (0x2 << 28)
155
156
157
158#define PSSCR_RL_MASK 0x0000000F
159#define PSSCR_MTL_MASK 0x000000F0
160#define PSSCR_TR_MASK 0x00000300
161#define PSSCR_PSLL_MASK 0x000F0000
162#define PSSCR_EC 0x00100000
163#define PSSCR_ESL 0x00200000
164#define PSSCR_SD 0x00400000
165#define PSSCR_PLS 0xf000000000000000
166#define PSSCR_GUEST_VIS 0xf0000000000003ffUL
167#define PSSCR_FAKE_SUSPEND 0x00000400
168#define PSSCR_FAKE_SUSPEND_LG 10
169
170
171#define FPSCR_FX 0x80000000
172#define FPSCR_FEX 0x40000000
173#define FPSCR_VX 0x20000000
174#define FPSCR_OX 0x10000000
175#define FPSCR_UX 0x08000000
176#define FPSCR_ZX 0x04000000
177#define FPSCR_XX 0x02000000
178#define FPSCR_VXSNAN 0x01000000
179#define FPSCR_VXISI 0x00800000
180#define FPSCR_VXIDI 0x00400000
181#define FPSCR_VXZDZ 0x00200000
182#define FPSCR_VXIMZ 0x00100000
183#define FPSCR_VXVC 0x00080000
184#define FPSCR_FR 0x00040000
185#define FPSCR_FI 0x00020000
186#define FPSCR_FPRF 0x0001f000
187#define FPSCR_FPCC 0x0000f000
188#define FPSCR_VXSOFT 0x00000400
189#define FPSCR_VXSQRT 0x00000200
190#define FPSCR_VXCVI 0x00000100
191#define FPSCR_VE 0x00000080
192#define FPSCR_OE 0x00000040
193#define FPSCR_UE 0x00000020
194#define FPSCR_ZE 0x00000010
195#define FPSCR_XE 0x00000008
196#define FPSCR_NI 0x00000004
197#define FPSCR_RN 0x00000003
198
199
200#define SPEFSCR_SOVH 0x80000000
201#define SPEFSCR_OVH 0x40000000
202#define SPEFSCR_FGH 0x20000000
203#define SPEFSCR_FXH 0x10000000
204#define SPEFSCR_FINVH 0x08000000
205#define SPEFSCR_FDBZH 0x04000000
206#define SPEFSCR_FUNFH 0x02000000
207#define SPEFSCR_FOVFH 0x01000000
208#define SPEFSCR_FINXS 0x00200000
209#define SPEFSCR_FINVS 0x00100000
210#define SPEFSCR_FDBZS 0x00080000
211#define SPEFSCR_FUNFS 0x00040000
212#define SPEFSCR_FOVFS 0x00020000
213#define SPEFSCR_MODE 0x00010000
214#define SPEFSCR_SOV 0x00008000
215#define SPEFSCR_OV 0x00004000
216#define SPEFSCR_FG 0x00002000
217#define SPEFSCR_FX 0x00001000
218#define SPEFSCR_FINV 0x00000800
219#define SPEFSCR_FDBZ 0x00000400
220#define SPEFSCR_FUNF 0x00000200
221#define SPEFSCR_FOVF 0x00000100
222#define SPEFSCR_FINXE 0x00000040
223#define SPEFSCR_FINVE 0x00000020
224#define SPEFSCR_FDBZE 0x00000010
225#define SPEFSCR_FUNFE 0x00000008
226#define SPEFSCR_FOVFE 0x00000004
227#define SPEFSCR_FRMC 0x00000003
228
229
230
231#ifdef CONFIG_40x
232#define SPRN_PID 0x3B1
233#else
234#define SPRN_PID 0x030
235#ifdef CONFIG_BOOKE
236#define SPRN_PID0 SPRN_PID
237#endif
238#endif
239
240#define SPRN_CTR 0x009
241#define SPRN_DSCR 0x11
242#define SPRN_CFAR 0x1c
243#define SPRN_AMR 0x1d
244#define SPRN_UAMOR 0x9d
245#define SPRN_AMOR 0x15d
246#define SPRN_ACOP 0x1F
247#define SPRN_TFIAR 0x81
248#define SPRN_TEXASR 0x82
249#define SPRN_TEXASRU 0x83
250
251#define TEXASR_FC_LG (63 - 7)
252#define TEXASR_AB_LG (63 - 31)
253#define TEXASR_SU_LG (63 - 32)
254#define TEXASR_HV_LG (63 - 34)
255#define TEXASR_PR_LG (63 - 35)
256#define TEXASR_FS_LG (63 - 36)
257#define TEXASR_EX_LG (63 - 37)
258#define TEXASR_ROT_LG (63 - 38)
259
260#define TEXASR_ABORT __MASK(TEXASR_AB_LG)
261#define TEXASR_SUSP __MASK(TEXASR_SU_LG)
262#define TEXASR_HV __MASK(TEXASR_HV_LG)
263#define TEXASR_PR __MASK(TEXASR_PR_LG)
264#define TEXASR_FS __MASK(TEXASR_FS_LG)
265#define TEXASR_EXACT __MASK(TEXASR_EX_LG)
266#define TEXASR_ROT __MASK(TEXASR_ROT_LG)
267#define TEXASR_FC (ASM_CONST(0xFF) << TEXASR_FC_LG)
268
269#define SPRN_TFHAR 0x80
270
271#define SPRN_TIDR 144
272#define SPRN_CTRLF 0x088
273#define SPRN_CTRLT 0x098
274#define CTRL_CT 0xc0000000
275#define CTRL_CT0 0x80000000
276#define CTRL_CT1 0x40000000
277#define CTRL_TE 0x00c00000
278#define CTRL_RUNLATCH 0x1
279#define SPRN_DAWR 0xB4
280#define SPRN_RPR 0xBA
281#define SPRN_CIABR 0xBB
282#define CIABR_PRIV 0x3
283#define CIABR_PRIV_USER 1
284#define CIABR_PRIV_SUPER 2
285#define CIABR_PRIV_HYPER 3
286#define SPRN_DAWRX 0xBC
287#define DAWRX_USER __MASK(0)
288#define DAWRX_KERNEL __MASK(1)
289#define DAWRX_HYP __MASK(2)
290#define DAWRX_WTI __MASK(3)
291#define DAWRX_WT __MASK(4)
292#define DAWRX_DR __MASK(5)
293#define DAWRX_DW __MASK(6)
294#define SPRN_DABR 0x3F5
295#define SPRN_DABR2 0x13D
296#define SPRN_DABRX 0x3F7
297#define DABRX_USER __MASK(0)
298#define DABRX_KERNEL __MASK(1)
299#define DABRX_HYP __MASK(2)
300#define DABRX_BTI __MASK(3)
301#define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER)
302#define SPRN_DAR 0x013
303#define SPRN_DBCR 0x136
304#define SPRN_DSISR 0x012
305#define DSISR_BAD_DIRECT_ST 0x80000000
306#define DSISR_NOHPTE 0x40000000
307#define DSISR_ATTR_CONFLICT 0x20000000
308#define DSISR_NOEXEC_OR_G 0x10000000
309#define DSISR_PROTFAULT 0x08000000
310#define DSISR_BADACCESS 0x04000000
311#define DSISR_ISSTORE 0x02000000
312#define DSISR_DABRMATCH 0x00400000
313#define DSISR_NOSEGMENT 0x00200000
314#define DSISR_KEYFAULT 0x00200000
315#define DSISR_BAD_EXT_CTRL 0x00100000
316#define DSISR_UNSUPP_MMU 0x00080000
317#define DSISR_SET_RC 0x00040000
318#define DSISR_PRTABLE_FAULT 0x00020000
319#define DSISR_ICSWX_NO_CT 0x00004000
320#define DSISR_BAD_COPYPASTE 0x00000008
321#define DSISR_BAD_AMO 0x00000004
322#define DSISR_BAD_CI_LDST 0x00000002
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339#define DSISR_BAD_FAULT_32S (DSISR_BAD_DIRECT_ST | \
340 DSISR_BADACCESS | \
341 DSISR_BAD_EXT_CTRL)
342#define DSISR_BAD_FAULT_64S (DSISR_BAD_FAULT_32S | \
343 DSISR_ATTR_CONFLICT | \
344 DSISR_UNSUPP_MMU | \
345 DSISR_PRTABLE_FAULT | \
346 DSISR_ICSWX_NO_CT | \
347 DSISR_BAD_COPYPASTE | \
348 DSISR_BAD_AMO | \
349 DSISR_BAD_CI_LDST)
350
351
352
353
354#define DSISR_SRR1_MATCH_32S (DSISR_NOHPTE | \
355 DSISR_NOEXEC_OR_G | \
356 DSISR_PROTFAULT)
357#define DSISR_SRR1_MATCH_64S (DSISR_SRR1_MATCH_32S | \
358 DSISR_KEYFAULT | \
359 DSISR_UNSUPP_MMU | \
360 DSISR_SET_RC | \
361 DSISR_PRTABLE_FAULT)
362
363#define SPRN_TBRL 0x10C
364#define SPRN_TBRU 0x10D
365#define SPRN_CIR 0x11B
366#define SPRN_TBWL 0x11C
367#define SPRN_TBWU 0x11D
368#define SPRN_TBU40 0x11E
369#define SPRN_SPURR 0x134
370#define SPRN_HSPRG0 0x130
371#define SPRN_HSPRG1 0x131
372#define SPRN_HDSISR 0x132
373#define SPRN_HDAR 0x133
374#define SPRN_HDEC 0x136
375#define SPRN_HIOR 0x137
376#define SPRN_RMOR 0x138
377#define SPRN_HRMOR 0x139
378#define SPRN_HSRR0 0x13A
379#define SPRN_HSRR1 0x13B
380#define SPRN_ASDR 0x330
381#define SPRN_IC 0x350
382#define SPRN_VTB 0x351
383#define SPRN_LDBAR 0x352
384#define SPRN_PMICR 0x354
385#define SPRN_PMSR 0x355
386#define SPRN_PMMAR 0x356
387#define SPRN_PSSCR 0x357
388#define SPRN_PSSCR_PR 0x337
389#define SPRN_PMCR 0x374
390#define SPRN_RWMR 0x375
391
392
393#define FSCR_SCV_LG 12
394#define FSCR_MSGP_LG 10
395#define FSCR_TAR_LG 8
396#define FSCR_EBB_LG 7
397#define FSCR_TM_LG 5
398#define FSCR_BHRB_LG 4
399#define FSCR_PM_LG 3
400#define FSCR_DSCR_LG 2
401#define FSCR_VECVSX_LG 1
402#define FSCR_FP_LG 0
403#define SPRN_FSCR 0x099
404#define FSCR_SCV __MASK(FSCR_SCV_LG)
405#define FSCR_TAR __MASK(FSCR_TAR_LG)
406#define FSCR_EBB __MASK(FSCR_EBB_LG)
407#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
408#define SPRN_HFSCR 0xbe
409#define HFSCR_MSGP __MASK(FSCR_MSGP_LG)
410#define HFSCR_TAR __MASK(FSCR_TAR_LG)
411#define HFSCR_EBB __MASK(FSCR_EBB_LG)
412#define HFSCR_TM __MASK(FSCR_TM_LG)
413#define HFSCR_PM __MASK(FSCR_PM_LG)
414#define HFSCR_BHRB __MASK(FSCR_BHRB_LG)
415#define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
416#define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
417#define HFSCR_FP __MASK(FSCR_FP_LG)
418#define SPRN_TAR 0x32f
419#define SPRN_LPCR 0x13E
420#define LPCR_VPM0 ASM_CONST(0x8000000000000000)
421#define LPCR_VPM1 ASM_CONST(0x4000000000000000)
422#define LPCR_ISL ASM_CONST(0x2000000000000000)
423#define LPCR_VC_SH 61
424#define LPCR_DPFD_SH 52
425#define LPCR_DPFD (ASM_CONST(7) << LPCR_DPFD_SH)
426#define LPCR_VRMASD_SH 47
427#define LPCR_VRMASD (ASM_CONST(0x1f) << LPCR_VRMASD_SH)
428#define LPCR_VRMA_L ASM_CONST(0x0008000000000000)
429#define LPCR_VRMA_LP0 ASM_CONST(0x0001000000000000)
430#define LPCR_VRMA_LP1 ASM_CONST(0x0000800000000000)
431#define LPCR_RMLS 0x1C000000
432#define LPCR_RMLS_SH 26
433#define LPCR_ILE ASM_CONST(0x0000000002000000)
434#define LPCR_AIL ASM_CONST(0x0000000001800000)
435#define LPCR_AIL_0 ASM_CONST(0x0000000000000000)
436#define LPCR_AIL_3 ASM_CONST(0x0000000001800000)
437#define LPCR_ONL ASM_CONST(0x0000000000040000)
438#define LPCR_LD ASM_CONST(0x0000000000020000)
439#define LPCR_PECE ASM_CONST(0x000000000001f000)
440#define LPCR_PECEDP ASM_CONST(0x0000000000010000)
441#define LPCR_PECEDH ASM_CONST(0x0000000000008000)
442#define LPCR_PECE0 ASM_CONST(0x0000000000004000)
443#define LPCR_PECE1 ASM_CONST(0x0000000000002000)
444#define LPCR_PECE2 ASM_CONST(0x0000000000001000)
445#define LPCR_PECE_HVEE ASM_CONST(0x0000400000000000)
446#define LPCR_MER ASM_CONST(0x0000000000000800)
447#define LPCR_MER_SH 11
448#define LPCR_GTSE ASM_CONST(0x0000000000000400)
449#define LPCR_TC ASM_CONST(0x0000000000000200)
450#define LPCR_HEIC ASM_CONST(0x0000000000000010)
451#define LPCR_LPES 0x0000000c
452#define LPCR_LPES0 ASM_CONST(0x0000000000000008)
453#define LPCR_LPES1 ASM_CONST(0x0000000000000004)
454#define LPCR_LPES_SH 2
455#define LPCR_RMI ASM_CONST(0x0000000000000002)
456#define LPCR_HVICE ASM_CONST(0x0000000000000002)
457#define LPCR_HDICE ASM_CONST(0x0000000000000001)
458#define LPCR_UPRT ASM_CONST(0x0000000000400000)
459#define LPCR_HR ASM_CONST(0x0000000000100000)
460#ifndef SPRN_LPID
461#define SPRN_LPID 0x13F
462#endif
463#define LPID_RSVD 0x3ff
464#define SPRN_HMER 0x150
465#define HMER_DEBUG_TRIG (1ul << (63 - 17))
466#define SPRN_HMEER 0x151
467#define SPRN_PCR 0x152
468#define PCR_VEC_DIS (1ul << (63-0))
469#define PCR_VSX_DIS (1ul << (63-1))
470#define PCR_TM_DIS (1ul << (63-2))
471
472
473
474
475
476#define PCR_ARCH_207 0x8
477#define PCR_ARCH_206 0x4
478#define PCR_ARCH_205 0x2
479#define SPRN_HEIR 0x153
480#define SPRN_TLBINDEXR 0x154
481#define SPRN_TLBVPNR 0x155
482#define SPRN_TLBRPNR 0x156
483#define SPRN_TLBLPIDR 0x157
484#define SPRN_DBAT0L 0x219
485#define SPRN_DBAT0U 0x218
486#define SPRN_DBAT1L 0x21B
487#define SPRN_DBAT1U 0x21A
488#define SPRN_DBAT2L 0x21D
489#define SPRN_DBAT2U 0x21C
490#define SPRN_DBAT3L 0x21F
491#define SPRN_DBAT3U 0x21E
492#define SPRN_DBAT4L 0x239
493#define SPRN_DBAT4U 0x238
494#define SPRN_DBAT5L 0x23B
495#define SPRN_DBAT5U 0x23A
496#define SPRN_DBAT6L 0x23D
497#define SPRN_DBAT6U 0x23C
498#define SPRN_DBAT7L 0x23F
499#define SPRN_DBAT7U 0x23E
500#define SPRN_PPR 0x380
501#define SPRN_TSCR 0x399
502
503#define SPRN_DEC 0x016
504#define SPRN_DER 0x095
505#define DER_RSTE 0x40000000
506#define DER_CHSTPE 0x20000000
507#define DER_MCIE 0x10000000
508#define DER_EXTIE 0x02000000
509#define DER_ALIE 0x01000000
510#define DER_PRIE 0x00800000
511#define DER_FPUVIE 0x00400000
512#define DER_DECIE 0x00200000
513#define DER_SYSIE 0x00040000
514#define DER_TRE 0x00020000
515#define DER_SEIE 0x00004000
516#define DER_ITLBMSE 0x00002000
517#define DER_ITLBERE 0x00001000
518#define DER_DTLBMSE 0x00000800
519#define DER_DTLBERE 0x00000400
520#define DER_LBRKE 0x00000008
521#define DER_IBRKE 0x00000004
522#define DER_EBRKE 0x00000002
523#define DER_DPIE 0x00000001
524#define SPRN_DMISS 0x3D0
525#define SPRN_DHDES 0x0B1
526#define SPRN_DPDES 0x0B0
527#define SPRN_EAR 0x11A
528#define SPRN_HASH1 0x3D2
529#define SPRN_HASH2 0x3D3
530#define SPRN_HID0 0x3F0
531#define HID0_HDICE_SH (63 - 23)
532#define HID0_EMCP (1<<31)
533#define HID0_EBA (1<<29)
534#define HID0_EBD (1<<28)
535#define HID0_SBCLK (1<<27)
536#define HID0_EICE (1<<26)
537#define HID0_TBEN (1<<26)
538#define HID0_ECLK (1<<25)
539#define HID0_PAR (1<<24)
540#define HID0_STEN (1<<24)
541#define HID0_HIGH_BAT (1<<23)
542#define HID0_DOZE (1<<23)
543#define HID0_NAP (1<<22)
544#define HID0_SLEEP (1<<21)
545#define HID0_DPM (1<<20)
546#define HID0_BHTCLR (1<<18)
547#define HID0_XAEN (1<<17)
548#define HID0_NHR (1<<16)
549#define HID0_ICE (1<<15)
550#define HID0_DCE (1<<14)
551#define HID0_ILOCK (1<<13)
552#define HID0_DLOCK (1<<12)
553#define HID0_ICFI (1<<11)
554#define HID0_DCI (1<<10)
555#define HID0_SPD (1<<9)
556#define HID0_DAPUEN (1<<8)
557#define HID0_SGE (1<<7)
558#define HID0_SIED (1<<7)
559#define HID0_DCFA (1<<6)
560#define HID0_LRSTK (1<<4)
561#define HID0_BTIC (1<<5)
562#define HID0_ABE (1<<3)
563#define HID0_FOLD (1<<3)
564#define HID0_BHTE (1<<2)
565#define HID0_BTCD (1<<1)
566#define HID0_NOPDST (1<<1)
567#define HID0_NOPTI (1<<0)
568
569#define HID0_POWER8_4LPARMODE __MASK(61)
570#define HID0_POWER8_2LPARMODE __MASK(57)
571#define HID0_POWER8_1TO2LPAR __MASK(52)
572#define HID0_POWER8_1TO4LPAR __MASK(51)
573#define HID0_POWER8_DYNLPARDIS __MASK(48)
574
575
576#define HID0_POWER9_RADIX __MASK(63 - 8)
577
578#define SPRN_HID1 0x3F1
579#ifdef CONFIG_6xx
580#define HID1_EMCP (1<<31)
581#define HID1_DFS (1<<22)
582#define HID1_PC0 (1<<16)
583#define HID1_PC1 (1<<15)
584#define HID1_PC2 (1<<14)
585#define HID1_PC3 (1<<13)
586#define HID1_SYNCBE (1<<11)
587#define HID1_ABE (1<<10)
588#define HID1_PS (1<<16)
589#endif
590#define SPRN_HID2 0x3F8
591#define SPRN_HID2_GEKKO 0x398
592#define SPRN_IABR 0x3F2
593#define SPRN_IABR2 0x3FA
594#define SPRN_IBCR 0x135
595#define SPRN_IAMR 0x03D
596#define SPRN_HID4 0x3F4
597#define HID4_LPES0 (1ul << (63-0))
598#define HID4_RMLS2_SH (63 - 2)
599#define HID4_LPID5_SH (63 - 6)
600#define HID4_RMOR_SH (63 - 22)
601#define HID4_RMOR (0xFFFFul << HID4_RMOR_SH)
602#define HID4_LPES1 (1 << (63-57))
603#define HID4_RMLS0_SH (63 - 58)
604#define HID4_LPID1_SH 0
605#define SPRN_HID4_GEKKO 0x3F3
606#define SPRN_HID5 0x3F6
607#define SPRN_HID6 0x3F9
608#define HID6_LB (0x0F<<12)
609#define HID6_DLP (1<<20)
610#define SPRN_TSC_CELL 0x399
611#define TSC_CELL_DEC_ENABLE_0 0x400000
612#define TSC_CELL_DEC_ENABLE_1 0x200000
613#define TSC_CELL_EE_ENABLE 0x100000
614#define TSC_CELL_EE_BOOST 0x080000
615#define SPRN_TSC 0x3FD
616#define SPRN_TST 0x3FC
617#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
618#define SPRN_IAC1 0x3F4
619#define SPRN_IAC2 0x3F5
620#endif
621#define SPRN_IBAT0L 0x211
622#define SPRN_IBAT0U 0x210
623#define SPRN_IBAT1L 0x213
624#define SPRN_IBAT1U 0x212
625#define SPRN_IBAT2L 0x215
626#define SPRN_IBAT2U 0x214
627#define SPRN_IBAT3L 0x217
628#define SPRN_IBAT3U 0x216
629#define SPRN_IBAT4L 0x231
630#define SPRN_IBAT4U 0x230
631#define SPRN_IBAT5L 0x233
632#define SPRN_IBAT5U 0x232
633#define SPRN_IBAT6L 0x235
634#define SPRN_IBAT6U 0x234
635#define SPRN_IBAT7L 0x237
636#define SPRN_IBAT7U 0x236
637#define SPRN_ICMP 0x3D5
638#define SPRN_ICTC 0x3FB
639#ifndef SPRN_ICTRL
640#define SPRN_ICTRL 0x3F3
641#endif
642#define ICTRL_EICE 0x08000000
643#define ICTRL_EDC 0x04000000
644#define ICTRL_EICP 0x00000100
645#define SPRN_IMISS 0x3D4
646#define SPRN_IMMR 0x27E
647#define SPRN_L2CR 0x3F9
648#define SPRN_L2CR2 0x3f8
649#define L2CR_L2E 0x80000000
650#define L2CR_L2PE 0x40000000
651#define L2CR_L2SIZ_MASK 0x30000000
652#define L2CR_L2SIZ_256KB 0x10000000
653#define L2CR_L2SIZ_512KB 0x20000000
654#define L2CR_L2SIZ_1MB 0x30000000
655#define L2CR_L2CLK_MASK 0x0e000000
656#define L2CR_L2CLK_DISABLED 0x00000000
657#define L2CR_L2CLK_DIV1 0x02000000
658#define L2CR_L2CLK_DIV1_5 0x04000000
659#define L2CR_L2CLK_DIV2 0x08000000
660#define L2CR_L2CLK_DIV2_5 0x0a000000
661#define L2CR_L2CLK_DIV3 0x0c000000
662#define L2CR_L2RAM_MASK 0x01800000
663#define L2CR_L2RAM_FLOW 0x00000000
664#define L2CR_L2RAM_PIPE 0x01000000
665#define L2CR_L2RAM_PIPE_LW 0x01800000
666#define L2CR_L2DO 0x00400000
667#define L2CR_L2I 0x00200000
668#define L2CR_L2CTL 0x00100000
669#define L2CR_L2WT 0x00080000
670#define L2CR_L2TS 0x00040000
671#define L2CR_L2OH_MASK 0x00030000
672#define L2CR_L2OH_0_5 0x00000000
673#define L2CR_L2OH_1_0 0x00010000
674#define L2CR_L2SL 0x00008000
675#define L2CR_L2DF 0x00004000
676#define L2CR_L2BYP 0x00002000
677#define L2CR_L2IP 0x00000001
678#define L2CR_L2IO_745x 0x00100000
679#define L2CR_L2DO_745x 0x00010000
680#define L2CR_L2REP_745x 0x00001000
681#define L2CR_L2HWF_745x 0x00000800
682#define SPRN_L3CR 0x3FA
683#define L3CR_L3E 0x80000000
684#define L3CR_L3PE 0x40000000
685#define L3CR_L3APE 0x20000000
686#define L3CR_L3SIZ 0x10000000
687#define L3CR_L3CLKEN 0x08000000
688#define L3CR_L3RES 0x04000000
689#define L3CR_L3CLKDIV 0x03800000
690#define L3CR_L3IO 0x00400000
691#define L3CR_L3SPO 0x00040000
692#define L3CR_L3CKSP 0x00030000
693#define L3CR_L3PSP 0x0000e000
694#define L3CR_L3REP 0x00001000
695#define L3CR_L3HWF 0x00000800
696#define L3CR_L3I 0x00000400
697#define L3CR_L3RT 0x00000300
698#define L3CR_L3NIRCA 0x00000080
699#define L3CR_L3DO 0x00000040
700#define L3CR_PMEN 0x00000004
701#define L3CR_PMSIZ 0x00000001
702
703#define SPRN_MSSCR0 0x3f6
704#define SPRN_MSSSR0 0x3f7
705#define SPRN_LDSTCR 0x3f8
706#define SPRN_LDSTDB 0x3f4
707#define SPRN_LR 0x008
708#ifndef SPRN_PIR
709#define SPRN_PIR 0x3FF
710#endif
711#define SPRN_TIR 0x1BE
712#define SPRN_PTCR 0x1D0
713#define SPRN_PSPB 0x09F
714#define SPRN_PTEHI 0x3D5
715#define SPRN_PTELO 0x3D6
716#define SPRN_PURR 0x135
717#define SPRN_PVR 0x11F
718#define SPRN_RPA 0x3D6
719#define SPRN_SDA 0x3BF
720#define SPRN_SDR1 0x019
721#define SPRN_ASR 0x118
722#define SPRN_SIA 0x3BB
723#define SPRN_SPRG0 0x110
724#define SPRN_SPRG1 0x111
725#define SPRN_SPRG2 0x112
726#define SPRN_SPRG3 0x113
727#define SPRN_USPRG3 0x103
728#define SPRN_SPRG4 0x114
729#define SPRN_USPRG4 0x104
730#define SPRN_SPRG5 0x115
731#define SPRN_USPRG5 0x105
732#define SPRN_SPRG6 0x116
733#define SPRN_USPRG6 0x106
734#define SPRN_SPRG7 0x117
735#define SPRN_USPRG7 0x107
736#define SPRN_SRR0 0x01A
737#define SPRN_SRR1 0x01B
738#define SRR1_ISI_NOPT 0x40000000
739#define SRR1_ISI_N_OR_G 0x10000000
740#define SRR1_ISI_PROT 0x08000000
741#define SRR1_WAKEMASK 0x00380000
742#define SRR1_WAKEMASK_P8 0x003c0000
743#define SRR1_WAKEMCE_RESVD 0x003c0000
744#define SRR1_WAKESYSERR 0x00300000
745#define SRR1_WAKEEE 0x00200000
746#define SRR1_WAKEHVI 0x00240000
747#define SRR1_WAKEMT 0x00280000
748#define SRR1_WAKEHMI 0x00280000
749#define SRR1_WAKEDEC 0x00180000
750#define SRR1_WAKEDBELL 0x00140000
751#define SRR1_WAKETHERM 0x00100000
752#define SRR1_WAKERESET 0x00100000
753#define SRR1_WAKEHDBELL 0x000c0000
754#define SRR1_WAKESTATE 0x00030000
755#define SRR1_WS_DEEPEST 0x00030000
756
757#define SRR1_WS_DEEPER 0x00020000
758#define SRR1_WS_DEEP 0x00010000
759#define SRR1_PROGTM 0x00200000
760#define SRR1_PROGFPE 0x00100000
761#define SRR1_PROGILL 0x00080000
762#define SRR1_PROGPRIV 0x00040000
763#define SRR1_PROGTRAP 0x00020000
764#define SRR1_PROGADDR 0x00010000
765
766#define SPRN_HSRR0 0x13A
767#define SPRN_HSRR1 0x13B
768#define HSRR1_DENORM 0x00100000
769
770#define SPRN_TBCTL 0x35f
771#define TBCTL_FREEZE 0x0000000000000000ull
772#define TBCTL_RESTART 0x0000000100000000ull
773#define TBCTL_UPDATE_UPPER 0x0000000200000000ull
774#define TBCTL_UPDATE_LOWER 0x0000000300000000ull
775
776#ifndef SPRN_SVR
777#define SPRN_SVR 0x11E
778#endif
779#define SPRN_THRM1 0x3FC
780
781#define THRM1_TIN (1 << 31)
782#define THRM1_TIV (1 << 30)
783#define THRM1_THRES(x) ((x&0x7f)<<23)
784#define THRM3_SITV(x) ((x&0x3fff)<<1)
785#define THRM1_TID (1<<2)
786#define THRM1_TIE (1<<1)
787#define THRM1_V (1<<0)
788#define SPRN_THRM2 0x3FD
789#define SPRN_THRM3 0x3FE
790#define THRM3_E (1<<0)
791#define SPRN_TLBMISS 0x3D4
792#define SPRN_UMMCR0 0x3A8
793#define SPRN_UMMCR1 0x3AC
794#define SPRN_UPMC1 0x3A9
795#define SPRN_UPMC2 0x3AA
796#define SPRN_UPMC3 0x3AD
797#define SPRN_UPMC4 0x3AE
798#define SPRN_USIA 0x3AB
799#define SPRN_VRSAVE 0x100
800#define SPRN_XER 0x001
801
802#define SPRN_MMCR0_GEKKO 0x3B8
803#define SPRN_MMCR1_GEKKO 0x3BC
804#define SPRN_PMC1_GEKKO 0x3B9
805#define SPRN_PMC2_GEKKO 0x3BA
806#define SPRN_PMC3_GEKKO 0x3BD
807#define SPRN_PMC4_GEKKO 0x3BE
808#define SPRN_WPAR_GEKKO 0x399
809
810#define SPRN_SCOMC 0x114
811#define SPRN_SCOMD 0x115
812
813
814#ifdef CONFIG_PPC64
815#define SPRN_MMCR0 795
816#define MMCR0_FC 0x80000000UL
817#define MMCR0_FCS 0x40000000UL
818#define MMCR0_KERNEL_DISABLE MMCR0_FCS
819#define MMCR0_FCP 0x20000000UL
820#define MMCR0_PROBLEM_DISABLE MMCR0_FCP
821#define MMCR0_FCM1 0x10000000UL
822#define MMCR0_FCM0 0x08000000UL
823#define MMCR0_PMXE ASM_CONST(0x04000000)
824#define MMCR0_FCECE ASM_CONST(0x02000000)
825#define MMCR0_TBEE 0x00400000UL
826#define MMCR0_BHRBA 0x00200000UL
827#define MMCR0_EBE 0x00100000UL
828#define MMCR0_PMCC 0x000c0000UL
829#define MMCR0_PMCC_U6 0x00080000UL
830#define MMCR0_PMC1CE 0x00008000UL
831#define MMCR0_PMCjCE ASM_CONST(0x00004000)
832#define MMCR0_TRIGGER 0x00002000UL
833#define MMCR0_PMAO_SYNC ASM_CONST(0x00000800)
834#define MMCR0_C56RUN ASM_CONST(0x00000100)
835
836#define MMCR0_PMAO ASM_CONST(0x00000080)
837#define MMCR0_SHRFC 0x00000040UL
838#define MMCR0_FC56 0x00000010UL
839#define MMCR0_FCTI 0x00000008UL
840#define MMCR0_FCTA 0x00000004UL
841#define MMCR0_FCWAIT 0x00000002UL
842#define MMCR0_FCHV 0x00000001UL
843#define SPRN_MMCR1 798
844#define SPRN_MMCR2 785
845#define SPRN_UMMCR2 769
846#define SPRN_MMCRA 0x312
847#define MMCRA_SDSYNC 0x80000000UL
848#define MMCRA_SDAR_DCACHE_MISS 0x40000000UL
849#define MMCRA_SDAR_ERAT_MISS 0x20000000UL
850#define MMCRA_SIHV 0x10000000UL
851#define MMCRA_SIPR 0x08000000UL
852#define MMCRA_SLOT 0x07000000UL
853#define MMCRA_SLOT_SHIFT 24
854#define MMCRA_SAMPLE_ENABLE 0x00000001UL
855#define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL
856#define POWER6_MMCRA_SIHV 0x0000040000000000ULL
857#define POWER6_MMCRA_SIPR 0x0000020000000000ULL
858#define POWER6_MMCRA_THRM 0x00000020UL
859#define POWER6_MMCRA_OTHER 0x0000000EUL
860
861#define POWER7P_MMCRA_SIAR_VALID 0x10000000
862#define POWER7P_MMCRA_SDAR_VALID 0x08000000
863
864#define SPRN_MMCRH 316
865#define SPRN_MMCRS 894
866#define SPRN_MMCRC 851
867#define SPRN_EBBHR 804
868#define SPRN_EBBRR 805
869#define SPRN_BESCR 806
870#define BESCR_GE 0x8000000000000000ULL
871#define SPRN_WORT 895
872#define SPRN_WORC 863
873
874#define SPRN_PMC1 787
875#define SPRN_PMC2 788
876#define SPRN_PMC3 789
877#define SPRN_PMC4 790
878#define SPRN_PMC5 791
879#define SPRN_PMC6 792
880#define SPRN_PMC7 793
881#define SPRN_PMC8 794
882#define SPRN_SIER 784
883#define SIER_SIPR 0x2000000
884#define SIER_SIHV 0x1000000
885#define SIER_SIAR_VALID 0x0400000
886#define SIER_SDAR_VALID 0x0200000
887#define SPRN_SIAR 796
888#define SPRN_SDAR 797
889#define SPRN_TACR 888
890#define SPRN_TCSCR 889
891#define SPRN_CSIGR 890
892#define SPRN_SPMC1 892
893#define SPRN_SPMC2 893
894
895
896#define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO)
897#define MMCR2_USER_MASK 0x4020100804020000UL
898#define SIER_USER_MASK 0x7fffffUL
899
900#define SPRN_PA6T_MMCR0 795
901#define PA6T_MMCR0_EN0 0x0000000000000001UL
902#define PA6T_MMCR0_EN1 0x0000000000000002UL
903#define PA6T_MMCR0_EN2 0x0000000000000004UL
904#define PA6T_MMCR0_EN3 0x0000000000000008UL
905#define PA6T_MMCR0_EN4 0x0000000000000010UL
906#define PA6T_MMCR0_EN5 0x0000000000000020UL
907#define PA6T_MMCR0_SUPEN 0x0000000000000040UL
908#define PA6T_MMCR0_PREN 0x0000000000000080UL
909#define PA6T_MMCR0_HYPEN 0x0000000000000100UL
910#define PA6T_MMCR0_FCM0 0x0000000000000200UL
911#define PA6T_MMCR0_FCM1 0x0000000000000400UL
912#define PA6T_MMCR0_INTGEN 0x0000000000000800UL
913#define PA6T_MMCR0_INTEN0 0x0000000000001000UL
914#define PA6T_MMCR0_INTEN1 0x0000000000002000UL
915#define PA6T_MMCR0_INTEN2 0x0000000000004000UL
916#define PA6T_MMCR0_INTEN3 0x0000000000008000UL
917#define PA6T_MMCR0_INTEN4 0x0000000000010000UL
918#define PA6T_MMCR0_INTEN5 0x0000000000020000UL
919#define PA6T_MMCR0_DISCNT 0x0000000000040000UL
920#define PA6T_MMCR0_UOP 0x0000000000080000UL
921#define PA6T_MMCR0_TRG 0x0000000000100000UL
922#define PA6T_MMCR0_TRGEN 0x0000000000200000UL
923#define PA6T_MMCR0_TRGREG 0x0000000001600000UL
924#define PA6T_MMCR0_SIARLOG 0x0000000002000000UL
925#define PA6T_MMCR0_SDARLOG 0x0000000004000000UL
926#define PA6T_MMCR0_PROEN 0x0000000008000000UL
927#define PA6T_MMCR0_PROLOG 0x0000000010000000UL
928#define PA6T_MMCR0_DAMEN2 0x0000000020000000UL
929#define PA6T_MMCR0_DAMEN3 0x0000000040000000UL
930#define PA6T_MMCR0_DAMEN4 0x0000000080000000UL
931#define PA6T_MMCR0_DAMEN5 0x0000000100000000UL
932#define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL
933#define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL
934#define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL
935#define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL
936#define PA6T_MMCR0_HANDDIS 0x0000002000000000UL
937#define PA6T_MMCR0_PCTEN 0x0000004000000000UL
938#define PA6T_MMCR0_SOCEN 0x0000008000000000UL
939#define PA6T_MMCR0_SOCMOD 0x0000010000000000UL
940
941#define SPRN_PA6T_MMCR1 798
942#define PA6T_MMCR1_ES2 0x00000000000000ffUL
943#define PA6T_MMCR1_ES3 0x000000000000ff00UL
944#define PA6T_MMCR1_ES4 0x0000000000ff0000UL
945#define PA6T_MMCR1_ES5 0x00000000ff000000UL
946
947#define SPRN_PA6T_UPMC0 771
948#define SPRN_PA6T_UPMC1 772
949#define SPRN_PA6T_UPMC2 773
950#define SPRN_PA6T_UPMC3 774
951#define SPRN_PA6T_UPMC4 775
952#define SPRN_PA6T_UPMC5 776
953#define SPRN_PA6T_UMMCR0 779
954#define SPRN_PA6T_SIAR 780
955#define SPRN_PA6T_UMMCR1 782
956#define SPRN_PA6T_SIER 785
957#define SPRN_PA6T_PMC0 787
958#define SPRN_PA6T_PMC1 788
959#define SPRN_PA6T_PMC2 789
960#define SPRN_PA6T_PMC3 790
961#define SPRN_PA6T_PMC4 791
962#define SPRN_PA6T_PMC5 792
963#define SPRN_PA6T_TSR0 793
964#define SPRN_PA6T_TSR1 794
965#define SPRN_PA6T_TSR2 799
966#define SPRN_PA6T_TSR3 784
967
968#define SPRN_PA6T_IER 981
969#define SPRN_PA6T_DER 982
970#define SPRN_PA6T_BER 862
971#define SPRN_PA6T_MER 849
972
973#define SPRN_PA6T_IMA0 880
974#define SPRN_PA6T_IMA1 881
975#define SPRN_PA6T_IMA2 882
976#define SPRN_PA6T_IMA3 883
977#define SPRN_PA6T_IMA4 884
978#define SPRN_PA6T_IMA5 885
979#define SPRN_PA6T_IMA6 886
980#define SPRN_PA6T_IMA7 887
981#define SPRN_PA6T_IMA8 888
982#define SPRN_PA6T_IMA9 889
983#define SPRN_PA6T_BTCR 978
984#define SPRN_PA6T_IMAAT 979
985#define SPRN_PA6T_PCCR 1019
986#define SPRN_BKMK 1020
987#define SPRN_PA6T_RPCCR 1021
988
989
990#else
991#define SPRN_MMCR0 952
992#define MMCR0_FC 0x80000000UL
993#define MMCR0_FCS 0x40000000UL
994#define MMCR0_FCP 0x20000000UL
995#define MMCR0_FCM1 0x10000000UL
996#define MMCR0_FCM0 0x08000000UL
997#define MMCR0_PMXE 0x04000000UL
998#define MMCR0_FCECE 0x02000000UL
999#define MMCR0_TBEE 0x00400000UL
1000#define MMCR0_PMC1CE 0x00008000UL
1001#define MMCR0_PMCnCE 0x00004000UL
1002#define MMCR0_TRIGGER 0x00002000UL
1003#define MMCR0_PMC1SEL 0x00001fc0UL
1004#define MMCR0_PMC2SEL 0x0000003fUL
1005
1006#define SPRN_MMCR1 956
1007#define MMCR1_PMC3SEL 0xf8000000UL
1008#define MMCR1_PMC4SEL 0x07c00000UL
1009#define MMCR1_PMC5SEL 0x003e0000UL
1010#define MMCR1_PMC6SEL 0x0001f800UL
1011#define SPRN_MMCR2 944
1012#define SPRN_PMC1 953
1013#define SPRN_PMC2 954
1014#define SPRN_PMC3 957
1015#define SPRN_PMC4 958
1016#define SPRN_PMC5 945
1017#define SPRN_PMC6 946
1018
1019#define SPRN_SIAR 955
1020
1021
1022#define MMCR0_PMC1_CYCLES (1 << 7)
1023#define MMCR0_PMC1_ICACHEMISS (5 << 7)
1024#define MMCR0_PMC1_DTLB (6 << 7)
1025#define MMCR0_PMC2_DCACHEMISS 0x6
1026#define MMCR0_PMC2_CYCLES 0x1
1027#define MMCR0_PMC2_ITLB 0x7
1028#define MMCR0_PMC2_LOADMISSTIME 0x5
1029#endif
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095#ifdef CONFIG_PPC64
1096#define SPRN_SPRG_PACA SPRN_SPRG1
1097#else
1098#define SPRN_SPRG_THREAD SPRN_SPRG3
1099#endif
1100
1101#ifdef CONFIG_PPC_BOOK3S_64
1102#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2
1103#define SPRN_SPRG_HPACA SPRN_HSPRG0
1104#define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1
1105#define SPRN_SPRG_VDSO_READ SPRN_USPRG3
1106#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG3
1107
1108#define GET_PACA(rX) \
1109 BEGIN_FTR_SECTION_NESTED(66); \
1110 mfspr rX,SPRN_SPRG_PACA; \
1111 FTR_SECTION_ELSE_NESTED(66); \
1112 mfspr rX,SPRN_SPRG_HPACA; \
1113 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1114
1115#define SET_PACA(rX) \
1116 BEGIN_FTR_SECTION_NESTED(66); \
1117 mtspr SPRN_SPRG_PACA,rX; \
1118 FTR_SECTION_ELSE_NESTED(66); \
1119 mtspr SPRN_SPRG_HPACA,rX; \
1120 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1121
1122#define GET_SCRATCH0(rX) \
1123 BEGIN_FTR_SECTION_NESTED(66); \
1124 mfspr rX,SPRN_SPRG_SCRATCH0; \
1125 FTR_SECTION_ELSE_NESTED(66); \
1126 mfspr rX,SPRN_SPRG_HSCRATCH0; \
1127 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1128
1129#define SET_SCRATCH0(rX) \
1130 BEGIN_FTR_SECTION_NESTED(66); \
1131 mtspr SPRN_SPRG_SCRATCH0,rX; \
1132 FTR_SECTION_ELSE_NESTED(66); \
1133 mtspr SPRN_SPRG_HSCRATCH0,rX; \
1134 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1135
1136#else
1137#define GET_SCRATCH0(rX) mfspr rX,SPRN_SPRG_SCRATCH0
1138#define SET_SCRATCH0(rX) mtspr SPRN_SPRG_SCRATCH0,rX
1139
1140#endif
1141
1142#ifdef CONFIG_PPC_BOOK3E_64
1143#define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8
1144#define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG3
1145#define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9
1146#define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2
1147#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6
1148#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0
1149#define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH
1150#define SPRN_SPRG_VDSO_READ SPRN_USPRG7
1151#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG7
1152
1153#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX
1154#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA
1155
1156#endif
1157
1158#ifdef CONFIG_PPC_BOOK3S_32
1159#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1160#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1161#define SPRN_SPRG_RTAS SPRN_SPRG2
1162#define SPRN_SPRG_603_LRU SPRN_SPRG4
1163#endif
1164
1165#ifdef CONFIG_40x
1166#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1167#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1168#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1169#define SPRN_SPRG_SCRATCH3 SPRN_SPRG4
1170#define SPRN_SPRG_SCRATCH4 SPRN_SPRG5
1171#define SPRN_SPRG_SCRATCH5 SPRN_SPRG6
1172#define SPRN_SPRG_SCRATCH6 SPRN_SPRG7
1173#endif
1174
1175#ifdef CONFIG_BOOKE
1176#define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0
1177#define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0
1178#define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1
1179#define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1
1180#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
1181#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
1182#define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R
1183#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W
1184#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R
1185#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W
1186#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1
1187#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1
1188#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R
1189#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W
1190#ifdef CONFIG_E200
1191#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG6R
1192#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG6W
1193#else
1194#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9
1195#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9
1196#endif
1197#endif
1198
1199#ifdef CONFIG_PPC_8xx
1200#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1201#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1202#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1203#endif
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213#ifdef CONFIG_PPC64
1214#define MTFSF_L(REG) \
1215 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
1216#else
1217#define MTFSF_L(REG) mtfsf 0xff, (REG)
1218#endif
1219
1220
1221
1222#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF)
1223#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF)
1224
1225#define pvr_version_is(pvr) (PVR_VER(mfspr(SPRN_PVR)) == (pvr))
1226
1227
1228
1229
1230
1231
1232#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF)
1233#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF)
1234#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF)
1235#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF)
1236#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF)
1237#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF)
1238
1239
1240
1241#define PVR_403GA 0x00200000
1242#define PVR_403GB 0x00200100
1243#define PVR_403GC 0x00200200
1244#define PVR_403GCX 0x00201400
1245#define PVR_405GP 0x40110000
1246#define PVR_476 0x11a52000
1247#define PVR_476FPE 0x7ff50000
1248#define PVR_STB03XXX 0x40310000
1249#define PVR_NP405H 0x41410000
1250#define PVR_NP405L 0x41610000
1251#define PVR_601 0x00010000
1252#define PVR_602 0x00050000
1253#define PVR_603 0x00030000
1254#define PVR_603e 0x00060000
1255#define PVR_603ev 0x00070000
1256#define PVR_603r 0x00071000
1257#define PVR_604 0x00040000
1258#define PVR_604e 0x00090000
1259#define PVR_604r 0x000A0000
1260#define PVR_620 0x00140000
1261#define PVR_740 0x00080000
1262#define PVR_750 PVR_740
1263#define PVR_740P 0x10080000
1264#define PVR_750P PVR_740P
1265#define PVR_7400 0x000C0000
1266#define PVR_7410 0x800C0000
1267#define PVR_7450 0x80000000
1268#define PVR_8540 0x80200000
1269#define PVR_8560 0x80200000
1270#define PVR_VER_E500V1 0x8020
1271#define PVR_VER_E500V2 0x8021
1272#define PVR_VER_E500MC 0x8023
1273#define PVR_VER_E5500 0x8024
1274#define PVR_VER_E6500 0x8040
1275
1276
1277
1278
1279
1280
1281
1282#define PVR_8xx 0x00500000
1283
1284#define PVR_8240 0x00810100
1285#define PVR_8245 0x80811014
1286#define PVR_8260 PVR_8240
1287
1288
1289#define PVR_476_ISS 0x00052000
1290
1291
1292#define PVR_NORTHSTAR 0x0033
1293#define PVR_PULSAR 0x0034
1294#define PVR_POWER4 0x0035
1295#define PVR_ICESTAR 0x0036
1296#define PVR_SSTAR 0x0037
1297#define PVR_POWER4p 0x0038
1298#define PVR_970 0x0039
1299#define PVR_POWER5 0x003A
1300#define PVR_POWER5p 0x003B
1301#define PVR_970FX 0x003C
1302#define PVR_POWER6 0x003E
1303#define PVR_POWER7 0x003F
1304#define PVR_630 0x0040
1305#define PVR_630p 0x0041
1306#define PVR_970MP 0x0044
1307#define PVR_970GX 0x0045
1308#define PVR_POWER7p 0x004A
1309#define PVR_POWER8E 0x004B
1310#define PVR_POWER8NVL 0x004C
1311#define PVR_POWER8 0x004D
1312#define PVR_POWER9 0x004E
1313#define PVR_BE 0x0070
1314#define PVR_PA6T 0x0090
1315
1316
1317#define PVR_ARCH_204 0x0f000001
1318#define PVR_ARCH_205 0x0f000002
1319#define PVR_ARCH_206 0x0f000003
1320#define PVR_ARCH_206p 0x0f100003
1321#define PVR_ARCH_207 0x0f000004
1322#define PVR_ARCH_300 0x0f000005
1323
1324
1325#ifndef __ASSEMBLY__
1326#define mfmsr() ({unsigned long rval; \
1327 asm volatile("mfmsr %0" : "=r" (rval) : \
1328 : "memory"); rval;})
1329#ifdef CONFIG_PPC_BOOK3S_64
1330#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
1331 : : "r" (v) : "memory")
1332#define mtmsr(v) __mtmsrd((v), 0)
1333#define __MTMSR "mtmsrd"
1334#else
1335#define mtmsr(v) asm volatile("mtmsr %0" : \
1336 : "r" ((unsigned long)(v)) \
1337 : "memory")
1338#define __MTMSR "mtmsr"
1339#endif
1340
1341static inline void mtmsr_isync(unsigned long val)
1342{
1343 asm volatile(__MTMSR " %0; " ASM_FTR_IFCLR("isync", "nop", %1) : :
1344 "r" (val), "i" (CPU_FTR_ARCH_206) : "memory");
1345}
1346
1347#define mfspr(rn) ({unsigned long rval; \
1348 asm volatile("mfspr %0," __stringify(rn) \
1349 : "=r" (rval)); rval;})
1350#ifndef mtspr
1351#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \
1352 : "r" ((unsigned long)(v)) \
1353 : "memory")
1354#endif
1355#define wrtspr(rn) asm volatile("mtspr " __stringify(rn) ",0" : \
1356 : : "memory")
1357
1358extern unsigned long msr_check_and_set(unsigned long bits);
1359extern bool strict_msr_control;
1360extern void __msr_check_and_clear(unsigned long bits);
1361static inline void msr_check_and_clear(unsigned long bits)
1362{
1363 if (strict_msr_control)
1364 __msr_check_and_clear(bits);
1365}
1366
1367#ifdef __powerpc64__
1368#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
1369#define mftb() ({unsigned long rval; \
1370 asm volatile( \
1371 "90: mfspr %0, %2;\n" \
1372 "97: cmpwi %0,0;\n" \
1373 " beq- 90b;\n" \
1374 "99:\n" \
1375 ".section __ftr_fixup,\"a\"\n" \
1376 ".align 3\n" \
1377 "98:\n" \
1378 " .8byte %1\n" \
1379 " .8byte %1\n" \
1380 " .8byte 97b-98b\n" \
1381 " .8byte 99b-98b\n" \
1382 " .8byte 0\n" \
1383 " .8byte 0\n" \
1384 ".previous" \
1385 : "=r" (rval) \
1386 : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \
1387 rval;})
1388#else
1389#define mftb() ({unsigned long rval; \
1390 asm volatile("mfspr %0, %1" : \
1391 "=r" (rval) : "i" (SPRN_TBRL)); rval;})
1392#endif
1393
1394#else
1395
1396#if defined(CONFIG_PPC_8xx)
1397#define mftbl() ({unsigned long rval; \
1398 asm volatile("mftbl %0" : "=r" (rval)); rval;})
1399#define mftbu() ({unsigned long rval; \
1400 asm volatile("mftbu %0" : "=r" (rval)); rval;})
1401#else
1402#define mftbl() ({unsigned long rval; \
1403 asm volatile("mfspr %0, %1" : "=r" (rval) : \
1404 "i" (SPRN_TBRL)); rval;})
1405#define mftbu() ({unsigned long rval; \
1406 asm volatile("mfspr %0, %1" : "=r" (rval) : \
1407 "i" (SPRN_TBRU)); rval;})
1408#endif
1409#define mftb() mftbl()
1410#endif
1411
1412#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
1413#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
1414
1415#ifdef CONFIG_PPC32
1416#define mfsrin(v) ({unsigned int rval; \
1417 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
1418 rval;})
1419#endif
1420
1421#define proc_trap() asm volatile("trap")
1422
1423extern unsigned long current_stack_pointer(void);
1424
1425extern unsigned long scom970_read(unsigned int address);
1426extern void scom970_write(unsigned int address, unsigned long value);
1427
1428struct pt_regs;
1429
1430extern void ppc_save_regs(struct pt_regs *regs);
1431
1432static inline void update_power8_hid0(unsigned long hid0)
1433{
1434
1435
1436
1437
1438
1439 asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0));
1440}
1441#endif
1442#endif
1443#endif
1444