LXR linux/drivers/ata/pata

   1/*
   2 *    pata_efar.c - EFAR PIIX clone controller driver
   3 *
   4 *      (C) 2005 Red Hat
   5 *      (C) 2009-2010 Bartlomiej Zolnierkiewicz
   6 *
   7 *    Some parts based on ata_piix.c by Jeff Garzik and others.
   8 *
   9 *    The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
  10 *    Intel ICH controllers the EFAR widened the UDMA mode register bits
  11 *    and doesn't require the funky clock selection.
  12 */
  13
  14#include <linux/kernel.h>
  15#include <linux/module.h>
  16#include <linux/pci.h>
  17#include <linux/blkdev.h>
  18#include <linux/delay.h>
  19#include <linux/device.h>
  20#include <scsi/scsi_host.h>
  21#include <linux/libata.h>
  22#include <linux/ata.h>
  23
  24#define DRV_NAME        "pata_efar"
  25#define DRV_VERSION     "0.4.5"
  26
  27/**
  28 *      efar_pre_reset  -       Enable bits
  29 *      @link: ATA link
  30 *      @deadline: deadline jiffies for the operation
  31 *
  32 *      Perform cable detection for the EFAR ATA interface. This is
  33 *      different to the PIIX arrangement
  34 */
  35
  36static int efar_pre_reset(struct ata_link *link, unsigned long deadline)
  37{
  38        static const struct pci_bits efar_enable_bits[] = {
  39                { 0x41U, 1U, 0x80UL, 0x80UL },  /* port 0 */
  40                { 0x43U, 1U, 0x80UL, 0x80UL },  /* port 1 */
  41        };
  42        struct ata_port *ap = link->ap;
  43        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  44
  45        if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no]))
  46                return -ENOENT;
  47
  48        return ata_sff_prereset(link, deadline);
  49}
  50
  51/**
  52 *      efar_cable_detect       -       check for 40/80 pin
  53 *      @ap: Port
  54 *
  55 *      Perform cable detection for the EFAR ATA interface. This is
  56 *      different to the PIIX arrangement
  57 */
  58
  59static int efar_cable_detect(struct ata_port *ap)
  60{
  61        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  62        u8 tmp;
  63
  64        pci_read_config_byte(pdev, 0x47, &tmp);
  65        if (tmp & (2 >> ap->port_no))
  66                return ATA_CBL_PATA40;
  67        return ATA_CBL_PATA80;
  68}
  69
  70static DEFINE_SPINLOCK(efar_lock);
  71
  72/**
  73 *      efar_set_piomode - Initialize host controller PATA PIO timings
  74 *      @ap: Port whose timings we are configuring
  75 *      @adev: Device to program
  76 *
  77 *      Set PIO mode for device, in host controller PCI config space.
  78 *
  79 *      LOCKING:
  80 *      None (inherited from caller).
  81 */
  82
  83static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
  84{
  85        unsigned int pio        = adev->pio_mode - XFER_PIO_0;
  86        struct pci_dev *dev     = to_pci_dev(ap->host->dev);
  87        unsigned int master_port = ap->port_no ? 0x42 : 0x40;
  88        unsigned long flags;
  89        u16 master_data;
  90        u8 udma_enable;
  91        int control = 0;
  92
  93        /*
  94         *      See Intel Document 298600-004 for the timing programing rules
  95         *      for PIIX/ICH. The EFAR is a clone so very similar
  96         */
  97
  98        static const     /* ISP  RTC */
  99        u8 timings[][2] = { { 0, 0 },
 100                            { 0, 0 },
 101                            { 1, 0 },
 102                            { 2, 1 },
 103                            { 2, 3 }, };
 104
 105        if (pio > 1)
 106                control |= 1;   /* TIME */
 107        if (ata_pio_need_iordy(adev))   /* PIO 3/4 require IORDY */
 108                control |= 2;   /* IE */
 109        /* Intel specifies that the prefetch/posting is for disk only */
 110        if (adev->class == ATA_DEV_ATA)
 111                control |= 4;   /* PPE */
 112
 113        spin_lock_irqsave(&efar_lock, flags);
 114
 115        pci_read_config_word(dev, master_port, &master_data);
 116
 117        /* Set PPE, IE, and TIME as appropriate */
 118        if (adev->devno == 0) {
 119                master_data &= 0xCCF0;
 120                master_data |= control;
 121                master_data |= (timings[pio][0] << 12) |
 122                        (timings[pio][1] << 8);
 123        } else {
 124                int shift = 4 * ap->port_no;
 125                u8 slave_data;
 126
 127                master_data &= 0xFF0F;
 128                master_data |= (control << 4);
 129
 130                /* Slave timing in separate register */
 131                pci_read_config_byte(dev, 0x44, &slave_data);
 132                slave_data &= ap->port_no ? 0x0F : 0xF0;
 133                slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift;
 134                pci_write_config_byte(dev, 0x44, slave_data);
 135        }
 136
 137        master_data |= 0x4000;  /* Ensure SITRE is set */
 138        pci_write_config_word(dev, master_port, master_data);
 139
 140        pci_read_config_byte(dev, 0x48, &udma_enable);
 141        udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
 142        pci_write_config_byte(dev, 0x48, udma_enable);
 143        spin_unlock_irqrestore(&efar_lock, flags);
 144}
 145
 146/**
 147 *      efar_set_dmamode - Initialize host controller PATA DMA timings
 148 *      @ap: Port whose timings we are configuring
 149 *      @adev: Device to program
 150 *
 151 *      Set UDMA/MWDMA mode for device, in host controller PCI config space.
 152 *
 153 *      LOCKING:
 154 *      None (inherited from caller).
 155 */
 156
 157static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev)
 158{
 159        struct pci_dev *dev     = to_pci_dev(ap->host->dev);
 160        u8 master_port          = ap->port_no ? 0x42 : 0x40;
 161        u16 master_data;
 162        u8 speed                = adev->dma_mode;
 163        int devid               = adev->devno + 2 * ap->port_no;
 164        unsigned long flags;
 165        u8 udma_enable;
 166
 167        static const     /* ISP  RTC */
 168        u8 timings[][2] = { { 0, 0 },
 169                            { 0, 0 },
 170                            { 1, 0 },
 171                            { 2, 1 },
 172                            { 2, 3 }, };
 173
 174        spin_lock_irqsave(&efar_lock, flags);
 175
 176        pci_read_config_word(dev, master_port, &master_data);
 177        pci_read_config_byte(dev, 0x48, &udma_enable);
 178
 179        if (speed >= XFER_UDMA_0) {
 180                unsigned int udma       = adev->dma_mode - XFER_UDMA_0;
 181                u16 udma_timing;
 182
 183                udma_enable |= (1 << devid);
 184
 185                /* Load the UDMA mode number */
 186                pci_read_config_word(dev, 0x4A, &udma_timing);
 187                udma_timing &= ~(7 << (4 * devid));
 188                udma_timing |= udma << (4 * devid);
 189                pci_write_config_word(dev, 0x4A, udma_timing);
 190        } else {
 191                /*
 192                 * MWDMA is driven by the PIO timings. We must also enable
 193                 * IORDY unconditionally along with TIME1. PPE has already
 194                 * been set when the PIO timing was set.
 195                 */
 196                unsigned int mwdma      = adev->dma_mode - XFER_MW_DMA_0;
 197                unsigned int control;
 198                u8 slave_data;
 199                const unsigned int needed_pio[3] = {
 200                        XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
 201                };
 202                int pio = needed_pio[mwdma] - XFER_PIO_0;
 203
 204                control = 3;    /* IORDY|TIME1 */
 205
 206                /* If the drive MWDMA is faster than it can do PIO then
 207                   we must force PIO into PIO0 */
 208
 209                if (adev->pio_mode < needed_pio[mwdma])
 210                        /* Enable DMA timing only */
 211                        control |= 8;   /* PIO cycles in PIO0 */
 212
 213                if (adev->devno) {      /* Slave */
 214                        master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
 215                        master_data |= control << 4;
 216                        pci_read_config_byte(dev, 0x44, &slave_data);
 217                        slave_data &= ap->port_no ? 0x0F : 0xF0;
 218                        /* Load the matching timing */
 219                        slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
 220                        pci_write_config_byte(dev, 0x44, slave_data);
 221                } else {        /* Master */
 222                        master_data &= 0xCCF4;  /* Mask out IORDY|TIME1|DMAONLY
 223                                                   and master timing bits */
 224                        master_data |= control;
 225                        master_data |=
 226                                (timings[pio][0] << 12) |
 227                                (timings[pio][1] << 8);
 228                }
 229                udma_enable &= ~(1 << devid);
 230                pci_write_config_word(dev, master_port, master_data);
 231        }
 232        pci_write_config_byte(dev, 0x48, udma_enable);
 233        spin_unlock_irqrestore(&efar_lock, flags);
 234}
 235
 236static struct scsi_host_template efar_sht = {
 237        ATA_BMDMA_SHT(DRV_NAME),
 238};
 239
 240static struct ata_port_operations efar_ops = {
 241        .inherits               = &ata_bmdma_port_ops,
 242        .cable_detect           = efar_cable_detect,
 243        .set_piomode            = efar_set_piomode,
 244        .set_dmamode            = efar_set_dmamode,
 245        .prereset               = efar_pre_reset,
 246};
 247
 248
 249/**
 250 *      efar_init_one - Register EFAR ATA PCI device with kernel services
 251 *      @pdev: PCI device to register
 252 *      @ent: Entry in efar_pci_tbl matching with @pdev
 253 *
 254 *      Called from kernel PCI layer.
 255 *
 256 *      LOCKING:
 257 *      Inherited from PCI layer (may sleep).
 258 *
 259 *      RETURNS:
 260 *      Zero on success, or -ERRNO value.
 261 */
 262
 263static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 264{
 265        static const struct ata_port_info info = {
 266                .flags          = ATA_FLAG_SLAVE_POSS,
 267                .pio_mask       = ATA_PIO4,
 268                .mwdma_mask     = ATA_MWDMA12_ONLY,
 269                .udma_mask      = ATA_UDMA4,
 270                .port_ops       = &efar_ops,
 271        };
 272        const struct ata_port_info *ppi[] = { &info, &info };
 273
 274        ata_print_version_once(&pdev->dev, DRV_VERSION);
 275
 276        return ata_pci_bmdma_init_one(pdev, ppi, &efar_sht, NULL,
 277                                      ATA_HOST_PARALLEL_SCAN);
 278}
 279
 280static const struct pci_device_id efar_pci_tbl[] = {
 281        { PCI_VDEVICE(EFAR, 0x9130), },
 282
 283        { }     /* terminate list */
 284};
 285
 286static struct pci_driver efar_pci_driver = {
 287        .name                   = DRV_NAME,
 288        .id_table               = efar_pci_tbl,
 289        .probe                  = efar_init_one,
 290        .remove                 = ata_pci_remove_one,
 291#ifdef CONFIG_PM_SLEEP
 292        .suspend                = ata_pci_device_suspend,
 293        .resume                 = ata_pci_device_resume,
 294#endif
 295};
 296
 297module_pci_driver(efar_pci_driver);
 298
 299MODULE_AUTHOR("Alan Cox");
 300MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
 301MODULE_LICENSE("GPL");
 302MODULE_DEVICE_TABLE(pci, efar_pci_tbl);
 303MODULE_VERSION(DRV_VERSION);
 304