LXR linux/drivers/clocksource/timer-fttmr010.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Faraday Technology FTTMR010 timer driver
   4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
   5 *
   6 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
   7 * Copyright (C) 2001-2006 Storlink, Corp.
   8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
   9 */
  10#include <linux/interrupt.h>
  11#include <linux/io.h>
  12#include <linux/of.h>
  13#include <linux/of_address.h>
  14#include <linux/of_irq.h>
  15#include <linux/clockchips.h>
  16#include <linux/clocksource.h>
  17#include <linux/sched_clock.h>
  18#include <linux/clk.h>
  19#include <linux/slab.h>
  20#include <linux/bitops.h>
  21#include <linux/delay.h>
  22
  23/*
  24 * Register definitions for the timers
  25 */
  26#define TIMER1_COUNT            (0x00)
  27#define TIMER1_LOAD             (0x04)
  28#define TIMER1_MATCH1           (0x08)
  29#define TIMER1_MATCH2           (0x0c)
  30#define TIMER2_COUNT            (0x10)
  31#define TIMER2_LOAD             (0x14)
  32#define TIMER2_MATCH1           (0x18)
  33#define TIMER2_MATCH2           (0x1c)
  34#define TIMER3_COUNT            (0x20)
  35#define TIMER3_LOAD             (0x24)
  36#define TIMER3_MATCH1           (0x28)
  37#define TIMER3_MATCH2           (0x2c)
  38#define TIMER_CR                (0x30)
  39#define TIMER_INTR_STATE        (0x34)
  40#define TIMER_INTR_MASK         (0x38)
  41
  42#define TIMER_1_CR_ENABLE       BIT(0)
  43#define TIMER_1_CR_CLOCK        BIT(1)
  44#define TIMER_1_CR_INT          BIT(2)
  45#define TIMER_2_CR_ENABLE       BIT(3)
  46#define TIMER_2_CR_CLOCK        BIT(4)
  47#define TIMER_2_CR_INT          BIT(5)
  48#define TIMER_3_CR_ENABLE       BIT(6)
  49#define TIMER_3_CR_CLOCK        BIT(7)
  50#define TIMER_3_CR_INT          BIT(8)
  51#define TIMER_1_CR_UPDOWN       BIT(9)
  52#define TIMER_2_CR_UPDOWN       BIT(10)
  53#define TIMER_3_CR_UPDOWN       BIT(11)
  54
  55/*
  56 * The Aspeed AST2400 moves bits around in the control register
  57 * and lacks bits for setting the timer to count upwards.
  58 */
  59#define TIMER_1_CR_ASPEED_ENABLE        BIT(0)
  60#define TIMER_1_CR_ASPEED_CLOCK         BIT(1)
  61#define TIMER_1_CR_ASPEED_INT           BIT(2)
  62#define TIMER_2_CR_ASPEED_ENABLE        BIT(4)
  63#define TIMER_2_CR_ASPEED_CLOCK         BIT(5)
  64#define TIMER_2_CR_ASPEED_INT           BIT(6)
  65#define TIMER_3_CR_ASPEED_ENABLE        BIT(8)
  66#define TIMER_3_CR_ASPEED_CLOCK         BIT(9)
  67#define TIMER_3_CR_ASPEED_INT           BIT(10)
  68
  69#define TIMER_1_INT_MATCH1      BIT(0)
  70#define TIMER_1_INT_MATCH2      BIT(1)
  71#define TIMER_1_INT_OVERFLOW    BIT(2)
  72#define TIMER_2_INT_MATCH1      BIT(3)
  73#define TIMER_2_INT_MATCH2      BIT(4)
  74#define TIMER_2_INT_OVERFLOW    BIT(5)
  75#define TIMER_3_INT_MATCH1      BIT(6)
  76#define TIMER_3_INT_MATCH2      BIT(7)
  77#define TIMER_3_INT_OVERFLOW    BIT(8)
  78#define TIMER_INT_ALL_MASK      0x1ff
  79
  80struct fttmr010 {
  81        void __iomem *base;
  82        unsigned int tick_rate;
  83        bool count_down;
  84        u32 t1_enable_val;
  85        struct clock_event_device clkevt;
  86#ifdef CONFIG_ARM
  87        struct delay_timer delay_timer;
  88#endif
  89};
  90
  91/*
  92 * A local singleton used by sched_clock and delay timer reads, which are
  93 * fast and stateless
  94 */
  95static struct fttmr010 *local_fttmr;
  96
  97static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
  98{
  99        return container_of(evt, struct fttmr010, clkevt);
 100}
 101
 102static unsigned long fttmr010_read_current_timer_up(void)
 103{
 104        return readl(local_fttmr->base + TIMER2_COUNT);
 105}
 106
 107static unsigned long fttmr010_read_current_timer_down(void)
 108{
 109        return ~readl(local_fttmr->base + TIMER2_COUNT);
 110}
 111
 112static u64 notrace fttmr010_read_sched_clock_up(void)
 113{
 114        return fttmr010_read_current_timer_up();
 115}
 116
 117static u64 notrace fttmr010_read_sched_clock_down(void)
 118{
 119        return fttmr010_read_current_timer_down();
 120}
 121
 122static int fttmr010_timer_set_next_event(unsigned long cycles,
 123                                       struct clock_event_device *evt)
 124{
 125        struct fttmr010 *fttmr010 = to_fttmr010(evt);
 126        u32 cr;
 127
 128        /* Stop */
 129        cr = readl(fttmr010->base + TIMER_CR);
 130        cr &= ~fttmr010->t1_enable_val;
 131        writel(cr, fttmr010->base + TIMER_CR);
 132
 133        if (fttmr010->count_down) {
 134                /*
 135                 * ASPEED Timer Controller will load TIMER1_LOAD register
 136                 * into TIMER1_COUNT register when the timer is re-enabled.
 137                 */
 138                writel(cycles, fttmr010->base + TIMER1_LOAD);
 139        } else {
 140                /* Setup the match register forward in time */
 141                cr = readl(fttmr010->base + TIMER1_COUNT);
 142                writel(cr + cycles, fttmr010->base + TIMER1_MATCH1);
 143        }
 144
 145        /* Start */
 146        cr = readl(fttmr010->base + TIMER_CR);
 147        cr |= fttmr010->t1_enable_val;
 148        writel(cr, fttmr010->base + TIMER_CR);
 149
 150        return 0;
 151}
 152
 153static int fttmr010_timer_shutdown(struct clock_event_device *evt)
 154{
 155        struct fttmr010 *fttmr010 = to_fttmr010(evt);
 156        u32 cr;
 157
 158        /* Stop */
 159        cr = readl(fttmr010->base + TIMER_CR);
 160        cr &= ~fttmr010->t1_enable_val;
 161        writel(cr, fttmr010->base + TIMER_CR);
 162
 163        return 0;
 164}
 165
 166static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
 167{
 168        struct fttmr010 *fttmr010 = to_fttmr010(evt);
 169        u32 cr;
 170
 171        /* Stop */
 172        cr = readl(fttmr010->base + TIMER_CR);
 173        cr &= ~fttmr010->t1_enable_val;
 174        writel(cr, fttmr010->base + TIMER_CR);
 175
 176        /* Setup counter start from 0 or ~0 */
 177        writel(0, fttmr010->base + TIMER1_COUNT);
 178        if (fttmr010->count_down)
 179                writel(~0, fttmr010->base + TIMER1_LOAD);
 180        else
 181                writel(0, fttmr010->base + TIMER1_LOAD);
 182
 183        /* Enable interrupt */
 184        cr = readl(fttmr010->base + TIMER_INTR_MASK);
 185        cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
 186        cr |= TIMER_1_INT_MATCH1;
 187        writel(cr, fttmr010->base + TIMER_INTR_MASK);
 188
 189        return 0;
 190}
 191
 192static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
 193{
 194        struct fttmr010 *fttmr010 = to_fttmr010(evt);
 195        u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
 196        u32 cr;
 197
 198        /* Stop */
 199        cr = readl(fttmr010->base + TIMER_CR);
 200        cr &= ~fttmr010->t1_enable_val;
 201        writel(cr, fttmr010->base + TIMER_CR);
 202
 203        /* Setup timer to fire at 1/HZ intervals. */
 204        if (fttmr010->count_down) {
 205                writel(period, fttmr010->base + TIMER1_LOAD);
 206                writel(0, fttmr010->base + TIMER1_MATCH1);
 207        } else {
 208                cr = 0xffffffff - (period - 1);
 209                writel(cr, fttmr010->base + TIMER1_COUNT);
 210                writel(cr, fttmr010->base + TIMER1_LOAD);
 211
 212                /* Enable interrupt on overflow */
 213                cr = readl(fttmr010->base + TIMER_INTR_MASK);
 214                cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
 215                cr |= TIMER_1_INT_OVERFLOW;
 216                writel(cr, fttmr010->base + TIMER_INTR_MASK);
 217        }
 218
 219        /* Start the timer */
 220        cr = readl(fttmr010->base + TIMER_CR);
 221        cr |= fttmr010->t1_enable_val;
 222        writel(cr, fttmr010->base + TIMER_CR);
 223
 224        return 0;
 225}
 226
 227/*
 228 * IRQ handler for the timer
 229 */
 230static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
 231{
 232        struct clock_event_device *evt = dev_id;
 233
 234        evt->event_handler(evt);
 235        return IRQ_HANDLED;
 236}
 237
 238static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed)
 239{
 240        struct fttmr010 *fttmr010;
 241        int irq;
 242        struct clk *clk;
 243        int ret;
 244        u32 val;
 245
 246        /*
 247         * These implementations require a clock reference.
 248         * FIXME: we currently only support clocking using PCLK
 249         * and using EXTCLK is not supported in the driver.
 250         */
 251        clk = of_clk_get_by_name(np, "PCLK");
 252        if (IS_ERR(clk)) {
 253                pr_err("could not get PCLK\n");
 254                return PTR_ERR(clk);
 255        }
 256        ret = clk_prepare_enable(clk);
 257        if (ret) {
 258                pr_err("failed to enable PCLK\n");
 259                return ret;
 260        }
 261
 262        fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
 263        if (!fttmr010) {
 264                ret = -ENOMEM;
 265                goto out_disable_clock;
 266        }
 267        fttmr010->tick_rate = clk_get_rate(clk);
 268
 269        fttmr010->base = of_iomap(np, 0);
 270        if (!fttmr010->base) {
 271                pr_err("Can't remap registers\n");
 272                ret = -ENXIO;
 273                goto out_free;
 274        }
 275        /* IRQ for timer 1 */
 276        irq = irq_of_parse_and_map(np, 0);
 277        if (irq <= 0) {
 278                pr_err("Can't parse IRQ\n");
 279                ret = -EINVAL;
 280                goto out_unmap;
 281        }
 282
 283        /*
 284         * The Aspeed AST2400 moves bits around in the control register,
 285         * otherwise it works the same.
 286         */
 287        if (is_aspeed) {
 288                fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE |
 289                        TIMER_1_CR_ASPEED_INT;
 290                /* Downward not available */
 291                fttmr010->count_down = true;
 292        } else {
 293                fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT;
 294        }
 295
 296        /*
 297         * Reset the interrupt mask and status
 298         */
 299        writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
 300        writel(0, fttmr010->base + TIMER_INTR_STATE);
 301
 302        /*
 303         * Enable timer 1 count up, timer 2 count up, except on Aspeed,
 304         * where everything just counts down.
 305         */
 306        if (is_aspeed)
 307                val = TIMER_2_CR_ASPEED_ENABLE;
 308        else {
 309                val = TIMER_2_CR_ENABLE;
 310                if (!fttmr010->count_down)
 311                        val |= TIMER_1_CR_UPDOWN | TIMER_2_CR_UPDOWN;
 312        }
 313        writel(val, fttmr010->base + TIMER_CR);
 314
 315        /*
 316         * Setup free-running clocksource timer (interrupts
 317         * disabled.)
 318         */
 319        local_fttmr = fttmr010;
 320        writel(0, fttmr010->base + TIMER2_COUNT);
 321        writel(0, fttmr010->base + TIMER2_MATCH1);
 322        writel(0, fttmr010->base + TIMER2_MATCH2);
 323
 324        if (fttmr010->count_down) {
 325                writel(~0, fttmr010->base + TIMER2_LOAD);
 326                clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
 327                                      "FTTMR010-TIMER2",
 328                                      fttmr010->tick_rate,
 329                                      300, 32, clocksource_mmio_readl_down);
 330                sched_clock_register(fttmr010_read_sched_clock_down, 32,
 331                                     fttmr010->tick_rate);
 332        } else {
 333                writel(0, fttmr010->base + TIMER2_LOAD);
 334                clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
 335                                      "FTTMR010-TIMER2",
 336                                      fttmr010->tick_rate,
 337                                      300, 32, clocksource_mmio_readl_up);
 338                sched_clock_register(fttmr010_read_sched_clock_up, 32,
 339                                     fttmr010->tick_rate);
 340        }
 341
 342        /*
 343         * Setup clockevent timer (interrupt-driven) on timer 1.
 344         */
 345        writel(0, fttmr010->base + TIMER1_COUNT);
 346        writel(0, fttmr010->base + TIMER1_LOAD);
 347        writel(0, fttmr010->base + TIMER1_MATCH1);
 348        writel(0, fttmr010->base + TIMER1_MATCH2);
 349        ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER,
 350                          "FTTMR010-TIMER1", &fttmr010->clkevt);
 351        if (ret) {
 352                pr_err("FTTMR010-TIMER1 no IRQ\n");
 353                goto out_unmap;
 354        }
 355
 356        fttmr010->clkevt.name = "FTTMR010-TIMER1";
 357        /* Reasonably fast and accurate clock event */
 358        fttmr010->clkevt.rating = 300;
 359        fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
 360                CLOCK_EVT_FEAT_ONESHOT;
 361        fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
 362        fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown;
 363        fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
 364        fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
 365        fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown;
 366        fttmr010->clkevt.cpumask = cpumask_of(0);
 367        fttmr010->clkevt.irq = irq;
 368        clockevents_config_and_register(&fttmr010->clkevt,
 369                                        fttmr010->tick_rate,
 370                                        1, 0xffffffff);
 371
 372#ifdef CONFIG_ARM
 373        /* Also use this timer for delays */
 374        if (fttmr010->count_down)
 375                fttmr010->delay_timer.read_current_timer =
 376                        fttmr010_read_current_timer_down;
 377        else
 378                fttmr010->delay_timer.read_current_timer =
 379                        fttmr010_read_current_timer_up;
 380        fttmr010->delay_timer.freq = fttmr010->tick_rate;
 381        register_current_timer_delay(&fttmr010->delay_timer);
 382#endif
 383
 384        return 0;
 385
 386out_unmap:
 387        iounmap(fttmr010->base);
 388out_free:
 389        kfree(fttmr010);
 390out_disable_clock:
 391        clk_disable_unprepare(clk);
 392
 393        return ret;
 394}
 395
 396static __init int aspeed_timer_init(struct device_node *np)
 397{
 398        return fttmr010_common_init(np, true);
 399}
 400
 401static __init int fttmr010_timer_init(struct device_node *np)
 402{
 403        return fttmr010_common_init(np, false);
 404}
 405
 406TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
 407TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
 408TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
 409TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
 410TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);
 411