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12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/gpio/driver.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/spinlock.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/of.h>
23
24#define DRIVER_NAME "zynq-gpio"
25
26
27#define ZYNQ_GPIO_MAX_BANK 4
28#define ZYNQMP_GPIO_MAX_BANK 6
29#define VERSAL_GPIO_MAX_BANK 4
30#define VERSAL_UNUSED_BANKS 2
31
32#define ZYNQ_GPIO_BANK0_NGPIO 32
33#define ZYNQ_GPIO_BANK1_NGPIO 22
34#define ZYNQ_GPIO_BANK2_NGPIO 32
35#define ZYNQ_GPIO_BANK3_NGPIO 32
36
37#define ZYNQMP_GPIO_BANK0_NGPIO 26
38#define ZYNQMP_GPIO_BANK1_NGPIO 26
39#define ZYNQMP_GPIO_BANK2_NGPIO 26
40#define ZYNQMP_GPIO_BANK3_NGPIO 32
41#define ZYNQMP_GPIO_BANK4_NGPIO 32
42#define ZYNQMP_GPIO_BANK5_NGPIO 32
43
44#define ZYNQ_GPIO_NR_GPIOS 118
45#define ZYNQMP_GPIO_NR_GPIOS 174
46
47#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
48#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
49 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
50#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
51#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
52 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
53#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
54#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
55 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
56#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
57#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
58 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
59#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
60#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
61 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
62#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
63#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
64 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
65
66
67
68#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
69
70#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
71
72#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
73#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
74
75#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
76
77#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
78
79#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
80
81#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
82
83#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
84
85#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
86
87#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
88
89#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
90
91#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
92
93
94#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
95
96
97#define ZYNQ_GPIO_MID_PIN_NUM 16
98
99
100#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
101
102
103#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
104#define GPIO_QUIRK_DATA_RO_BUG BIT(1)
105#define GPIO_QUIRK_VERSAL BIT(2)
106
107struct gpio_regs {
108 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
109 u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
110 u32 dirm[ZYNQMP_GPIO_MAX_BANK];
111 u32 outen[ZYNQMP_GPIO_MAX_BANK];
112 u32 int_en[ZYNQMP_GPIO_MAX_BANK];
113 u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
114 u32 int_type[ZYNQMP_GPIO_MAX_BANK];
115 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
116 u32 int_any[ZYNQMP_GPIO_MAX_BANK];
117};
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128
129struct zynq_gpio {
130 struct gpio_chip chip;
131 void __iomem *base_addr;
132 struct clk *clk;
133 int irq;
134 const struct zynq_platform_data *p_data;
135 struct gpio_regs context;
136 spinlock_t dirlock;
137};
138
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147
148struct zynq_platform_data {
149 const char *label;
150 u32 quirks;
151 u16 ngpio;
152 int max_bank;
153 int bank_min[ZYNQMP_GPIO_MAX_BANK];
154 int bank_max[ZYNQMP_GPIO_MAX_BANK];
155};
156
157static struct irq_chip zynq_gpio_level_irqchip;
158static struct irq_chip zynq_gpio_edge_irqchip;
159
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165
166static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
167{
168 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
169}
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176
177static int gpio_data_ro_bug(struct zynq_gpio *gpio)
178{
179 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
180}
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193
194static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
195 unsigned int *bank_num,
196 unsigned int *bank_pin_num,
197 struct zynq_gpio *gpio)
198{
199 int bank;
200
201 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
202 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
203 (pin_num <= gpio->p_data->bank_max[bank])) {
204 *bank_num = bank;
205 *bank_pin_num = pin_num -
206 gpio->p_data->bank_min[bank];
207 return;
208 }
209 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
210 bank = bank + VERSAL_UNUSED_BANKS;
211 }
212
213
214 WARN(true, "invalid GPIO pin number: %u", pin_num);
215 *bank_num = 0;
216 *bank_pin_num = 0;
217}
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227
228static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
229{
230 u32 data;
231 unsigned int bank_num, bank_pin_num;
232 struct zynq_gpio *gpio = gpiochip_get_data(chip);
233
234 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
235
236 if (gpio_data_ro_bug(gpio)) {
237 if (zynq_gpio_is_zynq(gpio)) {
238 if (bank_num <= 1) {
239 data = readl_relaxed(gpio->base_addr +
240 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
241 } else {
242 data = readl_relaxed(gpio->base_addr +
243 ZYNQ_GPIO_DATA_OFFSET(bank_num));
244 }
245 } else {
246 if (bank_num <= 2) {
247 data = readl_relaxed(gpio->base_addr +
248 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
249 } else {
250 data = readl_relaxed(gpio->base_addr +
251 ZYNQ_GPIO_DATA_OFFSET(bank_num));
252 }
253 }
254 } else {
255 data = readl_relaxed(gpio->base_addr +
256 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
257 }
258 return (data >> bank_pin_num) & 1;
259}
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270
271static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
272 int state)
273{
274 unsigned int reg_offset, bank_num, bank_pin_num;
275 struct zynq_gpio *gpio = gpiochip_get_data(chip);
276
277 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
278
279 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
280
281 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
282 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
283 } else {
284 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
285 }
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290
291 state = !!state;
292 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
293 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
294
295 writel_relaxed(state, gpio->base_addr + reg_offset);
296}
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307
308static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
309{
310 u32 reg;
311 unsigned int bank_num, bank_pin_num;
312 unsigned long flags;
313 struct zynq_gpio *gpio = gpiochip_get_data(chip);
314
315 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
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320
321 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
322 (bank_pin_num == 7 || bank_pin_num == 8))
323 return -EINVAL;
324
325
326 spin_lock_irqsave(&gpio->dirlock, flags);
327 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
328 reg &= ~BIT(bank_pin_num);
329 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
330 spin_unlock_irqrestore(&gpio->dirlock, flags);
331
332 return 0;
333}
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346
347static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
348 int state)
349{
350 u32 reg;
351 unsigned int bank_num, bank_pin_num;
352 unsigned long flags;
353 struct zynq_gpio *gpio = gpiochip_get_data(chip);
354
355 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
356
357
358 spin_lock_irqsave(&gpio->dirlock, flags);
359 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
360 reg |= BIT(bank_pin_num);
361 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
362
363
364 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
365 reg |= BIT(bank_pin_num);
366 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
367 spin_unlock_irqrestore(&gpio->dirlock, flags);
368
369
370 zynq_gpio_set_value(chip, pin, state);
371 return 0;
372}
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382
383static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
384{
385 u32 reg;
386 unsigned int bank_num, bank_pin_num;
387 struct zynq_gpio *gpio = gpiochip_get_data(chip);
388
389 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
390
391 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
392
393 return !(reg & BIT(bank_pin_num));
394}
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404static void zynq_gpio_irq_mask(struct irq_data *irq_data)
405{
406 unsigned int device_pin_num, bank_num, bank_pin_num;
407 struct zynq_gpio *gpio =
408 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
409
410 device_pin_num = irq_data->hwirq;
411 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
412 writel_relaxed(BIT(bank_pin_num),
413 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
414}
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424
425static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
426{
427 unsigned int device_pin_num, bank_num, bank_pin_num;
428 struct zynq_gpio *gpio =
429 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
430
431 device_pin_num = irq_data->hwirq;
432 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
433 writel_relaxed(BIT(bank_pin_num),
434 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
435}
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444
445static void zynq_gpio_irq_ack(struct irq_data *irq_data)
446{
447 unsigned int device_pin_num, bank_num, bank_pin_num;
448 struct zynq_gpio *gpio =
449 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
450
451 device_pin_num = irq_data->hwirq;
452 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
453 writel_relaxed(BIT(bank_pin_num),
454 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
455}
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463
464static void zynq_gpio_irq_enable(struct irq_data *irq_data)
465{
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476 zynq_gpio_irq_ack(irq_data);
477 zynq_gpio_irq_unmask(irq_data);
478}
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494
495static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
496{
497 u32 int_type, int_pol, int_any;
498 unsigned int device_pin_num, bank_num, bank_pin_num;
499 struct zynq_gpio *gpio =
500 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
501
502 device_pin_num = irq_data->hwirq;
503 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
504
505 int_type = readl_relaxed(gpio->base_addr +
506 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
507 int_pol = readl_relaxed(gpio->base_addr +
508 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
509 int_any = readl_relaxed(gpio->base_addr +
510 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
511
512
513
514
515
516 switch (type) {
517 case IRQ_TYPE_EDGE_RISING:
518 int_type |= BIT(bank_pin_num);
519 int_pol |= BIT(bank_pin_num);
520 int_any &= ~BIT(bank_pin_num);
521 break;
522 case IRQ_TYPE_EDGE_FALLING:
523 int_type |= BIT(bank_pin_num);
524 int_pol &= ~BIT(bank_pin_num);
525 int_any &= ~BIT(bank_pin_num);
526 break;
527 case IRQ_TYPE_EDGE_BOTH:
528 int_type |= BIT(bank_pin_num);
529 int_any |= BIT(bank_pin_num);
530 break;
531 case IRQ_TYPE_LEVEL_HIGH:
532 int_type &= ~BIT(bank_pin_num);
533 int_pol |= BIT(bank_pin_num);
534 break;
535 case IRQ_TYPE_LEVEL_LOW:
536 int_type &= ~BIT(bank_pin_num);
537 int_pol &= ~BIT(bank_pin_num);
538 break;
539 default:
540 return -EINVAL;
541 }
542
543 writel_relaxed(int_type,
544 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
545 writel_relaxed(int_pol,
546 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
547 writel_relaxed(int_any,
548 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
549
550 if (type & IRQ_TYPE_LEVEL_MASK)
551 irq_set_chip_handler_name_locked(irq_data,
552 &zynq_gpio_level_irqchip,
553 handle_fasteoi_irq, NULL);
554 else
555 irq_set_chip_handler_name_locked(irq_data,
556 &zynq_gpio_edge_irqchip,
557 handle_level_irq, NULL);
558
559 return 0;
560}
561
562static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
563{
564 struct zynq_gpio *gpio =
565 gpiochip_get_data(irq_data_get_irq_chip_data(data));
566
567 irq_set_irq_wake(gpio->irq, on);
568
569 return 0;
570}
571
572static int zynq_gpio_irq_reqres(struct irq_data *d)
573{
574 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
575 int ret;
576
577 ret = pm_runtime_get_sync(chip->parent);
578 if (ret < 0)
579 return ret;
580
581 return gpiochip_reqres_irq(chip, d->hwirq);
582}
583
584static void zynq_gpio_irq_relres(struct irq_data *d)
585{
586 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
587
588 gpiochip_relres_irq(chip, d->hwirq);
589 pm_runtime_put(chip->parent);
590}
591
592
593static struct irq_chip zynq_gpio_level_irqchip = {
594 .name = DRIVER_NAME,
595 .irq_enable = zynq_gpio_irq_enable,
596 .irq_eoi = zynq_gpio_irq_ack,
597 .irq_mask = zynq_gpio_irq_mask,
598 .irq_unmask = zynq_gpio_irq_unmask,
599 .irq_set_type = zynq_gpio_set_irq_type,
600 .irq_set_wake = zynq_gpio_set_wake,
601 .irq_request_resources = zynq_gpio_irq_reqres,
602 .irq_release_resources = zynq_gpio_irq_relres,
603 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
604 IRQCHIP_MASK_ON_SUSPEND,
605};
606
607static struct irq_chip zynq_gpio_edge_irqchip = {
608 .name = DRIVER_NAME,
609 .irq_enable = zynq_gpio_irq_enable,
610 .irq_ack = zynq_gpio_irq_ack,
611 .irq_mask = zynq_gpio_irq_mask,
612 .irq_unmask = zynq_gpio_irq_unmask,
613 .irq_set_type = zynq_gpio_set_irq_type,
614 .irq_set_wake = zynq_gpio_set_wake,
615 .irq_request_resources = zynq_gpio_irq_reqres,
616 .irq_release_resources = zynq_gpio_irq_relres,
617 .flags = IRQCHIP_MASK_ON_SUSPEND,
618};
619
620static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
621 unsigned int bank_num,
622 unsigned long pending)
623{
624 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
625 struct irq_domain *irqdomain = gpio->chip.irq.domain;
626 int offset;
627
628 if (!pending)
629 return;
630
631 for_each_set_bit(offset, &pending, 32) {
632 unsigned int gpio_irq;
633
634 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
635 generic_handle_irq(gpio_irq);
636 }
637}
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647
648
649static void zynq_gpio_irqhandler(struct irq_desc *desc)
650{
651 u32 int_sts, int_enb;
652 unsigned int bank_num;
653 struct zynq_gpio *gpio =
654 gpiochip_get_data(irq_desc_get_handler_data(desc));
655 struct irq_chip *irqchip = irq_desc_get_chip(desc);
656
657 chained_irq_enter(irqchip, desc);
658
659 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
660 int_sts = readl_relaxed(gpio->base_addr +
661 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
662 int_enb = readl_relaxed(gpio->base_addr +
663 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
664 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
665 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
666 bank_num = bank_num + VERSAL_UNUSED_BANKS;
667 }
668
669 chained_irq_exit(irqchip, desc);
670}
671
672static void zynq_gpio_save_context(struct zynq_gpio *gpio)
673{
674 unsigned int bank_num;
675
676 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
677 gpio->context.datalsw[bank_num] =
678 readl_relaxed(gpio->base_addr +
679 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
680 gpio->context.datamsw[bank_num] =
681 readl_relaxed(gpio->base_addr +
682 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
683 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
684 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
685 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
686 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
687 gpio->context.int_type[bank_num] =
688 readl_relaxed(gpio->base_addr +
689 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
690 gpio->context.int_polarity[bank_num] =
691 readl_relaxed(gpio->base_addr +
692 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
693 gpio->context.int_any[bank_num] =
694 readl_relaxed(gpio->base_addr +
695 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
696 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
697 bank_num = bank_num + VERSAL_UNUSED_BANKS;
698 }
699}
700
701static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
702{
703 unsigned int bank_num;
704
705 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
706 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
707 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
708 writel_relaxed(gpio->context.datalsw[bank_num],
709 gpio->base_addr +
710 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
711 writel_relaxed(gpio->context.datamsw[bank_num],
712 gpio->base_addr +
713 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
714 writel_relaxed(gpio->context.dirm[bank_num],
715 gpio->base_addr +
716 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
717 writel_relaxed(gpio->context.int_type[bank_num],
718 gpio->base_addr +
719 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
720 writel_relaxed(gpio->context.int_polarity[bank_num],
721 gpio->base_addr +
722 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
723 writel_relaxed(gpio->context.int_any[bank_num],
724 gpio->base_addr +
725 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
726 writel_relaxed(~(gpio->context.int_en[bank_num]),
727 gpio->base_addr +
728 ZYNQ_GPIO_INTEN_OFFSET(bank_num));
729 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
730 bank_num = bank_num + VERSAL_UNUSED_BANKS;
731 }
732}
733
734static int __maybe_unused zynq_gpio_suspend(struct device *dev)
735{
736 struct zynq_gpio *gpio = dev_get_drvdata(dev);
737 struct irq_data *data = irq_get_irq_data(gpio->irq);
738
739 if (!device_may_wakeup(dev))
740 disable_irq(gpio->irq);
741
742 if (!irqd_is_wakeup_set(data)) {
743 zynq_gpio_save_context(gpio);
744 return pm_runtime_force_suspend(dev);
745 }
746
747 return 0;
748}
749
750static int __maybe_unused zynq_gpio_resume(struct device *dev)
751{
752 struct zynq_gpio *gpio = dev_get_drvdata(dev);
753 struct irq_data *data = irq_get_irq_data(gpio->irq);
754 int ret;
755
756 if (!device_may_wakeup(dev))
757 enable_irq(gpio->irq);
758
759 if (!irqd_is_wakeup_set(data)) {
760 ret = pm_runtime_force_resume(dev);
761 zynq_gpio_restore_context(gpio);
762 return ret;
763 }
764
765 return 0;
766}
767
768static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
769{
770 struct platform_device *pdev = to_platform_device(dev);
771 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
772
773 clk_disable_unprepare(gpio->clk);
774
775 return 0;
776}
777
778static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
779{
780 struct platform_device *pdev = to_platform_device(dev);
781 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
782
783 return clk_prepare_enable(gpio->clk);
784}
785
786static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)
787{
788 int ret;
789
790 ret = pm_runtime_get_sync(chip->parent);
791
792
793
794
795
796 return ret < 0 ? ret : 0;
797}
798
799static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
800{
801 pm_runtime_put(chip->parent);
802}
803
804static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
805 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
806 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
807 zynq_gpio_runtime_resume, NULL)
808};
809
810static const struct zynq_platform_data versal_gpio_def = {
811 .label = "versal_gpio",
812 .quirks = GPIO_QUIRK_VERSAL,
813 .ngpio = 58,
814 .max_bank = VERSAL_GPIO_MAX_BANK,
815 .bank_min[0] = 0,
816 .bank_max[0] = 25,
817 .bank_min[3] = 26,
818 .bank_max[3] = 57,
819};
820
821static const struct zynq_platform_data zynqmp_gpio_def = {
822 .label = "zynqmp_gpio",
823 .quirks = GPIO_QUIRK_DATA_RO_BUG,
824 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
825 .max_bank = ZYNQMP_GPIO_MAX_BANK,
826 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
827 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
828 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
829 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
830 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
831 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
832 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
833 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
834 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
835 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
836 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
837 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
838};
839
840static const struct zynq_platform_data zynq_gpio_def = {
841 .label = "zynq_gpio",
842 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
843 .ngpio = ZYNQ_GPIO_NR_GPIOS,
844 .max_bank = ZYNQ_GPIO_MAX_BANK,
845 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
846 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
847 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
848 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
849 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
850 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
851 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
852 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
853};
854
855static const struct of_device_id zynq_gpio_of_match[] = {
856 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
857 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
858 { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
859 { }
860};
861MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
862
863
864
865
866
867
868
869
870
871
872
873
874static int zynq_gpio_probe(struct platform_device *pdev)
875{
876 int ret, bank_num;
877 struct zynq_gpio *gpio;
878 struct gpio_chip *chip;
879 struct resource *res;
880 const struct of_device_id *match;
881
882 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
883 if (!gpio)
884 return -ENOMEM;
885
886 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
887 if (!match) {
888 dev_err(&pdev->dev, "of_match_node() failed\n");
889 return -EINVAL;
890 }
891 gpio->p_data = match->data;
892 platform_set_drvdata(pdev, gpio);
893
894 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
895 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
896 if (IS_ERR(gpio->base_addr))
897 return PTR_ERR(gpio->base_addr);
898
899 gpio->irq = platform_get_irq(pdev, 0);
900 if (gpio->irq < 0) {
901 dev_err(&pdev->dev, "invalid IRQ\n");
902 return gpio->irq;
903 }
904
905
906 chip = &gpio->chip;
907 chip->label = gpio->p_data->label;
908 chip->owner = THIS_MODULE;
909 chip->parent = &pdev->dev;
910 chip->get = zynq_gpio_get_value;
911 chip->set = zynq_gpio_set_value;
912 chip->request = zynq_gpio_request;
913 chip->free = zynq_gpio_free;
914 chip->direction_input = zynq_gpio_dir_in;
915 chip->direction_output = zynq_gpio_dir_out;
916 chip->get_direction = zynq_gpio_get_direction;
917 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");
918 chip->ngpio = gpio->p_data->ngpio;
919
920
921 gpio->clk = devm_clk_get(&pdev->dev, NULL);
922 if (IS_ERR(gpio->clk)) {
923 dev_err(&pdev->dev, "input clock not found.\n");
924 return PTR_ERR(gpio->clk);
925 }
926 ret = clk_prepare_enable(gpio->clk);
927 if (ret) {
928 dev_err(&pdev->dev, "Unable to enable clock.\n");
929 return ret;
930 }
931
932 spin_lock_init(&gpio->dirlock);
933
934 pm_runtime_set_active(&pdev->dev);
935 pm_runtime_enable(&pdev->dev);
936 ret = pm_runtime_get_sync(&pdev->dev);
937 if (ret < 0)
938 goto err_pm_dis;
939
940
941 ret = gpiochip_add_data(chip, gpio);
942 if (ret) {
943 dev_err(&pdev->dev, "Failed to add gpio chip\n");
944 goto err_pm_put;
945 }
946
947
948 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
949 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
950 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
951 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
952 bank_num = bank_num + VERSAL_UNUSED_BANKS;
953 }
954
955 ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
956 handle_level_irq, IRQ_TYPE_NONE);
957 if (ret) {
958 dev_err(&pdev->dev, "Failed to add irq chip\n");
959 goto err_rm_gpiochip;
960 }
961
962 gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,
963 zynq_gpio_irqhandler);
964
965 irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);
966 device_init_wakeup(&pdev->dev, 1);
967 pm_runtime_put(&pdev->dev);
968
969 return 0;
970
971err_rm_gpiochip:
972 gpiochip_remove(chip);
973err_pm_put:
974 pm_runtime_put(&pdev->dev);
975err_pm_dis:
976 pm_runtime_disable(&pdev->dev);
977 clk_disable_unprepare(gpio->clk);
978
979 return ret;
980}
981
982
983
984
985
986
987
988static int zynq_gpio_remove(struct platform_device *pdev)
989{
990 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
991
992 pm_runtime_get_sync(&pdev->dev);
993 gpiochip_remove(&gpio->chip);
994 clk_disable_unprepare(gpio->clk);
995 device_set_wakeup_capable(&pdev->dev, 0);
996 pm_runtime_disable(&pdev->dev);
997 return 0;
998}
999
1000static struct platform_driver zynq_gpio_driver = {
1001 .driver = {
1002 .name = DRIVER_NAME,
1003 .pm = &zynq_gpio_dev_pm_ops,
1004 .of_match_table = zynq_gpio_of_match,
1005 },
1006 .probe = zynq_gpio_probe,
1007 .remove = zynq_gpio_remove,
1008};
1009
1010
1011
1012
1013
1014
1015static int __init zynq_gpio_init(void)
1016{
1017 return platform_driver_register(&zynq_gpio_driver);
1018}
1019subsys_initcall(zynq_gpio_init);
1020
1021static void __exit zynq_gpio_exit(void)
1022{
1023 platform_driver_unregister(&zynq_gpio_driver);
1024}
1025module_exit(zynq_gpio_exit);
1026
1027MODULE_AUTHOR("Xilinx Inc.");
1028MODULE_DESCRIPTION("Zynq GPIO driver");
1029MODULE_LICENSE("GPL");
1030