LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3 * All Rights Reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the
   7 * "Software"), to deal in the Software without restriction, including
   8 * without limitation the rights to use, copy, modify, merge, publish,
   9 * distribute, sub license, and/or sell copies of the Software, and to
  10 * permit persons to whom the Software is furnished to do so, subject to
  11 * the following conditions:
  12 *
  13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20 *
  21 * The above copyright notice and this permission notice (including the
  22 * next paragraph) shall be included in all copies or substantial portions
  23 * of the Software.
  24 *
  25 */
  26#ifndef __AMDGPU_GMC_H__
  27#define __AMDGPU_GMC_H__
  28
  29#include <linux/types.h>
  30
  31#include "amdgpu_irq.h"
  32
  33struct firmware;
  34
  35/*
  36 * VMHUB structures, functions & helpers
  37 */
  38struct amdgpu_vmhub {
  39        uint32_t        ctx0_ptb_addr_lo32;
  40        uint32_t        ctx0_ptb_addr_hi32;
  41        uint32_t        vm_inv_eng0_req;
  42        uint32_t        vm_inv_eng0_ack;
  43        uint32_t        vm_context0_cntl;
  44        uint32_t        vm_l2_pro_fault_status;
  45        uint32_t        vm_l2_pro_fault_cntl;
  46};
  47
  48/*
  49 * GPU MC structures, functions & helpers
  50 */
  51struct amdgpu_gmc_funcs {
  52        /* flush the vm tlb via mmio */
  53        void (*flush_gpu_tlb)(struct amdgpu_device *adev,
  54                              uint32_t vmid);
  55        /* flush the vm tlb via ring */
  56        uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
  57                                       uint64_t pd_addr);
  58        /* Change the VMID -> PASID mapping */
  59        void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
  60                                   unsigned pasid);
  61        /* write pte/pde updates using the cpu */
  62        int (*set_pte_pde)(struct amdgpu_device *adev,
  63                           void *cpu_pt_addr, /* cpu addr of page table */
  64                           uint32_t gpu_page_idx, /* pte/pde to update */
  65                           uint64_t addr, /* addr to write into pte/pde */
  66                           uint64_t flags); /* access flags */
  67        /* enable/disable PRT support */
  68        void (*set_prt)(struct amdgpu_device *adev, bool enable);
  69        /* set pte flags based per asic */
  70        uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
  71                                     uint32_t flags);
  72        /* get the pde for a given mc addr */
  73        void (*get_vm_pde)(struct amdgpu_device *adev, int level,
  74                           u64 *dst, u64 *flags);
  75};
  76
  77struct amdgpu_gmc {
  78        resource_size_t         aper_size;
  79        resource_size_t         aper_base;
  80        /* for some chips with <= 32MB we need to lie
  81         * about vram size near mc fb location */
  82        u64                     mc_vram_size;
  83        u64                     visible_vram_size;
  84        u64                     gart_size;
  85        u64                     gart_start;
  86        u64                     gart_end;
  87        u64                     vram_start;
  88        u64                     vram_end;
  89        unsigned                vram_width;
  90        u64                     real_vram_size;
  91        int                     vram_mtrr;
  92        u64                     mc_mask;
  93        const struct firmware   *fw;    /* MC firmware */
  94        uint32_t                fw_version;
  95        struct amdgpu_irq_src   vm_fault;
  96        uint32_t                vram_type;
  97        uint32_t                srbm_soft_reset;
  98        bool                    prt_warning;
  99        uint64_t                stolen_size;
 100        /* apertures */
 101        u64                     shared_aperture_start;
 102        u64                     shared_aperture_end;
 103        u64                     private_aperture_start;
 104        u64                     private_aperture_end;
 105        /* protects concurrent invalidation */
 106        spinlock_t              invalidate_lock;
 107        bool                    translate_further;
 108        struct kfd_vm_fault_info *vm_fault_info;
 109        atomic_t                vm_fault_info_updated;
 110
 111        const struct amdgpu_gmc_funcs   *gmc_funcs;
 112};
 113
 114/**
 115 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
 116 *
 117 * @adev: amdgpu_device pointer
 118 *
 119 * Returns:
 120 * True if full VRAM is visible through the BAR
 121 */
 122static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
 123{
 124        WARN_ON(gmc->real_vram_size < gmc->visible_vram_size);
 125
 126        return (gmc->real_vram_size == gmc->visible_vram_size);
 127}
 128
 129#endif
 130