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12#include <asm/unaligned.h>
13
14#include <drm/bridge/mhl.h>
15#include <drm/drm_crtc.h>
16#include <drm/drm_edid.h>
17#include <drm/drm_encoder.h>
18
19#include <linux/clk.h>
20#include <linux/delay.h>
21#include <linux/extcon.h>
22#include <linux/gpio/consumer.h>
23#include <linux/i2c.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/module.h>
29#include <linux/mutex.h>
30#include <linux/of_graph.h>
31#include <linux/regulator/consumer.h>
32#include <linux/slab.h>
33
34#include <media/rc-core.h>
35
36#include "sil-sii8620.h"
37
38#define SII8620_BURST_BUF_LEN 288
39#define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3)
40
41#define MHL1_MAX_PCLK 75000
42#define MHL1_MAX_PCLK_PP_MODE 150000
43#define MHL3_MAX_PCLK 200000
44#define MHL3_MAX_PCLK_PP_MODE 300000
45
46enum sii8620_mode {
47 CM_DISCONNECTED,
48 CM_DISCOVERY,
49 CM_MHL1,
50 CM_MHL3,
51 CM_ECBUS_S
52};
53
54enum sii8620_sink_type {
55 SINK_NONE,
56 SINK_HDMI,
57 SINK_DVI
58};
59
60enum sii8620_mt_state {
61 MT_STATE_READY,
62 MT_STATE_BUSY,
63 MT_STATE_DONE
64};
65
66struct sii8620 {
67 struct drm_bridge bridge;
68 struct device *dev;
69 struct rc_dev *rc_dev;
70 struct clk *clk_xtal;
71 struct gpio_desc *gpio_reset;
72 struct gpio_desc *gpio_int;
73 struct regulator_bulk_data supplies[2];
74 struct mutex lock;
75 int error;
76 unsigned int use_packed_pixel:1;
77 enum sii8620_mode mode;
78 enum sii8620_sink_type sink_type;
79 u8 cbus_status;
80 u8 stat[MHL_DST_SIZE];
81 u8 xstat[MHL_XDS_SIZE];
82 u8 devcap[MHL_DCAP_SIZE];
83 u8 xdevcap[MHL_XDC_SIZE];
84 bool feature_complete;
85 bool devcap_read;
86 bool sink_detected;
87 struct edid *edid;
88 unsigned int gen2_write_burst:1;
89 enum sii8620_mt_state mt_state;
90 struct extcon_dev *extcon;
91 struct notifier_block extcon_nb;
92 struct work_struct extcon_wq;
93 int cable_state;
94 struct list_head mt_queue;
95 struct {
96 int r_size;
97 int r_count;
98 int rx_ack;
99 int rx_count;
100 u8 rx_buf[32];
101 int tx_count;
102 u8 tx_buf[32];
103 } burst;
104};
105
106struct sii8620_mt_msg;
107
108typedef void (*sii8620_mt_msg_cb)(struct sii8620 *ctx,
109 struct sii8620_mt_msg *msg);
110
111typedef void (*sii8620_cb)(struct sii8620 *ctx, int ret);
112
113struct sii8620_mt_msg {
114 struct list_head node;
115 u8 reg[4];
116 u8 ret;
117 sii8620_mt_msg_cb send;
118 sii8620_mt_msg_cb recv;
119 sii8620_cb continuation;
120};
121
122static const u8 sii8620_i2c_page[] = {
123 0x39,
124 0x3d,
125 0x49,
126 0x4d,
127 0x5d,
128 0x64,
129 0x59,
130 0x61,
131};
132
133static void sii8620_fetch_edid(struct sii8620 *ctx);
134static void sii8620_set_upstream_edid(struct sii8620 *ctx);
135static void sii8620_enable_hpd(struct sii8620 *ctx);
136static void sii8620_mhl_disconnected(struct sii8620 *ctx);
137static void sii8620_disconnect(struct sii8620 *ctx);
138
139static int sii8620_clear_error(struct sii8620 *ctx)
140{
141 int ret = ctx->error;
142
143 ctx->error = 0;
144 return ret;
145}
146
147static void sii8620_read_buf(struct sii8620 *ctx, u16 addr, u8 *buf, int len)
148{
149 struct device *dev = ctx->dev;
150 struct i2c_client *client = to_i2c_client(dev);
151 u8 data = addr;
152 struct i2c_msg msg[] = {
153 {
154 .addr = sii8620_i2c_page[addr >> 8],
155 .flags = client->flags,
156 .len = 1,
157 .buf = &data
158 },
159 {
160 .addr = sii8620_i2c_page[addr >> 8],
161 .flags = client->flags | I2C_M_RD,
162 .len = len,
163 .buf = buf
164 },
165 };
166 int ret;
167
168 if (ctx->error)
169 return;
170
171 ret = i2c_transfer(client->adapter, msg, 2);
172 dev_dbg(dev, "read at %04x: %*ph, %d\n", addr, len, buf, ret);
173
174 if (ret != 2) {
175 dev_err(dev, "Read at %#06x of %d bytes failed with code %d.\n",
176 addr, len, ret);
177 ctx->error = ret < 0 ? ret : -EIO;
178 }
179}
180
181static u8 sii8620_readb(struct sii8620 *ctx, u16 addr)
182{
183 u8 ret;
184
185 sii8620_read_buf(ctx, addr, &ret, 1);
186 return ret;
187}
188
189static void sii8620_write_buf(struct sii8620 *ctx, u16 addr, const u8 *buf,
190 int len)
191{
192 struct device *dev = ctx->dev;
193 struct i2c_client *client = to_i2c_client(dev);
194 u8 data[2];
195 struct i2c_msg msg = {
196 .addr = sii8620_i2c_page[addr >> 8],
197 .flags = client->flags,
198 .len = len + 1,
199 };
200 int ret;
201
202 if (ctx->error)
203 return;
204
205 if (len > 1) {
206 msg.buf = kmalloc(len + 1, GFP_KERNEL);
207 if (!msg.buf) {
208 ctx->error = -ENOMEM;
209 return;
210 }
211 memcpy(msg.buf + 1, buf, len);
212 } else {
213 msg.buf = data;
214 msg.buf[1] = *buf;
215 }
216
217 msg.buf[0] = addr;
218
219 ret = i2c_transfer(client->adapter, &msg, 1);
220 dev_dbg(dev, "write at %04x: %*ph, %d\n", addr, len, buf, ret);
221
222 if (ret != 1) {
223 dev_err(dev, "Write at %#06x of %*ph failed with code %d.\n",
224 addr, len, buf, ret);
225 ctx->error = ret ?: -EIO;
226 }
227
228 if (len > 1)
229 kfree(msg.buf);
230}
231
232#define sii8620_write(ctx, addr, arr...) \
233({\
234 u8 d[] = { arr }; \
235 sii8620_write_buf(ctx, addr, d, ARRAY_SIZE(d)); \
236})
237
238static void __sii8620_write_seq(struct sii8620 *ctx, const u16 *seq, int len)
239{
240 int i;
241
242 for (i = 0; i < len; i += 2)
243 sii8620_write(ctx, seq[i], seq[i + 1]);
244}
245
246#define sii8620_write_seq(ctx, seq...) \
247({\
248 const u16 d[] = { seq }; \
249 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \
250})
251
252#define sii8620_write_seq_static(ctx, seq...) \
253({\
254 static const u16 d[] = { seq }; \
255 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \
256})
257
258static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val)
259{
260 val = (val & mask) | (sii8620_readb(ctx, addr) & ~mask);
261 sii8620_write(ctx, addr, val);
262}
263
264static inline bool sii8620_is_mhl3(struct sii8620 *ctx)
265{
266 return ctx->mode >= CM_MHL3;
267}
268
269static void sii8620_mt_cleanup(struct sii8620 *ctx)
270{
271 struct sii8620_mt_msg *msg, *n;
272
273 list_for_each_entry_safe(msg, n, &ctx->mt_queue, node) {
274 list_del(&msg->node);
275 kfree(msg);
276 }
277 ctx->mt_state = MT_STATE_READY;
278}
279
280static void sii8620_mt_work(struct sii8620 *ctx)
281{
282 struct sii8620_mt_msg *msg;
283
284 if (ctx->error)
285 return;
286 if (ctx->mt_state == MT_STATE_BUSY || list_empty(&ctx->mt_queue))
287 return;
288
289 if (ctx->mt_state == MT_STATE_DONE) {
290 ctx->mt_state = MT_STATE_READY;
291 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg,
292 node);
293 list_del(&msg->node);
294 if (msg->recv)
295 msg->recv(ctx, msg);
296 if (msg->continuation)
297 msg->continuation(ctx, msg->ret);
298 kfree(msg);
299 }
300
301 if (ctx->mt_state != MT_STATE_READY || list_empty(&ctx->mt_queue))
302 return;
303
304 ctx->mt_state = MT_STATE_BUSY;
305 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
306 if (msg->send)
307 msg->send(ctx, msg);
308}
309
310static void sii8620_enable_gen2_write_burst(struct sii8620 *ctx)
311{
312 u8 ctrl = BIT_MDT_RCV_CTRL_MDT_RCV_EN;
313
314 if (ctx->gen2_write_burst)
315 return;
316
317 if (ctx->mode >= CM_MHL1)
318 ctrl |= BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN;
319
320 sii8620_write_seq(ctx,
321 REG_MDT_RCV_TIMEOUT, 100,
322 REG_MDT_RCV_CTRL, ctrl
323 );
324 ctx->gen2_write_burst = 1;
325}
326
327static void sii8620_disable_gen2_write_burst(struct sii8620 *ctx)
328{
329 if (!ctx->gen2_write_burst)
330 return;
331
332 sii8620_write_seq_static(ctx,
333 REG_MDT_XMIT_CTRL, 0,
334 REG_MDT_RCV_CTRL, 0
335 );
336 ctx->gen2_write_burst = 0;
337}
338
339static void sii8620_start_gen2_write_burst(struct sii8620 *ctx)
340{
341 sii8620_write_seq_static(ctx,
342 REG_MDT_INT_1_MASK, BIT_MDT_RCV_TIMEOUT
343 | BIT_MDT_RCV_SM_ABORT_PKT_RCVD | BIT_MDT_RCV_SM_ERROR
344 | BIT_MDT_XMIT_TIMEOUT | BIT_MDT_XMIT_SM_ABORT_PKT_RCVD
345 | BIT_MDT_XMIT_SM_ERROR,
346 REG_MDT_INT_0_MASK, BIT_MDT_XFIFO_EMPTY
347 | BIT_MDT_IDLE_AFTER_HAWB_DISABLE
348 | BIT_MDT_RFIFO_DATA_RDY
349 );
350 sii8620_enable_gen2_write_burst(ctx);
351}
352
353static void sii8620_mt_msc_cmd_send(struct sii8620 *ctx,
354 struct sii8620_mt_msg *msg)
355{
356 if (msg->reg[0] == MHL_SET_INT &&
357 msg->reg[1] == MHL_INT_REG(RCHANGE) &&
358 msg->reg[2] == MHL_INT_RC_FEAT_REQ)
359 sii8620_enable_gen2_write_burst(ctx);
360 else
361 sii8620_disable_gen2_write_burst(ctx);
362
363 switch (msg->reg[0]) {
364 case MHL_WRITE_STAT:
365 case MHL_SET_INT:
366 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg + 1, 2);
367 sii8620_write(ctx, REG_MSC_COMMAND_START,
368 BIT_MSC_COMMAND_START_WRITE_STAT);
369 break;
370 case MHL_MSC_MSG:
371 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg, 3);
372 sii8620_write(ctx, REG_MSC_COMMAND_START,
373 BIT_MSC_COMMAND_START_MSC_MSG);
374 break;
375 case MHL_READ_DEVCAP_REG:
376 case MHL_READ_XDEVCAP_REG:
377 sii8620_write(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg[1]);
378 sii8620_write(ctx, REG_MSC_COMMAND_START,
379 BIT_MSC_COMMAND_START_READ_DEVCAP);
380 break;
381 default:
382 dev_err(ctx->dev, "%s: command %#x not supported\n", __func__,
383 msg->reg[0]);
384 }
385}
386
387static struct sii8620_mt_msg *sii8620_mt_msg_new(struct sii8620 *ctx)
388{
389 struct sii8620_mt_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL);
390
391 if (!msg)
392 ctx->error = -ENOMEM;
393 else
394 list_add_tail(&msg->node, &ctx->mt_queue);
395
396 return msg;
397}
398
399static void sii8620_mt_set_cont(struct sii8620 *ctx, sii8620_cb cont)
400{
401 struct sii8620_mt_msg *msg;
402
403 if (ctx->error)
404 return;
405
406 if (list_empty(&ctx->mt_queue)) {
407 ctx->error = -EINVAL;
408 return;
409 }
410 msg = list_last_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
411 msg->continuation = cont;
412}
413
414static void sii8620_mt_msc_cmd(struct sii8620 *ctx, u8 cmd, u8 arg1, u8 arg2)
415{
416 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
417
418 if (!msg)
419 return;
420
421 msg->reg[0] = cmd;
422 msg->reg[1] = arg1;
423 msg->reg[2] = arg2;
424 msg->send = sii8620_mt_msc_cmd_send;
425}
426
427static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val)
428{
429 sii8620_mt_msc_cmd(ctx, MHL_WRITE_STAT, reg, val);
430}
431
432static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask)
433{
434 sii8620_mt_msc_cmd(ctx, MHL_SET_INT, irq, mask);
435}
436
437static void sii8620_mt_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data)
438{
439 sii8620_mt_msc_cmd(ctx, MHL_MSC_MSG, cmd, data);
440}
441
442static void sii8620_mt_rap(struct sii8620 *ctx, u8 code)
443{
444 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code);
445}
446
447static void sii8620_mt_rcpk(struct sii8620 *ctx, u8 code)
448{
449 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPK, code);
450}
451
452static void sii8620_mt_rcpe(struct sii8620 *ctx, u8 code)
453{
454 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPE, code);
455}
456
457static void sii8620_mt_read_devcap_send(struct sii8620 *ctx,
458 struct sii8620_mt_msg *msg)
459{
460 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP
461 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
462 | BIT_EDID_CTRL_EDID_MODE_EN;
463
464 if (msg->reg[0] == MHL_READ_XDEVCAP)
465 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN;
466
467 sii8620_write_seq(ctx,
468 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE,
469 REG_EDID_CTRL, ctrl,
470 REG_TPI_CBUS_START, BIT_TPI_CBUS_START_GET_DEVCAP_START
471 );
472}
473
474
475static void sii8620_update_array(u8 *dst, u8 *src, int count)
476{
477 while (--count >= 0) {
478 *src ^= *dst;
479 *dst++ ^= *src++;
480 }
481}
482
483static void sii8620_identify_sink(struct sii8620 *ctx)
484{
485 static const char * const sink_str[] = {
486 [SINK_NONE] = "NONE",
487 [SINK_HDMI] = "HDMI",
488 [SINK_DVI] = "DVI"
489 };
490
491 char sink_name[20];
492 struct device *dev = ctx->dev;
493
494 if (!ctx->sink_detected || !ctx->devcap_read)
495 return;
496
497 sii8620_fetch_edid(ctx);
498 if (!ctx->edid) {
499 dev_err(ctx->dev, "Cannot fetch EDID\n");
500 sii8620_mhl_disconnected(ctx);
501 return;
502 }
503 sii8620_set_upstream_edid(ctx);
504
505 if (drm_detect_hdmi_monitor(ctx->edid))
506 ctx->sink_type = SINK_HDMI;
507 else
508 ctx->sink_type = SINK_DVI;
509
510 drm_edid_get_monitor_name(ctx->edid, sink_name, ARRAY_SIZE(sink_name));
511
512 dev_info(dev, "detected sink(type: %s): %s\n",
513 sink_str[ctx->sink_type], sink_name);
514}
515
516static void sii8620_mr_devcap(struct sii8620 *ctx)
517{
518 u8 dcap[MHL_DCAP_SIZE];
519 struct device *dev = ctx->dev;
520
521 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, dcap, MHL_DCAP_SIZE);
522 if (ctx->error < 0)
523 return;
524
525 dev_info(dev, "detected dongle MHL %d.%d, ChipID %02x%02x:%02x%02x\n",
526 dcap[MHL_DCAP_MHL_VERSION] / 16,
527 dcap[MHL_DCAP_MHL_VERSION] % 16,
528 dcap[MHL_DCAP_ADOPTER_ID_H], dcap[MHL_DCAP_ADOPTER_ID_L],
529 dcap[MHL_DCAP_DEVICE_ID_H], dcap[MHL_DCAP_DEVICE_ID_L]);
530 sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE);
531 ctx->devcap_read = true;
532 sii8620_identify_sink(ctx);
533}
534
535static void sii8620_mr_xdevcap(struct sii8620 *ctx)
536{
537 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, ctx->xdevcap,
538 MHL_XDC_SIZE);
539}
540
541static void sii8620_mt_read_devcap_recv(struct sii8620 *ctx,
542 struct sii8620_mt_msg *msg)
543{
544 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP
545 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
546 | BIT_EDID_CTRL_EDID_MODE_EN;
547
548 if (msg->reg[0] == MHL_READ_XDEVCAP)
549 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN;
550
551 sii8620_write_seq(ctx,
552 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE | BIT_INTR9_EDID_DONE
553 | BIT_INTR9_EDID_ERROR,
554 REG_EDID_CTRL, ctrl,
555 REG_EDID_FIFO_ADDR, 0
556 );
557
558 if (msg->reg[0] == MHL_READ_XDEVCAP)
559 sii8620_mr_xdevcap(ctx);
560 else
561 sii8620_mr_devcap(ctx);
562}
563
564static void sii8620_mt_read_devcap(struct sii8620 *ctx, bool xdevcap)
565{
566 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
567
568 if (!msg)
569 return;
570
571 msg->reg[0] = xdevcap ? MHL_READ_XDEVCAP : MHL_READ_DEVCAP;
572 msg->send = sii8620_mt_read_devcap_send;
573 msg->recv = sii8620_mt_read_devcap_recv;
574}
575
576static void sii8620_mt_read_devcap_reg_recv(struct sii8620 *ctx,
577 struct sii8620_mt_msg *msg)
578{
579 u8 reg = msg->reg[1] & 0x7f;
580
581 if (msg->reg[1] & 0x80)
582 ctx->xdevcap[reg] = msg->ret;
583 else
584 ctx->devcap[reg] = msg->ret;
585}
586
587static void sii8620_mt_read_devcap_reg(struct sii8620 *ctx, u8 reg)
588{
589 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
590
591 if (!msg)
592 return;
593
594 msg->reg[0] = (reg & 0x80) ? MHL_READ_XDEVCAP_REG : MHL_READ_DEVCAP_REG;
595 msg->reg[1] = reg;
596 msg->send = sii8620_mt_msc_cmd_send;
597 msg->recv = sii8620_mt_read_devcap_reg_recv;
598}
599
600static inline void sii8620_mt_read_xdevcap_reg(struct sii8620 *ctx, u8 reg)
601{
602 sii8620_mt_read_devcap_reg(ctx, reg | 0x80);
603}
604
605static void *sii8620_burst_get_tx_buf(struct sii8620 *ctx, int len)
606{
607 u8 *buf = &ctx->burst.tx_buf[ctx->burst.tx_count];
608 int size = len + 2;
609
610 if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) {
611 dev_err(ctx->dev, "TX-BLK buffer exhausted\n");
612 ctx->error = -EINVAL;
613 return NULL;
614 }
615
616 ctx->burst.tx_count += size;
617 buf[1] = len;
618
619 return buf + 2;
620}
621
622static u8 *sii8620_burst_get_rx_buf(struct sii8620 *ctx, int len)
623{
624 u8 *buf = &ctx->burst.rx_buf[ctx->burst.rx_count];
625 int size = len + 1;
626
627 if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) {
628 dev_err(ctx->dev, "RX-BLK buffer exhausted\n");
629 ctx->error = -EINVAL;
630 return NULL;
631 }
632
633 ctx->burst.rx_count += size;
634 buf[0] = len;
635
636 return buf + 1;
637}
638
639static void sii8620_burst_send(struct sii8620 *ctx)
640{
641 int tx_left = ctx->burst.tx_count;
642 u8 *d = ctx->burst.tx_buf;
643
644 while (tx_left > 0) {
645 int len = d[1] + 2;
646
647 if (ctx->burst.r_count + len > ctx->burst.r_size)
648 break;
649 d[0] = min(ctx->burst.rx_ack, 255);
650 ctx->burst.rx_ack -= d[0];
651 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, d, len);
652 ctx->burst.r_count += len;
653 tx_left -= len;
654 d += len;
655 }
656
657 ctx->burst.tx_count = tx_left;
658
659 while (ctx->burst.rx_ack > 0) {
660 u8 b[2] = { min(ctx->burst.rx_ack, 255), 0 };
661
662 if (ctx->burst.r_count + 2 > ctx->burst.r_size)
663 break;
664 ctx->burst.rx_ack -= b[0];
665 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, b, 2);
666 ctx->burst.r_count += 2;
667 }
668}
669
670static void sii8620_burst_receive(struct sii8620 *ctx)
671{
672 u8 buf[3], *d;
673 int count;
674
675 sii8620_read_buf(ctx, REG_EMSCRFIFOBCNTL, buf, 2);
676 count = get_unaligned_le16(buf);
677 while (count > 0) {
678 int len = min(count, 3);
679
680 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, buf, len);
681 count -= len;
682 ctx->burst.rx_ack += len - 1;
683 ctx->burst.r_count -= buf[1];
684 if (ctx->burst.r_count < 0)
685 ctx->burst.r_count = 0;
686
687 if (len < 3 || !buf[2])
688 continue;
689
690 len = buf[2];
691 d = sii8620_burst_get_rx_buf(ctx, len);
692 if (!d)
693 continue;
694 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, d, len);
695 count -= len;
696 ctx->burst.rx_ack += len;
697 }
698}
699
700static void sii8620_burst_tx_rbuf_info(struct sii8620 *ctx, int size)
701{
702 struct mhl_burst_blk_rcv_buffer_info *d =
703 sii8620_burst_get_tx_buf(ctx, sizeof(*d));
704 if (!d)
705 return;
706
707 d->id = cpu_to_be16(MHL_BURST_ID_BLK_RCV_BUFFER_INFO);
708 d->size = cpu_to_le16(size);
709}
710
711static u8 sii8620_checksum(void *ptr, int size)
712{
713 u8 *d = ptr, sum = 0;
714
715 while (size--)
716 sum += *d++;
717
718 return sum;
719}
720
721static void sii8620_mhl_burst_hdr_set(struct mhl3_burst_header *h,
722 enum mhl_burst_id id)
723{
724 h->id = cpu_to_be16(id);
725 h->total_entries = 1;
726 h->sequence_index = 1;
727}
728
729static void sii8620_burst_tx_bits_per_pixel_fmt(struct sii8620 *ctx, u8 fmt)
730{
731 struct mhl_burst_bits_per_pixel_fmt *d;
732 const int size = sizeof(*d) + sizeof(d->desc[0]);
733
734 d = sii8620_burst_get_tx_buf(ctx, size);
735 if (!d)
736 return;
737
738 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_BITS_PER_PIXEL_FMT);
739 d->num_entries = 1;
740 d->desc[0].stream_id = 0;
741 d->desc[0].pixel_format = fmt;
742 d->hdr.checksum -= sii8620_checksum(d, size);
743}
744
745static void sii8620_burst_rx_all(struct sii8620 *ctx)
746{
747 u8 *d = ctx->burst.rx_buf;
748 int count = ctx->burst.rx_count;
749
750 while (count-- > 0) {
751 int len = *d++;
752 int id = get_unaligned_be16(&d[0]);
753
754 switch (id) {
755 case MHL_BURST_ID_BLK_RCV_BUFFER_INFO:
756 ctx->burst.r_size = get_unaligned_le16(&d[2]);
757 break;
758 default:
759 break;
760 }
761 count -= len;
762 d += len;
763 }
764 ctx->burst.rx_count = 0;
765}
766
767static void sii8620_fetch_edid(struct sii8620 *ctx)
768{
769 u8 lm_ddc, ddc_cmd, int3, cbus;
770 unsigned long timeout;
771 int fetched, i;
772 int edid_len = EDID_LENGTH;
773 u8 *edid;
774
775 sii8620_readb(ctx, REG_CBUS_STATUS);
776 lm_ddc = sii8620_readb(ctx, REG_LM_DDC);
777 ddc_cmd = sii8620_readb(ctx, REG_DDC_CMD);
778
779 sii8620_write_seq(ctx,
780 REG_INTR9_MASK, 0,
781 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO,
782 REG_HDCP2X_POLL_CS, 0x71,
783 REG_HDCP2X_CTRL_0, BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX,
784 REG_LM_DDC, lm_ddc | BIT_LM_DDC_SW_TPI_EN_DISABLED,
785 );
786
787 for (i = 0; i < 256; ++i) {
788 u8 ddc_stat = sii8620_readb(ctx, REG_DDC_STATUS);
789
790 if (!(ddc_stat & BIT_DDC_STATUS_DDC_I2C_IN_PROG))
791 break;
792 sii8620_write(ctx, REG_DDC_STATUS,
793 BIT_DDC_STATUS_DDC_FIFO_EMPTY);
794 }
795
796 sii8620_write(ctx, REG_DDC_ADDR, 0x50 << 1);
797
798 edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
799 if (!edid) {
800 ctx->error = -ENOMEM;
801 return;
802 }
803
804#define FETCH_SIZE 16
805 for (fetched = 0; fetched < edid_len; fetched += FETCH_SIZE) {
806 sii8620_readb(ctx, REG_DDC_STATUS);
807 sii8620_write_seq(ctx,
808 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_ABORT,
809 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO,
810 REG_DDC_STATUS, BIT_DDC_STATUS_DDC_FIFO_EMPTY
811 );
812 sii8620_write_seq(ctx,
813 REG_DDC_SEGM, fetched >> 8,
814 REG_DDC_OFFSET, fetched & 0xff,
815 REG_DDC_DIN_CNT1, FETCH_SIZE,
816 REG_DDC_DIN_CNT2, 0,
817 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_ENH_DDC_READ_NO_ACK
818 );
819
820 int3 = 0;
821 timeout = jiffies + msecs_to_jiffies(200);
822 for (;;) {
823 cbus = sii8620_readb(ctx, REG_CBUS_STATUS);
824 if (~cbus & BIT_CBUS_STATUS_CBUS_CONNECTED) {
825 kfree(edid);
826 edid = NULL;
827 goto end;
828 }
829 if (int3 & BIT_DDC_CMD_DONE) {
830 if (sii8620_readb(ctx, REG_DDC_DOUT_CNT)
831 >= FETCH_SIZE)
832 break;
833 } else {
834 int3 = sii8620_readb(ctx, REG_INTR3);
835 }
836 if (time_is_before_jiffies(timeout)) {
837 ctx->error = -ETIMEDOUT;
838 dev_err(ctx->dev, "timeout during EDID read\n");
839 kfree(edid);
840 edid = NULL;
841 goto end;
842 }
843 usleep_range(10, 20);
844 }
845
846 sii8620_read_buf(ctx, REG_DDC_DATA, edid + fetched, FETCH_SIZE);
847 if (fetched + FETCH_SIZE == EDID_LENGTH) {
848 u8 ext = ((struct edid *)edid)->extensions;
849
850 if (ext) {
851 u8 *new_edid;
852
853 edid_len += ext * EDID_LENGTH;
854 new_edid = krealloc(edid, edid_len, GFP_KERNEL);
855 if (!new_edid) {
856 kfree(edid);
857 ctx->error = -ENOMEM;
858 return;
859 }
860 edid = new_edid;
861 }
862 }
863 }
864
865 sii8620_write_seq(ctx,
866 REG_INTR3_MASK, BIT_DDC_CMD_DONE,
867 REG_LM_DDC, lm_ddc
868 );
869
870end:
871 kfree(ctx->edid);
872 ctx->edid = (struct edid *)edid;
873}
874
875static void sii8620_set_upstream_edid(struct sii8620 *ctx)
876{
877 sii8620_setbits(ctx, REG_DPD, BIT_DPD_PDNRX12 | BIT_DPD_PDIDCK_N
878 | BIT_DPD_PD_MHL_CLK_N, 0xff);
879
880 sii8620_write_seq_static(ctx,
881 REG_RX_HDMI_CTRL3, 0x00,
882 REG_PKT_FILTER_0, 0xFF,
883 REG_PKT_FILTER_1, 0xFF,
884 REG_ALICE0_BW_I2C, 0x06
885 );
886
887 sii8620_setbits(ctx, REG_RX_HDMI_CLR_BUFFER,
888 BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN, 0xff);
889
890 sii8620_write_seq_static(ctx,
891 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
892 | BIT_EDID_CTRL_EDID_MODE_EN,
893 REG_EDID_FIFO_ADDR, 0,
894 );
895
896 sii8620_write_buf(ctx, REG_EDID_FIFO_WR_DATA, (u8 *)ctx->edid,
897 (ctx->edid->extensions + 1) * EDID_LENGTH);
898
899 sii8620_write_seq_static(ctx,
900 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID
901 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
902 | BIT_EDID_CTRL_EDID_MODE_EN,
903 REG_INTR5_MASK, BIT_INTR_SCDT_CHANGE,
904 REG_INTR9_MASK, 0
905 );
906}
907
908static void sii8620_xtal_set_rate(struct sii8620 *ctx)
909{
910 static const struct {
911 unsigned int rate;
912 u8 div;
913 u8 tp1;
914 } rates[] = {
915 { 19200, 0x04, 0x53 },
916 { 20000, 0x04, 0x62 },
917 { 24000, 0x05, 0x75 },
918 { 30000, 0x06, 0x92 },
919 { 38400, 0x0c, 0xbc },
920 };
921 unsigned long rate = clk_get_rate(ctx->clk_xtal) / 1000;
922 int i;
923
924 for (i = 0; i < ARRAY_SIZE(rates) - 1; ++i)
925 if (rate <= rates[i].rate)
926 break;
927
928 if (rate != rates[i].rate)
929 dev_err(ctx->dev, "xtal clock rate(%lukHz) not supported, setting MHL for %ukHz.\n",
930 rate, rates[i].rate);
931
932 sii8620_write(ctx, REG_DIV_CTL_MAIN, rates[i].div);
933 sii8620_write(ctx, REG_HDCP2X_TP1, rates[i].tp1);
934}
935
936static int sii8620_hw_on(struct sii8620 *ctx)
937{
938 int ret;
939
940 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
941 if (ret)
942 return ret;
943
944 usleep_range(10000, 20000);
945 ret = clk_prepare_enable(ctx->clk_xtal);
946 if (ret)
947 return ret;
948
949 msleep(100);
950 gpiod_set_value(ctx->gpio_reset, 0);
951 msleep(100);
952
953 return 0;
954}
955
956static int sii8620_hw_off(struct sii8620 *ctx)
957{
958 clk_disable_unprepare(ctx->clk_xtal);
959 gpiod_set_value(ctx->gpio_reset, 1);
960 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
961}
962
963static void sii8620_cbus_reset(struct sii8620 *ctx)
964{
965 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST
966 | BIT_PWD_SRST_CBUS_RST_SW_EN);
967 usleep_range(10000, 20000);
968 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN);
969}
970
971static void sii8620_set_auto_zone(struct sii8620 *ctx)
972{
973 if (ctx->mode != CM_MHL1) {
974 sii8620_write_seq_static(ctx,
975 REG_TX_ZONE_CTL1, 0x0,
976 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
977 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
978 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE
979 );
980 } else {
981 sii8620_write_seq_static(ctx,
982 REG_TX_ZONE_CTL1, VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE,
983 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
984 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE
985 );
986 }
987}
988
989static void sii8620_stop_video(struct sii8620 *ctx)
990{
991 u8 uninitialized_var(val);
992
993 sii8620_write_seq_static(ctx,
994 REG_TPI_INTR_EN, 0,
995 REG_HDCP2X_INTR0_MASK, 0,
996 REG_TPI_COPP_DATA2, 0,
997 REG_TPI_INTR_ST0, ~0,
998 );
999
1000 switch (ctx->sink_type) {
1001 case SINK_DVI:
1002 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN
1003 | BIT_TPI_SC_TPI_AV_MUTE;
1004 break;
1005 case SINK_HDMI:
1006 default:
1007 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN
1008 | BIT_TPI_SC_TPI_AV_MUTE
1009 | BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI;
1010 break;
1011 }
1012
1013 sii8620_write(ctx, REG_TPI_SC, val);
1014}
1015
1016static void sii8620_set_format(struct sii8620 *ctx)
1017{
1018 u8 out_fmt;
1019
1020 if (sii8620_is_mhl3(ctx)) {
1021 sii8620_setbits(ctx, REG_M3_P0CTRL,
1022 BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED,
1023 ctx->use_packed_pixel ? ~0 : 0);
1024 } else {
1025 if (ctx->use_packed_pixel) {
1026 sii8620_write_seq_static(ctx,
1027 REG_VID_MODE, BIT_VID_MODE_M1080P,
1028 REG_MHL_TOP_CTL, BIT_MHL_TOP_CTL_MHL_PP_SEL | 1,
1029 REG_MHLTX_CTL6, 0x60
1030 );
1031 } else {
1032 sii8620_write_seq_static(ctx,
1033 REG_VID_MODE, 0,
1034 REG_MHL_TOP_CTL, 1,
1035 REG_MHLTX_CTL6, 0xa0
1036 );
1037 }
1038 }
1039
1040 if (ctx->use_packed_pixel)
1041 out_fmt = VAL_TPI_FORMAT(YCBCR422, FULL);
1042 else
1043 out_fmt = VAL_TPI_FORMAT(RGB, FULL);
1044
1045 sii8620_write_seq(ctx,
1046 REG_TPI_INPUT, VAL_TPI_FORMAT(RGB, FULL),
1047 REG_TPI_OUTPUT, out_fmt,
1048 );
1049}
1050
1051static int mhl3_infoframe_init(struct mhl3_infoframe *frame)
1052{
1053 memset(frame, 0, sizeof(*frame));
1054
1055 frame->version = 3;
1056 frame->hev_format = -1;
1057 return 0;
1058}
1059
1060static ssize_t mhl3_infoframe_pack(struct mhl3_infoframe *frame,
1061 void *buffer, size_t size)
1062{
1063 const int frm_len = HDMI_INFOFRAME_HEADER_SIZE + MHL3_INFOFRAME_SIZE;
1064 u8 *ptr = buffer;
1065
1066 if (size < frm_len)
1067 return -ENOSPC;
1068
1069 memset(buffer, 0, size);
1070 ptr[0] = HDMI_INFOFRAME_TYPE_VENDOR;
1071 ptr[1] = frame->version;
1072 ptr[2] = MHL3_INFOFRAME_SIZE;
1073 ptr[4] = MHL3_IEEE_OUI & 0xff;
1074 ptr[5] = (MHL3_IEEE_OUI >> 8) & 0xff;
1075 ptr[6] = (MHL3_IEEE_OUI >> 16) & 0xff;
1076 ptr[7] = frame->video_format & 0x3;
1077 ptr[7] |= (frame->format_type & 0x7) << 2;
1078 ptr[7] |= frame->sep_audio ? BIT(5) : 0;
1079 if (frame->hev_format >= 0) {
1080 ptr[9] = 1;
1081 ptr[10] = (frame->hev_format >> 8) & 0xff;
1082 ptr[11] = frame->hev_format & 0xff;
1083 }
1084 if (frame->av_delay) {
1085 bool sign = frame->av_delay < 0;
1086 int delay = sign ? -frame->av_delay : frame->av_delay;
1087
1088 ptr[12] = (delay >> 16) & 0xf;
1089 if (sign)
1090 ptr[12] |= BIT(4);
1091 ptr[13] = (delay >> 8) & 0xff;
1092 ptr[14] = delay & 0xff;
1093 }
1094 ptr[3] -= sii8620_checksum(buffer, frm_len);
1095 return frm_len;
1096}
1097
1098static void sii8620_set_infoframes(struct sii8620 *ctx,
1099 struct drm_display_mode *mode)
1100{
1101 struct mhl3_infoframe mhl_frm;
1102 union hdmi_infoframe frm;
1103 u8 buf[31];
1104 int ret;
1105
1106 ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi,
1107 mode,
1108 true);
1109 if (ctx->use_packed_pixel)
1110 frm.avi.colorspace = HDMI_COLORSPACE_YUV422;
1111
1112 if (!ret)
1113 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, ARRAY_SIZE(buf));
1114 if (ret > 0)
1115 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, buf + 3, ret - 3);
1116
1117 if (!sii8620_is_mhl3(ctx) || !ctx->use_packed_pixel) {
1118 sii8620_write(ctx, REG_TPI_SC,
1119 BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI);
1120 sii8620_write(ctx, REG_PKT_FILTER_0,
1121 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT |
1122 BIT_PKT_FILTER_0_DROP_MPEG_PKT |
1123 BIT_PKT_FILTER_0_DROP_GCP_PKT,
1124 BIT_PKT_FILTER_1_DROP_GEN_PKT);
1125 return;
1126 }
1127
1128 sii8620_write(ctx, REG_PKT_FILTER_0,
1129 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT |
1130 BIT_PKT_FILTER_0_DROP_MPEG_PKT |
1131 BIT_PKT_FILTER_0_DROP_AVI_PKT |
1132 BIT_PKT_FILTER_0_DROP_GCP_PKT,
1133 BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS |
1134 BIT_PKT_FILTER_1_DROP_GEN_PKT |
1135 BIT_PKT_FILTER_1_DROP_VSIF_PKT);
1136
1137 sii8620_write(ctx, REG_TPI_INFO_FSEL, BIT_TPI_INFO_FSEL_EN
1138 | BIT_TPI_INFO_FSEL_RPT | VAL_TPI_INFO_FSEL_VSI);
1139 ret = mhl3_infoframe_init(&mhl_frm);
1140 if (!ret)
1141 ret = mhl3_infoframe_pack(&mhl_frm, buf, ARRAY_SIZE(buf));
1142 sii8620_write_buf(ctx, REG_TPI_INFO_B0, buf, ret);
1143}
1144
1145static void sii8620_start_video(struct sii8620 *ctx)
1146{
1147 struct drm_display_mode *mode =
1148 &ctx->bridge.encoder->crtc->state->adjusted_mode;
1149
1150 if (!sii8620_is_mhl3(ctx))
1151 sii8620_stop_video(ctx);
1152
1153 if (ctx->sink_type == SINK_DVI && !sii8620_is_mhl3(ctx)) {
1154 sii8620_write(ctx, REG_RX_HDMI_CTRL2,
1155 VAL_RX_HDMI_CTRL2_DEFVAL);
1156 sii8620_write(ctx, REG_TPI_SC, 0);
1157 return;
1158 }
1159
1160 sii8620_write_seq_static(ctx,
1161 REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL
1162 | BIT_RX_HDMI_CTRL2_USE_AV_MUTE,
1163 REG_VID_OVRRD, BIT_VID_OVRRD_PP_AUTO_DISABLE
1164 | BIT_VID_OVRRD_M1080P_OVRRD);
1165 sii8620_set_format(ctx);
1166
1167 if (!sii8620_is_mhl3(ctx)) {
1168 u8 link_mode = MHL_DST_LM_PATH_ENABLED;
1169
1170 if (ctx->use_packed_pixel)
1171 link_mode |= MHL_DST_LM_CLK_MODE_PACKED_PIXEL;
1172 else
1173 link_mode |= MHL_DST_LM_CLK_MODE_NORMAL;
1174
1175 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), link_mode);
1176 sii8620_set_auto_zone(ctx);
1177 } else {
1178 static const struct {
1179 int max_clk;
1180 u8 zone;
1181 u8 link_rate;
1182 u8 rrp_decode;
1183 } clk_spec[] = {
1184 { 150000, VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS,
1185 MHL_XDS_LINK_RATE_1_5_GBPS, 0x38 },
1186 { 300000, VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS,
1187 MHL_XDS_LINK_RATE_3_0_GBPS, 0x40 },
1188 { 600000, VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS,
1189 MHL_XDS_LINK_RATE_6_0_GBPS, 0x40 },
1190 };
1191 u8 p0_ctrl = BIT_M3_P0CTRL_MHL3_P0_PORT_EN;
1192 int clk = mode->clock * (ctx->use_packed_pixel ? 2 : 3);
1193 int i;
1194
1195 for (i = 0; i < ARRAY_SIZE(clk_spec) - 1; ++i)
1196 if (clk < clk_spec[i].max_clk)
1197 break;
1198
1199 if (100 * clk >= 98 * clk_spec[i].max_clk)
1200 p0_ctrl |= BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN;
1201
1202 sii8620_burst_tx_bits_per_pixel_fmt(ctx, ctx->use_packed_pixel);
1203 sii8620_burst_send(ctx);
1204 sii8620_write_seq(ctx,
1205 REG_MHL_DP_CTL0, 0xf0,
1206 REG_MHL3_TX_ZONE_CTL, clk_spec[i].zone);
1207 sii8620_setbits(ctx, REG_M3_P0CTRL,
1208 BIT_M3_P0CTRL_MHL3_P0_PORT_EN
1209 | BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN, p0_ctrl);
1210 sii8620_setbits(ctx, REG_M3_POSTM, MSK_M3_POSTM_RRP_DECODE,
1211 clk_spec[i].rrp_decode);
1212 sii8620_write_seq_static(ctx,
1213 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE
1214 | BIT_M3_CTRL_H2M_SWRST,
1215 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE
1216 );
1217 sii8620_mt_write_stat(ctx, MHL_XDS_REG(AVLINK_MODE_CONTROL),
1218 clk_spec[i].link_rate);
1219 }
1220
1221 sii8620_set_infoframes(ctx, mode);
1222}
1223
1224static void sii8620_disable_hpd(struct sii8620 *ctx)
1225{
1226 sii8620_setbits(ctx, REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID, 0);
1227 sii8620_write_seq_static(ctx,
1228 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN,
1229 REG_INTR8_MASK, 0
1230 );
1231}
1232
1233static void sii8620_enable_hpd(struct sii8620 *ctx)
1234{
1235 sii8620_setbits(ctx, REG_TMDS_CSTAT_P3,
1236 BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS
1237 | BIT_TMDS_CSTAT_P3_CLR_AVI, ~0);
1238 sii8620_write_seq_static(ctx,
1239 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN
1240 | BIT_HPD_CTRL_HPD_HIGH,
1241 );
1242}
1243
1244static void sii8620_mhl_discover(struct sii8620 *ctx)
1245{
1246 sii8620_write_seq_static(ctx,
1247 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1248 | BIT_DISC_CTRL9_DISC_PULSE_PROCEED,
1249 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_5K, VAL_PUP_20K),
1250 REG_CBUS_DISC_INTR0_MASK, BIT_MHL3_EST_INT
1251 | BIT_MHL_EST_INT
1252 | BIT_NOT_MHL_EST_INT
1253 | BIT_CBUS_MHL3_DISCON_INT
1254 | BIT_CBUS_MHL12_DISCON_INT
1255 | BIT_RGND_READY_INT,
1256 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1257 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
1258 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE,
1259 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE
1260 | BIT_MHL_DP_CTL0_TX_OE_OVR,
1261 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
1262 REG_MHL_DP_CTL1, 0xA2,
1263 REG_MHL_DP_CTL2, 0x03,
1264 REG_MHL_DP_CTL3, 0x35,
1265 REG_MHL_DP_CTL5, 0x02,
1266 REG_MHL_DP_CTL6, 0x02,
1267 REG_MHL_DP_CTL7, 0x03,
1268 REG_COC_CTLC, 0xFF,
1269 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12
1270 | BIT_DPD_OSC_EN | BIT_DPD_PWRON_HSIC,
1271 REG_COC_INTR_MASK, BIT_COC_PLL_LOCK_STATUS_CHANGE
1272 | BIT_COC_CALIBRATION_DONE,
1273 REG_CBUS_INT_1_MASK, BIT_CBUS_MSC_ABORT_RCVD
1274 | BIT_CBUS_CMD_ABORT,
1275 REG_CBUS_INT_0_MASK, BIT_CBUS_MSC_MT_DONE
1276 | BIT_CBUS_HPD_CHG
1277 | BIT_CBUS_MSC_MR_WRITE_STAT
1278 | BIT_CBUS_MSC_MR_MSC_MSG
1279 | BIT_CBUS_MSC_MR_WRITE_BURST
1280 | BIT_CBUS_MSC_MR_SET_INT
1281 | BIT_CBUS_MSC_MT_DONE_NACK
1282 );
1283}
1284
1285static void sii8620_peer_specific_init(struct sii8620 *ctx)
1286{
1287 if (sii8620_is_mhl3(ctx))
1288 sii8620_write_seq_static(ctx,
1289 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD,
1290 REG_EMSCINTRMASK1,
1291 BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR
1292 );
1293 else
1294 sii8620_write_seq_static(ctx,
1295 REG_HDCP2X_INTR0_MASK, 0x00,
1296 REG_EMSCINTRMASK1, 0x00,
1297 REG_HDCP2X_INTR0, 0xFF,
1298 REG_INTR1, 0xFF,
1299 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD
1300 | BIT_SYS_CTRL1_TX_CTRL_HDMI
1301 );
1302}
1303
1304#define SII8620_MHL_VERSION 0x32
1305#define SII8620_SCRATCHPAD_SIZE 16
1306#define SII8620_INT_STAT_SIZE 0x33
1307
1308static void sii8620_set_dev_cap(struct sii8620 *ctx)
1309{
1310 static const u8 devcap[MHL_DCAP_SIZE] = {
1311 [MHL_DCAP_MHL_VERSION] = SII8620_MHL_VERSION,
1312 [MHL_DCAP_CAT] = MHL_DCAP_CAT_SOURCE | MHL_DCAP_CAT_POWER,
1313 [MHL_DCAP_ADOPTER_ID_H] = 0x01,
1314 [MHL_DCAP_ADOPTER_ID_L] = 0x41,
1315 [MHL_DCAP_VID_LINK_MODE] = MHL_DCAP_VID_LINK_RGB444
1316 | MHL_DCAP_VID_LINK_PPIXEL
1317 | MHL_DCAP_VID_LINK_16BPP,
1318 [MHL_DCAP_AUD_LINK_MODE] = MHL_DCAP_AUD_LINK_2CH,
1319 [MHL_DCAP_VIDEO_TYPE] = MHL_DCAP_VT_GRAPHICS,
1320 [MHL_DCAP_LOG_DEV_MAP] = MHL_DCAP_LD_GUI,
1321 [MHL_DCAP_BANDWIDTH] = 0x0f,
1322 [MHL_DCAP_FEATURE_FLAG] = MHL_DCAP_FEATURE_RCP_SUPPORT
1323 | MHL_DCAP_FEATURE_RAP_SUPPORT
1324 | MHL_DCAP_FEATURE_SP_SUPPORT,
1325 [MHL_DCAP_SCRATCHPAD_SIZE] = SII8620_SCRATCHPAD_SIZE,
1326 [MHL_DCAP_INT_STAT_SIZE] = SII8620_INT_STAT_SIZE,
1327 };
1328 static const u8 xdcap[MHL_XDC_SIZE] = {
1329 [MHL_XDC_ECBUS_SPEEDS] = MHL_XDC_ECBUS_S_075
1330 | MHL_XDC_ECBUS_S_8BIT,
1331 [MHL_XDC_TMDS_SPEEDS] = MHL_XDC_TMDS_150
1332 | MHL_XDC_TMDS_300 | MHL_XDC_TMDS_600,
1333 [MHL_XDC_ECBUS_ROLES] = MHL_XDC_DEV_HOST,
1334 [MHL_XDC_LOG_DEV_MAPX] = MHL_XDC_LD_PHONE,
1335 };
1336
1337 sii8620_write_buf(ctx, REG_MHL_DEVCAP_0, devcap, ARRAY_SIZE(devcap));
1338 sii8620_write_buf(ctx, REG_MHL_EXTDEVCAP_0, xdcap, ARRAY_SIZE(xdcap));
1339}
1340
1341static void sii8620_mhl_init(struct sii8620 *ctx)
1342{
1343 sii8620_write_seq_static(ctx,
1344 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1345 REG_CBUS_MSC_COMPAT_CTRL,
1346 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN,
1347 );
1348
1349 sii8620_peer_specific_init(ctx);
1350
1351 sii8620_disable_hpd(ctx);
1352
1353 sii8620_write_seq_static(ctx,
1354 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO,
1355 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1356 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1357 REG_TMDS0_CCTRL1, 0x90,
1358 REG_TMDS_CLK_EN, 0x01,
1359 REG_TMDS_CH_EN, 0x11,
1360 REG_BGR_BIAS, 0x87,
1361 REG_ALICE0_ZONE_CTRL, 0xE8,
1362 REG_ALICE0_MODE_CTRL, 0x04,
1363 );
1364 sii8620_setbits(ctx, REG_LM_DDC, BIT_LM_DDC_SW_TPI_EN_DISABLED, 0);
1365 sii8620_write_seq_static(ctx,
1366 REG_TPI_HW_OPT3, 0x76,
1367 REG_TMDS_CCTRL, BIT_TMDS_CCTRL_TMDS_OE,
1368 REG_TPI_DTD_B2, 79,
1369 );
1370 sii8620_set_dev_cap(ctx);
1371 sii8620_write_seq_static(ctx,
1372 REG_MDT_XMIT_TIMEOUT, 100,
1373 REG_MDT_XMIT_CTRL, 0x03,
1374 REG_MDT_XFIFO_STAT, 0x00,
1375 REG_MDT_RCV_TIMEOUT, 100,
1376 REG_CBUS_LINK_CTRL_8, 0x1D,
1377 );
1378
1379 sii8620_start_gen2_write_burst(ctx);
1380 sii8620_write_seq_static(ctx,
1381 REG_BIST_CTRL, 0x00,
1382 REG_COC_CTL1, 0x10,
1383 REG_COC_CTL2, 0x18,
1384 REG_COC_CTLF, 0x07,
1385 REG_COC_CTL11, 0xF8,
1386 REG_COC_CTL17, 0x61,
1387 REG_COC_CTL18, 0x46,
1388 REG_COC_CTL19, 0x15,
1389 REG_COC_CTL1A, 0x01,
1390 REG_MHL_COC_CTL3, BIT_MHL_COC_CTL3_COC_AECHO_EN,
1391 REG_MHL_COC_CTL4, 0x2D,
1392 REG_MHL_COC_CTL5, 0xF9,
1393 REG_MSC_HEARTBEAT_CTRL, 0x27,
1394 );
1395 sii8620_disable_gen2_write_burst(ctx);
1396
1397 sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), SII8620_MHL_VERSION);
1398 sii8620_mt_write_stat(ctx, MHL_DST_REG(CONNECTED_RDY),
1399 MHL_DST_CONN_DCAP_RDY | MHL_DST_CONN_XDEVCAPP_SUPP
1400 | MHL_DST_CONN_POW_STAT);
1401 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), MHL_INT_RC_DCAP_CHG);
1402}
1403
1404static void sii8620_emsc_enable(struct sii8620 *ctx)
1405{
1406 u8 reg;
1407
1408 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_EMSC_EN
1409 | BIT_GENCTL_CLR_EMSC_RFIFO
1410 | BIT_GENCTL_CLR_EMSC_XFIFO, ~0);
1411 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_CLR_EMSC_RFIFO
1412 | BIT_GENCTL_CLR_EMSC_XFIFO, 0);
1413 sii8620_setbits(ctx, REG_COMMECNT, BIT_COMMECNT_I2C_TO_EMSC_EN, ~0);
1414 reg = sii8620_readb(ctx, REG_EMSCINTR);
1415 sii8620_write(ctx, REG_EMSCINTR, reg);
1416 sii8620_write(ctx, REG_EMSCINTRMASK, BIT_EMSCINTR_SPI_DVLD);
1417}
1418
1419static int sii8620_wait_for_fsm_state(struct sii8620 *ctx, u8 state)
1420{
1421 int i;
1422
1423 for (i = 0; i < 10; ++i) {
1424 u8 s = sii8620_readb(ctx, REG_COC_STAT_0);
1425
1426 if ((s & MSK_COC_STAT_0_FSM_STATE) == state)
1427 return 0;
1428 if (!(s & BIT_COC_STAT_0_PLL_LOCKED))
1429 return -EBUSY;
1430 usleep_range(4000, 6000);
1431 }
1432 return -ETIMEDOUT;
1433}
1434
1435static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode)
1436{
1437 int ret;
1438
1439 if (ctx->mode == mode)
1440 return;
1441
1442 switch (mode) {
1443 case CM_MHL1:
1444 sii8620_write_seq_static(ctx,
1445 REG_CBUS_MSC_COMPAT_CTRL, 0x02,
1446 REG_M3_CTRL, VAL_M3_CTRL_MHL1_2_VALUE,
1447 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12
1448 | BIT_DPD_OSC_EN,
1449 REG_COC_INTR_MASK, 0
1450 );
1451 ctx->mode = mode;
1452 break;
1453 case CM_MHL3:
1454 sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE);
1455 ctx->mode = mode;
1456 return;
1457 case CM_ECBUS_S:
1458 sii8620_emsc_enable(ctx);
1459 sii8620_write_seq_static(ctx,
1460 REG_TTXSPINUMS, 4,
1461 REG_TRXSPINUMS, 4,
1462 REG_TTXHSICNUMS, 0x14,
1463 REG_TRXHSICNUMS, 0x14,
1464 REG_TTXTOTNUMS, 0x18,
1465 REG_TRXTOTNUMS, 0x18,
1466 REG_PWD_SRST, BIT_PWD_SRST_COC_DOC_RST
1467 | BIT_PWD_SRST_CBUS_RST_SW_EN,
1468 REG_MHL_COC_CTL1, 0xbd,
1469 REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN,
1470 REG_COC_CTLB, 0x01,
1471 REG_COC_CTL0, 0x5c,
1472 REG_COC_CTL14, 0x03,
1473 REG_COC_CTL15, 0x80,
1474 REG_MHL_DP_CTL6, BIT_MHL_DP_CTL6_DP_TAP1_SGN
1475 | BIT_MHL_DP_CTL6_DP_TAP1_EN
1476 | BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN,
1477 REG_MHL_DP_CTL8, 0x03
1478 );
1479 ret = sii8620_wait_for_fsm_state(ctx, 0x03);
1480 sii8620_write_seq_static(ctx,
1481 REG_COC_CTL14, 0x00,
1482 REG_COC_CTL15, 0x80
1483 );
1484 if (!ret)
1485 sii8620_write(ctx, REG_CBUS3_CNVT, 0x85);
1486 else
1487 sii8620_disconnect(ctx);
1488 return;
1489 case CM_DISCONNECTED:
1490 ctx->mode = mode;
1491 break;
1492 default:
1493 dev_err(ctx->dev, "%s mode %d not supported\n", __func__, mode);
1494 break;
1495 }
1496
1497 sii8620_set_auto_zone(ctx);
1498
1499 if (mode != CM_MHL1)
1500 return;
1501
1502 sii8620_write_seq_static(ctx,
1503 REG_MHL_DP_CTL0, 0xBC,
1504 REG_MHL_DP_CTL1, 0xBB,
1505 REG_MHL_DP_CTL3, 0x48,
1506 REG_MHL_DP_CTL5, 0x39,
1507 REG_MHL_DP_CTL2, 0x2A,
1508 REG_MHL_DP_CTL6, 0x2A,
1509 REG_MHL_DP_CTL7, 0x08
1510 );
1511}
1512
1513static void sii8620_hpd_unplugged(struct sii8620 *ctx)
1514{
1515 sii8620_disable_hpd(ctx);
1516 ctx->sink_type = SINK_NONE;
1517 ctx->sink_detected = false;
1518 ctx->feature_complete = false;
1519 kfree(ctx->edid);
1520 ctx->edid = NULL;
1521}
1522
1523static void sii8620_disconnect(struct sii8620 *ctx)
1524{
1525 sii8620_disable_gen2_write_burst(ctx);
1526 sii8620_stop_video(ctx);
1527 msleep(100);
1528 sii8620_cbus_reset(ctx);
1529 sii8620_set_mode(ctx, CM_DISCONNECTED);
1530 sii8620_write_seq_static(ctx,
1531 REG_TX_ZONE_CTL1, 0,
1532 REG_MHL_PLL_CTL0, 0x07,
1533 REG_COC_CTL0, 0x40,
1534 REG_CBUS3_CNVT, 0x84,
1535 REG_COC_CTL14, 0x00,
1536 REG_COC_CTL0, 0x40,
1537 REG_HRXCTRL3, 0x07,
1538 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1539 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
1540 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE,
1541 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE
1542 | BIT_MHL_DP_CTL0_TX_OE_OVR,
1543 REG_MHL_DP_CTL1, 0xBB,
1544 REG_MHL_DP_CTL3, 0x48,
1545 REG_MHL_DP_CTL5, 0x3F,
1546 REG_MHL_DP_CTL2, 0x2F,
1547 REG_MHL_DP_CTL6, 0x2A,
1548 REG_MHL_DP_CTL7, 0x03
1549 );
1550 sii8620_hpd_unplugged(ctx);
1551 sii8620_write_seq_static(ctx,
1552 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
1553 REG_MHL_COC_CTL1, 0x07,
1554 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1555 REG_DISC_CTRL8, 0x00,
1556 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1557 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1558 REG_INT_CTRL, 0x00,
1559 REG_MSC_HEARTBEAT_CTRL, 0x27,
1560 REG_DISC_CTRL1, 0x25,
1561 REG_CBUS_DISC_INTR0, (u8)~BIT_RGND_READY_INT,
1562 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT,
1563 REG_MDT_INT_1, 0xff,
1564 REG_MDT_INT_1_MASK, 0x00,
1565 REG_MDT_INT_0, 0xff,
1566 REG_MDT_INT_0_MASK, 0x00,
1567 REG_COC_INTR, 0xff,
1568 REG_COC_INTR_MASK, 0x00,
1569 REG_TRXINTH, 0xff,
1570 REG_TRXINTMH, 0x00,
1571 REG_CBUS_INT_0, 0xff,
1572 REG_CBUS_INT_0_MASK, 0x00,
1573 REG_CBUS_INT_1, 0xff,
1574 REG_CBUS_INT_1_MASK, 0x00,
1575 REG_EMSCINTR, 0xff,
1576 REG_EMSCINTRMASK, 0x00,
1577 REG_EMSCINTR1, 0xff,
1578 REG_EMSCINTRMASK1, 0x00,
1579 REG_INTR8, 0xff,
1580 REG_INTR8_MASK, 0x00,
1581 REG_TPI_INTR_ST0, 0xff,
1582 REG_TPI_INTR_EN, 0x00,
1583 REG_HDCP2X_INTR0, 0xff,
1584 REG_HDCP2X_INTR0_MASK, 0x00,
1585 REG_INTR9, 0xff,
1586 REG_INTR9_MASK, 0x00,
1587 REG_INTR3, 0xff,
1588 REG_INTR3_MASK, 0x00,
1589 REG_INTR5, 0xff,
1590 REG_INTR5_MASK, 0x00,
1591 REG_INTR2, 0xff,
1592 REG_INTR2_MASK, 0x00,
1593 );
1594 memset(ctx->stat, 0, sizeof(ctx->stat));
1595 memset(ctx->xstat, 0, sizeof(ctx->xstat));
1596 memset(ctx->devcap, 0, sizeof(ctx->devcap));
1597 memset(ctx->xdevcap, 0, sizeof(ctx->xdevcap));
1598 ctx->devcap_read = false;
1599 ctx->cbus_status = 0;
1600 sii8620_mt_cleanup(ctx);
1601}
1602
1603static void sii8620_mhl_disconnected(struct sii8620 *ctx)
1604{
1605 sii8620_write_seq_static(ctx,
1606 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1607 REG_CBUS_MSC_COMPAT_CTRL,
1608 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN
1609 );
1610 sii8620_disconnect(ctx);
1611}
1612
1613static void sii8620_irq_disc(struct sii8620 *ctx)
1614{
1615 u8 stat = sii8620_readb(ctx, REG_CBUS_DISC_INTR0);
1616
1617 if (stat & VAL_CBUS_MHL_DISCON)
1618 sii8620_mhl_disconnected(ctx);
1619
1620 if (stat & BIT_RGND_READY_INT) {
1621 u8 stat2 = sii8620_readb(ctx, REG_DISC_STAT2);
1622
1623 if ((stat2 & MSK_DISC_STAT2_RGND) == VAL_RGND_1K) {
1624 sii8620_mhl_discover(ctx);
1625 } else {
1626 sii8620_write_seq_static(ctx,
1627 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1628 | BIT_DISC_CTRL9_NOMHL_EST
1629 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1630 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT
1631 | BIT_CBUS_MHL3_DISCON_INT
1632 | BIT_CBUS_MHL12_DISCON_INT
1633 | BIT_NOT_MHL_EST_INT
1634 );
1635 }
1636 }
1637 if (stat & BIT_MHL_EST_INT)
1638 sii8620_mhl_init(ctx);
1639
1640 sii8620_write(ctx, REG_CBUS_DISC_INTR0, stat);
1641}
1642
1643static void sii8620_read_burst(struct sii8620 *ctx)
1644{
1645 u8 buf[17];
1646
1647 sii8620_read_buf(ctx, REG_MDT_RCV_READ_PORT, buf, ARRAY_SIZE(buf));
1648 sii8620_write(ctx, REG_MDT_RCV_CTRL, BIT_MDT_RCV_CTRL_MDT_RCV_EN |
1649 BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN |
1650 BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR);
1651 sii8620_readb(ctx, REG_MDT_RFIFO_STAT);
1652}
1653
1654static void sii8620_irq_g2wb(struct sii8620 *ctx)
1655{
1656 u8 stat = sii8620_readb(ctx, REG_MDT_INT_0);
1657
1658 if (stat & BIT_MDT_IDLE_AFTER_HAWB_DISABLE)
1659 if (sii8620_is_mhl3(ctx))
1660 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE),
1661 MHL_INT_RC_FEAT_COMPLETE);
1662
1663 if (stat & BIT_MDT_RFIFO_DATA_RDY)
1664 sii8620_read_burst(ctx);
1665
1666 if (stat & BIT_MDT_XFIFO_EMPTY)
1667 sii8620_write(ctx, REG_MDT_XMIT_CTRL, 0);
1668
1669 sii8620_write(ctx, REG_MDT_INT_0, stat);
1670}
1671
1672static void sii8620_status_dcap_ready(struct sii8620 *ctx)
1673{
1674 enum sii8620_mode mode;
1675
1676 mode = ctx->stat[MHL_DST_VERSION] >= 0x30 ? CM_MHL3 : CM_MHL1;
1677 if (mode > ctx->mode)
1678 sii8620_set_mode(ctx, mode);
1679 sii8620_peer_specific_init(ctx);
1680 sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE
1681 | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR);
1682}
1683
1684static void sii8620_status_changed_path(struct sii8620 *ctx)
1685{
1686 u8 link_mode;
1687
1688 if (ctx->use_packed_pixel)
1689 link_mode = MHL_DST_LM_CLK_MODE_PACKED_PIXEL;
1690 else
1691 link_mode = MHL_DST_LM_CLK_MODE_NORMAL;
1692
1693 if (ctx->stat[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED)
1694 link_mode |= MHL_DST_LM_PATH_ENABLED;
1695
1696 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
1697 link_mode);
1698}
1699
1700static void sii8620_msc_mr_write_stat(struct sii8620 *ctx)
1701{
1702 u8 st[MHL_DST_SIZE], xst[MHL_XDS_SIZE];
1703
1704 sii8620_read_buf(ctx, REG_MHL_STAT_0, st, MHL_DST_SIZE);
1705 sii8620_read_buf(ctx, REG_MHL_EXTSTAT_0, xst, MHL_XDS_SIZE);
1706
1707 sii8620_update_array(ctx->stat, st, MHL_DST_SIZE);
1708 sii8620_update_array(ctx->xstat, xst, MHL_XDS_SIZE);
1709
1710 if (ctx->stat[MHL_DST_CONNECTED_RDY] & st[MHL_DST_CONNECTED_RDY] &
1711 MHL_DST_CONN_DCAP_RDY) {
1712 sii8620_status_dcap_ready(ctx);
1713
1714 if (!sii8620_is_mhl3(ctx))
1715 sii8620_mt_read_devcap(ctx, false);
1716 }
1717
1718 if (st[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED)
1719 sii8620_status_changed_path(ctx);
1720}
1721
1722static void sii8620_ecbus_up(struct sii8620 *ctx, int ret)
1723{
1724 if (ret < 0)
1725 return;
1726
1727 sii8620_set_mode(ctx, CM_ECBUS_S);
1728}
1729
1730static void sii8620_got_ecbus_speed(struct sii8620 *ctx, int ret)
1731{
1732 if (ret < 0)
1733 return;
1734
1735 sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE),
1736 MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT);
1737 sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP);
1738 sii8620_mt_set_cont(ctx, sii8620_ecbus_up);
1739}
1740
1741static void sii8620_mhl_burst_emsc_support_set(struct mhl_burst_emsc_support *d,
1742 enum mhl_burst_id id)
1743{
1744 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_EMSC_SUPPORT);
1745 d->num_entries = 1;
1746 d->burst_id[0] = cpu_to_be16(id);
1747}
1748
1749static void sii8620_send_features(struct sii8620 *ctx)
1750{
1751 u8 buf[16];
1752
1753 sii8620_write(ctx, REG_MDT_XMIT_CTRL, BIT_MDT_XMIT_CTRL_EN
1754 | BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN);
1755 sii8620_mhl_burst_emsc_support_set((void *)buf,
1756 MHL_BURST_ID_HID_PAYLOAD);
1757 sii8620_write_buf(ctx, REG_MDT_XMIT_WRITE_PORT, buf, ARRAY_SIZE(buf));
1758}
1759
1760static bool sii8620_rcp_consume(struct sii8620 *ctx, u8 scancode)
1761{
1762 bool pressed = !(scancode & MHL_RCP_KEY_RELEASED_MASK);
1763
1764 scancode &= MHL_RCP_KEY_ID_MASK;
1765
1766 if (!ctx->rc_dev) {
1767 dev_dbg(ctx->dev, "RCP input device not initialized\n");
1768 return false;
1769 }
1770
1771 if (pressed)
1772 rc_keydown(ctx->rc_dev, RC_PROTO_CEC, scancode, 0);
1773 else
1774 rc_keyup(ctx->rc_dev);
1775
1776 return true;
1777}
1778
1779static void sii8620_msc_mr_set_int(struct sii8620 *ctx)
1780{
1781 u8 ints[MHL_INT_SIZE];
1782
1783 sii8620_read_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE);
1784 sii8620_write_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE);
1785
1786 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_DCAP_CHG) {
1787 switch (ctx->mode) {
1788 case CM_MHL3:
1789 sii8620_mt_read_xdevcap_reg(ctx, MHL_XDC_ECBUS_SPEEDS);
1790 sii8620_mt_set_cont(ctx, sii8620_got_ecbus_speed);
1791 break;
1792 case CM_ECBUS_S:
1793 sii8620_mt_read_devcap(ctx, true);
1794 break;
1795 default:
1796 break;
1797 }
1798 }
1799 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_REQ)
1800 sii8620_send_features(ctx);
1801 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_COMPLETE) {
1802 ctx->feature_complete = true;
1803 if (ctx->edid)
1804 sii8620_enable_hpd(ctx);
1805 }
1806}
1807
1808static struct sii8620_mt_msg *sii8620_msc_msg_first(struct sii8620 *ctx)
1809{
1810 struct device *dev = ctx->dev;
1811
1812 if (list_empty(&ctx->mt_queue)) {
1813 dev_err(dev, "unexpected MSC MT response\n");
1814 return NULL;
1815 }
1816
1817 return list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
1818}
1819
1820static void sii8620_msc_mt_done(struct sii8620 *ctx)
1821{
1822 struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx);
1823
1824 if (!msg)
1825 return;
1826
1827 msg->ret = sii8620_readb(ctx, REG_MSC_MT_RCVD_DATA0);
1828 ctx->mt_state = MT_STATE_DONE;
1829}
1830
1831static void sii8620_msc_mr_msc_msg(struct sii8620 *ctx)
1832{
1833 struct sii8620_mt_msg *msg;
1834 u8 buf[2];
1835
1836 sii8620_read_buf(ctx, REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA, buf, 2);
1837
1838 switch (buf[0]) {
1839 case MHL_MSC_MSG_RAPK:
1840 msg = sii8620_msc_msg_first(ctx);
1841 if (!msg)
1842 return;
1843 msg->ret = buf[1];
1844 ctx->mt_state = MT_STATE_DONE;
1845 break;
1846 case MHL_MSC_MSG_RCP:
1847 if (!sii8620_rcp_consume(ctx, buf[1]))
1848 sii8620_mt_rcpe(ctx,
1849 MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE);
1850 sii8620_mt_rcpk(ctx, buf[1]);
1851 break;
1852 default:
1853 dev_err(ctx->dev, "%s message type %d,%d not supported",
1854 __func__, buf[0], buf[1]);
1855 }
1856}
1857
1858static void sii8620_irq_msc(struct sii8620 *ctx)
1859{
1860 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_0);
1861
1862 if (stat & ~BIT_CBUS_HPD_CHG)
1863 sii8620_write(ctx, REG_CBUS_INT_0, stat & ~BIT_CBUS_HPD_CHG);
1864
1865 if (stat & BIT_CBUS_HPD_CHG) {
1866 u8 cbus_stat = sii8620_readb(ctx, REG_CBUS_STATUS);
1867
1868 if ((cbus_stat ^ ctx->cbus_status) & BIT_CBUS_STATUS_CBUS_HPD) {
1869 sii8620_write(ctx, REG_CBUS_INT_0, BIT_CBUS_HPD_CHG);
1870 } else {
1871 stat ^= BIT_CBUS_STATUS_CBUS_HPD;
1872 cbus_stat ^= BIT_CBUS_STATUS_CBUS_HPD;
1873 }
1874 ctx->cbus_status = cbus_stat;
1875 }
1876
1877 if (stat & BIT_CBUS_MSC_MR_WRITE_STAT)
1878 sii8620_msc_mr_write_stat(ctx);
1879
1880 if (stat & BIT_CBUS_HPD_CHG) {
1881 if (ctx->cbus_status & BIT_CBUS_STATUS_CBUS_HPD) {
1882 ctx->sink_detected = true;
1883 sii8620_identify_sink(ctx);
1884 } else {
1885 sii8620_hpd_unplugged(ctx);
1886 }
1887 }
1888
1889 if (stat & BIT_CBUS_MSC_MR_SET_INT)
1890 sii8620_msc_mr_set_int(ctx);
1891
1892 if (stat & BIT_CBUS_MSC_MT_DONE)
1893 sii8620_msc_mt_done(ctx);
1894
1895 if (stat & BIT_CBUS_MSC_MR_MSC_MSG)
1896 sii8620_msc_mr_msc_msg(ctx);
1897}
1898
1899static void sii8620_irq_coc(struct sii8620 *ctx)
1900{
1901 u8 stat = sii8620_readb(ctx, REG_COC_INTR);
1902
1903 if (stat & BIT_COC_CALIBRATION_DONE) {
1904 u8 cstat = sii8620_readb(ctx, REG_COC_STAT_0);
1905
1906 cstat &= BIT_COC_STAT_0_PLL_LOCKED | MSK_COC_STAT_0_FSM_STATE;
1907 if (cstat == (BIT_COC_STAT_0_PLL_LOCKED | 0x02)) {
1908 sii8620_write_seq_static(ctx,
1909 REG_COC_CTLB, 0,
1910 REG_TRXINTMH, BIT_TDM_INTR_SYNC_DATA
1911 | BIT_TDM_INTR_SYNC_WAIT
1912 );
1913 }
1914 }
1915
1916 sii8620_write(ctx, REG_COC_INTR, stat);
1917}
1918
1919static void sii8620_irq_merr(struct sii8620 *ctx)
1920{
1921 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_1);
1922
1923 sii8620_write(ctx, REG_CBUS_INT_1, stat);
1924}
1925
1926static void sii8620_irq_edid(struct sii8620 *ctx)
1927{
1928 u8 stat = sii8620_readb(ctx, REG_INTR9);
1929
1930 sii8620_write(ctx, REG_INTR9, stat);
1931
1932 if (stat & BIT_INTR9_DEVCAP_DONE)
1933 ctx->mt_state = MT_STATE_DONE;
1934}
1935
1936static void sii8620_irq_scdt(struct sii8620 *ctx)
1937{
1938 u8 stat = sii8620_readb(ctx, REG_INTR5);
1939
1940 if (stat & BIT_INTR_SCDT_CHANGE) {
1941 u8 cstat = sii8620_readb(ctx, REG_TMDS_CSTAT_P3);
1942
1943 if (cstat & BIT_TMDS_CSTAT_P3_SCDT)
1944 sii8620_start_video(ctx);
1945 }
1946
1947 sii8620_write(ctx, REG_INTR5, stat);
1948}
1949
1950static void sii8620_got_xdevcap(struct sii8620 *ctx, int ret)
1951{
1952 if (ret < 0)
1953 return;
1954
1955 sii8620_mt_read_devcap(ctx, false);
1956}
1957
1958static void sii8620_irq_tdm(struct sii8620 *ctx)
1959{
1960 u8 stat = sii8620_readb(ctx, REG_TRXINTH);
1961 u8 tdm = sii8620_readb(ctx, REG_TRXSTA2);
1962
1963 if ((tdm & MSK_TDM_SYNCHRONIZED) == VAL_TDM_SYNCHRONIZED) {
1964 ctx->mode = CM_ECBUS_S;
1965 ctx->burst.rx_ack = 0;
1966 ctx->burst.r_size = SII8620_BURST_BUF_LEN;
1967 sii8620_burst_tx_rbuf_info(ctx, SII8620_BURST_BUF_LEN);
1968 sii8620_mt_read_devcap(ctx, true);
1969 sii8620_mt_set_cont(ctx, sii8620_got_xdevcap);
1970 } else {
1971 sii8620_write_seq_static(ctx,
1972 REG_MHL_PLL_CTL2, 0,
1973 REG_MHL_PLL_CTL2, BIT_MHL_PLL_CTL2_CLKDETECT_EN
1974 );
1975 }
1976
1977 sii8620_write(ctx, REG_TRXINTH, stat);
1978}
1979
1980static void sii8620_irq_block(struct sii8620 *ctx)
1981{
1982 u8 stat = sii8620_readb(ctx, REG_EMSCINTR);
1983
1984 if (stat & BIT_EMSCINTR_SPI_DVLD) {
1985 u8 bstat = sii8620_readb(ctx, REG_SPIBURSTSTAT);
1986
1987 if (bstat & BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE)
1988 sii8620_burst_receive(ctx);
1989 }
1990
1991 sii8620_write(ctx, REG_EMSCINTR, stat);
1992}
1993
1994static void sii8620_irq_ddc(struct sii8620 *ctx)
1995{
1996 u8 stat = sii8620_readb(ctx, REG_INTR3);
1997
1998 if (stat & BIT_DDC_CMD_DONE) {
1999 sii8620_write(ctx, REG_INTR3_MASK, 0);
2000 if (sii8620_is_mhl3(ctx) && !ctx->feature_complete)
2001 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE),
2002 MHL_INT_RC_FEAT_REQ);
2003 else
2004 sii8620_enable_hpd(ctx);
2005 }
2006 sii8620_write(ctx, REG_INTR3, stat);
2007}
2008
2009
2010static bool sii8620_test_bit(unsigned int nr, const u8 *addr)
2011{
2012 return 1 & (addr[nr / BITS_PER_BYTE] >> (nr % BITS_PER_BYTE));
2013}
2014
2015static irqreturn_t sii8620_irq_thread(int irq, void *data)
2016{
2017 static const struct {
2018 int bit;
2019 void (*handler)(struct sii8620 *ctx);
2020 } irq_vec[] = {
2021 { BIT_FAST_INTR_STAT_DISC, sii8620_irq_disc },
2022 { BIT_FAST_INTR_STAT_G2WB, sii8620_irq_g2wb },
2023 { BIT_FAST_INTR_STAT_COC, sii8620_irq_coc },
2024 { BIT_FAST_INTR_STAT_TDM, sii8620_irq_tdm },
2025 { BIT_FAST_INTR_STAT_MSC, sii8620_irq_msc },
2026 { BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr },
2027 { BIT_FAST_INTR_STAT_BLOCK, sii8620_irq_block },
2028 { BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid },
2029 { BIT_FAST_INTR_STAT_DDC, sii8620_irq_ddc },
2030 { BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt },
2031 };
2032 struct sii8620 *ctx = data;
2033 u8 stats[LEN_FAST_INTR_STAT];
2034 int i, ret;
2035
2036 mutex_lock(&ctx->lock);
2037
2038 sii8620_read_buf(ctx, REG_FAST_INTR_STAT, stats, ARRAY_SIZE(stats));
2039 for (i = 0; i < ARRAY_SIZE(irq_vec); ++i)
2040 if (sii8620_test_bit(irq_vec[i].bit, stats))
2041 irq_vec[i].handler(ctx);
2042
2043 sii8620_burst_rx_all(ctx);
2044 sii8620_mt_work(ctx);
2045 sii8620_burst_send(ctx);
2046
2047 ret = sii8620_clear_error(ctx);
2048 if (ret) {
2049 dev_err(ctx->dev, "Error during IRQ handling, %d.\n", ret);
2050 sii8620_mhl_disconnected(ctx);
2051 }
2052 mutex_unlock(&ctx->lock);
2053
2054 return IRQ_HANDLED;
2055}
2056
2057static void sii8620_cable_in(struct sii8620 *ctx)
2058{
2059 struct device *dev = ctx->dev;
2060 u8 ver[5];
2061 int ret;
2062
2063 ret = sii8620_hw_on(ctx);
2064 if (ret) {
2065 dev_err(dev, "Error powering on, %d.\n", ret);
2066 return;
2067 }
2068
2069 sii8620_read_buf(ctx, REG_VND_IDL, ver, ARRAY_SIZE(ver));
2070 ret = sii8620_clear_error(ctx);
2071 if (ret) {
2072 dev_err(dev, "Error accessing I2C bus, %d.\n", ret);
2073 return;
2074 }
2075
2076 dev_info(dev, "ChipID %02x%02x:%02x%02x rev %02x.\n", ver[1], ver[0],
2077 ver[3], ver[2], ver[4]);
2078
2079 sii8620_write(ctx, REG_DPD,
2080 BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN);
2081
2082 sii8620_xtal_set_rate(ctx);
2083 sii8620_disconnect(ctx);
2084
2085 sii8620_write_seq_static(ctx,
2086 REG_MHL_CBUS_CTL0, VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG
2087 | VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734,
2088 REG_MHL_CBUS_CTL1, VAL_MHL_CBUS_CTL1_1115_OHM,
2089 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN,
2090 );
2091
2092 ret = sii8620_clear_error(ctx);
2093 if (ret) {
2094 dev_err(dev, "Error accessing I2C bus, %d.\n", ret);
2095 return;
2096 }
2097
2098 enable_irq(to_i2c_client(ctx->dev)->irq);
2099}
2100
2101static void sii8620_init_rcp_input_dev(struct sii8620 *ctx)
2102{
2103 struct rc_dev *rc_dev;
2104 int ret;
2105
2106 rc_dev = rc_allocate_device(RC_DRIVER_SCANCODE);
2107 if (!rc_dev) {
2108 dev_err(ctx->dev, "Failed to allocate RC device\n");
2109 ctx->error = -ENOMEM;
2110 return;
2111 }
2112
2113 rc_dev->input_phys = "sii8620/input0";
2114 rc_dev->input_id.bustype = BUS_VIRTUAL;
2115 rc_dev->map_name = RC_MAP_CEC;
2116 rc_dev->allowed_protocols = RC_PROTO_BIT_CEC;
2117 rc_dev->driver_name = "sii8620";
2118 rc_dev->device_name = "sii8620";
2119
2120 ret = rc_register_device(rc_dev);
2121
2122 if (ret) {
2123 dev_err(ctx->dev, "Failed to register RC device\n");
2124 ctx->error = ret;
2125 rc_free_device(ctx->rc_dev);
2126 return;
2127 }
2128 ctx->rc_dev = rc_dev;
2129}
2130
2131static void sii8620_cable_out(struct sii8620 *ctx)
2132{
2133 disable_irq(to_i2c_client(ctx->dev)->irq);
2134 sii8620_hw_off(ctx);
2135}
2136
2137static void sii8620_extcon_work(struct work_struct *work)
2138{
2139 struct sii8620 *ctx =
2140 container_of(work, struct sii8620, extcon_wq);
2141 int state = extcon_get_state(ctx->extcon, EXTCON_DISP_MHL);
2142
2143 if (state == ctx->cable_state)
2144 return;
2145
2146 ctx->cable_state = state;
2147
2148 if (state > 0)
2149 sii8620_cable_in(ctx);
2150 else
2151 sii8620_cable_out(ctx);
2152}
2153
2154static int sii8620_extcon_notifier(struct notifier_block *self,
2155 unsigned long event, void *ptr)
2156{
2157 struct sii8620 *ctx =
2158 container_of(self, struct sii8620, extcon_nb);
2159
2160 schedule_work(&ctx->extcon_wq);
2161
2162 return NOTIFY_DONE;
2163}
2164
2165static int sii8620_extcon_init(struct sii8620 *ctx)
2166{
2167 struct extcon_dev *edev;
2168 struct device_node *musb, *muic;
2169 int ret;
2170
2171
2172 musb = of_graph_get_remote_node(ctx->dev->of_node, 1, -1);
2173
2174 muic = of_get_next_parent(musb);
2175
2176 if (!muic) {
2177 dev_info(ctx->dev, "no extcon found, switching to 'always on' mode\n");
2178 return 0;
2179 }
2180
2181 edev = extcon_find_edev_by_node(muic);
2182 of_node_put(muic);
2183 if (IS_ERR(edev)) {
2184 if (PTR_ERR(edev) == -EPROBE_DEFER)
2185 return -EPROBE_DEFER;
2186 dev_err(ctx->dev, "Invalid or missing extcon\n");
2187 return PTR_ERR(edev);
2188 }
2189
2190 ctx->extcon = edev;
2191 ctx->extcon_nb.notifier_call = sii8620_extcon_notifier;
2192 INIT_WORK(&ctx->extcon_wq, sii8620_extcon_work);
2193 ret = extcon_register_notifier(edev, EXTCON_DISP_MHL, &ctx->extcon_nb);
2194 if (ret) {
2195 dev_err(ctx->dev, "failed to register notifier for MHL\n");
2196 return ret;
2197 }
2198
2199 return 0;
2200}
2201
2202static inline struct sii8620 *bridge_to_sii8620(struct drm_bridge *bridge)
2203{
2204 return container_of(bridge, struct sii8620, bridge);
2205}
2206
2207static int sii8620_attach(struct drm_bridge *bridge)
2208{
2209 struct sii8620 *ctx = bridge_to_sii8620(bridge);
2210
2211 sii8620_init_rcp_input_dev(ctx);
2212
2213 return sii8620_clear_error(ctx);
2214}
2215
2216static void sii8620_detach(struct drm_bridge *bridge)
2217{
2218 struct sii8620 *ctx = bridge_to_sii8620(bridge);
2219
2220 rc_unregister_device(ctx->rc_dev);
2221}
2222
2223static int sii8620_is_packing_required(struct sii8620 *ctx,
2224 const struct drm_display_mode *mode)
2225{
2226 int max_pclk, max_pclk_pp_mode;
2227
2228 if (sii8620_is_mhl3(ctx)) {
2229 max_pclk = MHL3_MAX_PCLK;
2230 max_pclk_pp_mode = MHL3_MAX_PCLK_PP_MODE;
2231 } else {
2232 max_pclk = MHL1_MAX_PCLK;
2233 max_pclk_pp_mode = MHL1_MAX_PCLK_PP_MODE;
2234 }
2235
2236 if (mode->clock < max_pclk)
2237 return 0;
2238 else if (mode->clock < max_pclk_pp_mode)
2239 return 1;
2240 else
2241 return -1;
2242}
2243
2244static enum drm_mode_status sii8620_mode_valid(struct drm_bridge *bridge,
2245 const struct drm_display_mode *mode)
2246{
2247 struct sii8620 *ctx = bridge_to_sii8620(bridge);
2248 int pack_required = sii8620_is_packing_required(ctx, mode);
2249 bool can_pack = ctx->devcap[MHL_DCAP_VID_LINK_MODE] &
2250 MHL_DCAP_VID_LINK_PPIXEL;
2251
2252 switch (pack_required) {
2253 case 0:
2254 return MODE_OK;
2255 case 1:
2256 return (can_pack) ? MODE_OK : MODE_CLOCK_HIGH;
2257 default:
2258 return MODE_CLOCK_HIGH;
2259 }
2260}
2261
2262static bool sii8620_mode_fixup(struct drm_bridge *bridge,
2263 const struct drm_display_mode *mode,
2264 struct drm_display_mode *adjusted_mode)
2265{
2266 struct sii8620 *ctx = bridge_to_sii8620(bridge);
2267
2268 mutex_lock(&ctx->lock);
2269
2270 ctx->use_packed_pixel = sii8620_is_packing_required(ctx, adjusted_mode);
2271
2272 mutex_unlock(&ctx->lock);
2273
2274 return true;
2275}
2276
2277static const struct drm_bridge_funcs sii8620_bridge_funcs = {
2278 .attach = sii8620_attach,
2279 .detach = sii8620_detach,
2280 .mode_fixup = sii8620_mode_fixup,
2281 .mode_valid = sii8620_mode_valid,
2282};
2283
2284static int sii8620_probe(struct i2c_client *client,
2285 const struct i2c_device_id *id)
2286{
2287 struct device *dev = &client->dev;
2288 struct sii8620 *ctx;
2289 int ret;
2290
2291 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
2292 if (!ctx)
2293 return -ENOMEM;
2294
2295 ctx->dev = dev;
2296 mutex_init(&ctx->lock);
2297 INIT_LIST_HEAD(&ctx->mt_queue);
2298
2299 ctx->clk_xtal = devm_clk_get(dev, "xtal");
2300 if (IS_ERR(ctx->clk_xtal)) {
2301 dev_err(dev, "failed to get xtal clock from DT\n");
2302 return PTR_ERR(ctx->clk_xtal);
2303 }
2304
2305 if (!client->irq) {
2306 dev_err(dev, "no irq provided\n");
2307 return -EINVAL;
2308 }
2309 irq_set_status_flags(client->irq, IRQ_NOAUTOEN);
2310 ret = devm_request_threaded_irq(dev, client->irq, NULL,
2311 sii8620_irq_thread,
2312 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
2313 "sii8620", ctx);
2314 if (ret < 0) {
2315 dev_err(dev, "failed to install IRQ handler\n");
2316 return ret;
2317 }
2318
2319 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
2320 if (IS_ERR(ctx->gpio_reset)) {
2321 dev_err(dev, "failed to get reset gpio from DT\n");
2322 return PTR_ERR(ctx->gpio_reset);
2323 }
2324
2325 ctx->supplies[0].supply = "cvcc10";
2326 ctx->supplies[1].supply = "iovcc18";
2327 ret = devm_regulator_bulk_get(dev, 2, ctx->supplies);
2328 if (ret)
2329 return ret;
2330
2331 ret = sii8620_extcon_init(ctx);
2332 if (ret < 0) {
2333 dev_err(ctx->dev, "failed to initialize EXTCON\n");
2334 return ret;
2335 }
2336
2337 i2c_set_clientdata(client, ctx);
2338
2339 ctx->bridge.funcs = &sii8620_bridge_funcs;
2340 ctx->bridge.of_node = dev->of_node;
2341 drm_bridge_add(&ctx->bridge);
2342
2343 if (!ctx->extcon)
2344 sii8620_cable_in(ctx);
2345
2346 return 0;
2347}
2348
2349static int sii8620_remove(struct i2c_client *client)
2350{
2351 struct sii8620 *ctx = i2c_get_clientdata(client);
2352
2353 if (ctx->extcon) {
2354 extcon_unregister_notifier(ctx->extcon, EXTCON_DISP_MHL,
2355 &ctx->extcon_nb);
2356 flush_work(&ctx->extcon_wq);
2357 if (ctx->cable_state > 0)
2358 sii8620_cable_out(ctx);
2359 } else {
2360 sii8620_cable_out(ctx);
2361 }
2362 drm_bridge_remove(&ctx->bridge);
2363
2364 return 0;
2365}
2366
2367static const struct of_device_id sii8620_dt_match[] = {
2368 { .compatible = "sil,sii8620" },
2369 { },
2370};
2371MODULE_DEVICE_TABLE(of, sii8620_dt_match);
2372
2373static const struct i2c_device_id sii8620_id[] = {
2374 { "sii8620", 0 },
2375 { },
2376};
2377
2378MODULE_DEVICE_TABLE(i2c, sii8620_id);
2379static struct i2c_driver sii8620_driver = {
2380 .driver = {
2381 .name = "sii8620",
2382 .of_match_table = of_match_ptr(sii8620_dt_match),
2383 },
2384 .probe = sii8620_probe,
2385 .remove = sii8620_remove,
2386 .id_table = sii8620_id,
2387};
2388
2389module_i2c_driver(sii8620_driver);
2390MODULE_LICENSE("GPL v2");
2391
