LXR linux/drivers/gpu/drm/i915/intel_guc

   1/*
   2 * Copyright © 2014-2017 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 *
  23 */
  24
  25#ifndef _INTEL_GUC_LOG_H_
  26#define _INTEL_GUC_LOG_H_
  27
  28#include <linux/mutex.h>
  29#include <linux/relay.h>
  30#include <linux/workqueue.h>
  31
  32#include "intel_guc_fwif.h"
  33#include "i915_gem.h"
  34
  35struct intel_guc;
  36
  37#ifdef CONFIG_DRM_I915_DEBUG_GUC
  38#define CRASH_BUFFER_SIZE       SZ_2M
  39#define DPC_BUFFER_SIZE         SZ_8M
  40#define ISR_BUFFER_SIZE         SZ_8M
  41#else
  42#define CRASH_BUFFER_SIZE       SZ_8K
  43#define DPC_BUFFER_SIZE         SZ_32K
  44#define ISR_BUFFER_SIZE         SZ_32K
  45#endif
  46
  47/*
  48 * While we're using plain log level in i915, GuC controls are much more...
  49 * "elaborate"? We have a couple of bits for verbosity, separate bit for actual
  50 * log enabling, and separate bit for default logging - which "conveniently"
  51 * ignores the enable bit.
  52 */
  53#define GUC_LOG_LEVEL_DISABLED          0
  54#define GUC_LOG_LEVEL_NON_VERBOSE       1
  55#define GUC_LOG_LEVEL_IS_ENABLED(x)     ((x) > GUC_LOG_LEVEL_DISABLED)
  56#define GUC_LOG_LEVEL_IS_VERBOSE(x)     ((x) > GUC_LOG_LEVEL_NON_VERBOSE)
  57#define GUC_LOG_LEVEL_TO_VERBOSITY(x) ({                \
  58        typeof(x) _x = (x);                             \
  59        GUC_LOG_LEVEL_IS_VERBOSE(_x) ? _x - 2 : 0;      \
  60})
  61#define GUC_VERBOSITY_TO_LOG_LEVEL(x)   ((x) + 2)
  62#define GUC_LOG_LEVEL_MAX GUC_VERBOSITY_TO_LOG_LEVEL(GUC_LOG_VERBOSITY_MAX)
  63
  64struct intel_guc_log {
  65        u32 level;
  66        struct i915_vma *vma;
  67        struct {
  68                void *buf_addr;
  69                struct workqueue_struct *flush_wq;
  70                struct work_struct flush_work;
  71                struct rchan *channel;
  72                struct mutex lock;
  73                u32 full_count;
  74        } relay;
  75        /* logging related stats */
  76        struct {
  77                u32 sampled_overflow;
  78                u32 overflow;
  79                u32 flush;
  80        } stats[GUC_MAX_LOG_BUFFER];
  81};
  82
  83void intel_guc_log_init_early(struct intel_guc_log *log);
  84int intel_guc_log_create(struct intel_guc_log *log);
  85void intel_guc_log_destroy(struct intel_guc_log *log);
  86
  87int intel_guc_log_set_level(struct intel_guc_log *log, u32 level);
  88bool intel_guc_log_relay_enabled(const struct intel_guc_log *log);
  89int intel_guc_log_relay_open(struct intel_guc_log *log);
  90void intel_guc_log_relay_flush(struct intel_guc_log *log);
  91void intel_guc_log_relay_close(struct intel_guc_log *log);
  92
  93void intel_guc_log_handle_flush_event(struct intel_guc_log *log);
  94
  95static inline u32 intel_guc_log_get_level(struct intel_guc_log *log)
  96{
  97        return log->level;
  98}
  99
 100#endif
 101