1
2
3
4#include <linux/reservation.h>
5#include <linux/mm_types.h>
6#include <drm/drmP.h>
7#include <drm/drm_encoder.h>
8#include <drm/drm_gem.h>
9#include <drm/gpu_scheduler.h>
10
11#define GMP_GRANULARITY (128 * 1024)
12
13
14
15
16
17enum v3d_queue {
18 V3D_BIN,
19 V3D_RENDER,
20};
21
22#define V3D_MAX_QUEUES (V3D_RENDER + 1)
23
24struct v3d_queue_state {
25 struct drm_gpu_scheduler sched;
26
27 u64 fence_context;
28 u64 emit_seqno;
29};
30
31struct v3d_dev {
32 struct drm_device drm;
33
34
35
36
37 int ver;
38
39 struct device *dev;
40 struct platform_device *pdev;
41 void __iomem *hub_regs;
42 void __iomem *core_regs[3];
43 void __iomem *bridge_regs;
44 void __iomem *gca_regs;
45 struct clk *clk;
46
47
48 volatile u32 *pt;
49 dma_addr_t pt_paddr;
50
51
52
53
54
55 void *mmu_scratch;
56 dma_addr_t mmu_scratch_paddr;
57
58
59 u32 cores;
60
61
62
63
64 struct drm_mm mm;
65 spinlock_t mm_lock;
66
67 struct work_struct overflow_mem_work;
68
69 struct v3d_exec_info *bin_job;
70 struct v3d_exec_info *render_job;
71
72 struct v3d_queue_state queue[V3D_MAX_QUEUES];
73
74
75
76
77 spinlock_t job_lock;
78
79
80 struct mutex bo_lock;
81
82
83
84
85
86 struct mutex reset_lock;
87
88
89
90
91 struct mutex sched_lock;
92
93 struct {
94 u32 num_allocated;
95 u32 pages_allocated;
96 } bo_stats;
97};
98
99static inline struct v3d_dev *
100to_v3d_dev(struct drm_device *dev)
101{
102 return (struct v3d_dev *)dev->dev_private;
103}
104
105
106struct v3d_file_priv {
107 struct v3d_dev *v3d;
108
109 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES];
110};
111
112
113struct v3d_vma {
114 struct v3d_page_table *pt;
115 struct list_head list;
116};
117
118struct v3d_bo {
119 struct drm_gem_object base;
120
121 struct mutex lock;
122
123 struct drm_mm_node node;
124
125 u32 pages_refcount;
126 struct page **pages;
127 struct sg_table *sgt;
128 void *vaddr;
129
130 struct list_head vmas;
131
132
133
134
135 struct list_head unref_head;
136
137
138 struct reservation_object *resv;
139 struct reservation_object _resv;
140};
141
142static inline struct v3d_bo *
143to_v3d_bo(struct drm_gem_object *bo)
144{
145 return (struct v3d_bo *)bo;
146}
147
148struct v3d_fence {
149 struct dma_fence base;
150 struct drm_device *dev;
151
152 u64 seqno;
153 enum v3d_queue queue;
154};
155
156static inline struct v3d_fence *
157to_v3d_fence(struct dma_fence *fence)
158{
159 return (struct v3d_fence *)fence;
160}
161
162#define V3D_READ(offset) readl(v3d->hub_regs + offset)
163#define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
164
165#define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
166#define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
167
168#define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
169#define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
170
171#define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
172#define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
173
174struct v3d_job {
175 struct drm_sched_job base;
176
177 struct v3d_exec_info *exec;
178
179
180 struct dma_fence *in_fence;
181
182
183 struct dma_fence *done_fence;
184
185
186 u32 start, end;
187
188 u32 timedout_ctca, timedout_ctra;
189};
190
191struct v3d_exec_info {
192 struct v3d_dev *v3d;
193
194 struct v3d_job bin, render;
195
196
197
198
199 struct dma_fence *bin_done_fence;
200
201 struct kref refcount;
202
203
204 struct v3d_bo **bo;
205 u32 bo_count;
206
207
208
209
210 struct list_head unref_list;
211
212
213 u32 qma, qms, qts;
214};
215
216
217
218
219
220
221
222
223
224#define wait_for(COND, MS) ({ \
225 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
226 int ret__ = 0; \
227 while (!(COND)) { \
228 if (time_after(jiffies, timeout__)) { \
229 if (!(COND)) \
230 ret__ = -ETIMEDOUT; \
231 break; \
232 } \
233 msleep(1); \
234 } \
235 ret__; \
236})
237
238static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
239{
240
241 if (NSEC_PER_SEC % HZ &&
242 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
243 return MAX_JIFFY_OFFSET;
244
245 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
246}
247
248
249void v3d_free_object(struct drm_gem_object *gem_obj);
250struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv,
251 size_t size);
252int v3d_create_bo_ioctl(struct drm_device *dev, void *data,
253 struct drm_file *file_priv);
254int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data,
255 struct drm_file *file_priv);
256int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data,
257 struct drm_file *file_priv);
258vm_fault_t v3d_gem_fault(struct vm_fault *vmf);
259int v3d_mmap(struct file *filp, struct vm_area_struct *vma);
260struct reservation_object *v3d_prime_res_obj(struct drm_gem_object *obj);
261int v3d_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
262struct sg_table *v3d_prime_get_sg_table(struct drm_gem_object *obj);
263struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev,
264 struct dma_buf_attachment *attach,
265 struct sg_table *sgt);
266
267
268int v3d_debugfs_init(struct drm_minor *minor);
269
270
271extern const struct dma_fence_ops v3d_fence_ops;
272struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
273
274
275int v3d_gem_init(struct drm_device *dev);
276void v3d_gem_destroy(struct drm_device *dev);
277int v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
278 struct drm_file *file_priv);
279int v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
280 struct drm_file *file_priv);
281void v3d_exec_put(struct v3d_exec_info *exec);
282void v3d_reset(struct v3d_dev *v3d);
283void v3d_invalidate_caches(struct v3d_dev *v3d);
284void v3d_flush_caches(struct v3d_dev *v3d);
285
286
287void v3d_irq_init(struct v3d_dev *v3d);
288void v3d_irq_enable(struct v3d_dev *v3d);
289void v3d_irq_disable(struct v3d_dev *v3d);
290void v3d_irq_reset(struct v3d_dev *v3d);
291
292
293int v3d_mmu_get_offset(struct drm_file *file_priv, struct v3d_bo *bo,
294 u32 *offset);
295int v3d_mmu_set_page_table(struct v3d_dev *v3d);
296void v3d_mmu_insert_ptes(struct v3d_bo *bo);
297void v3d_mmu_remove_ptes(struct v3d_bo *bo);
298
299
300int v3d_sched_init(struct v3d_dev *v3d);
301void v3d_sched_fini(struct v3d_dev *v3d);
302