1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18#ifndef _XILINX_DRM_H_
19#define _XILINX_DRM_H_
20
21enum xilinx_video_format {
22 XILINX_VIDEO_FORMAT_YUV422 = 0,
23 XILINX_VIDEO_FORMAT_YUV444 = 1,
24 XILINX_VIDEO_FORMAT_RGB = 2,
25 XILINX_VIDEO_FORMAT_YUV420 = 3,
26 XILINX_VIDEO_FORMAT_XRGB = 16,
27 XILINX_VIDEO_FORMAT_NONE = 32,
28};
29
30
31int xilinx_drm_format_by_code(unsigned int xilinx_format, u32 *drm_format);
32int xilinx_drm_format_by_name(const char *name, u32 *drm_format);
33
34unsigned int xilinx_drm_format_bpp(u32 drm_format);
35unsigned int xilinx_drm_format_depth(u32 drm_format);
36
37
38static inline void xilinx_drm_writel(void __iomem *base, int offset, u32 val)
39{
40 writel(val, base + offset);
41}
42
43
44static inline u32 xilinx_drm_readl(void __iomem *base, int offset)
45{
46 return readl(base + offset);
47}
48
49static inline void xilinx_drm_clr(void __iomem *base, int offset, u32 clr)
50{
51 xilinx_drm_writel(base, offset, xilinx_drm_readl(base, offset) & ~clr);
52}
53
54static inline void xilinx_drm_set(void __iomem *base, int offset, u32 set)
55{
56 xilinx_drm_writel(base, offset, xilinx_drm_readl(base, offset) | set);
57}
58
59struct drm_device;
60
61bool xilinx_drm_check_format(struct drm_device *drm, uint32_t fourcc);
62uint32_t xilinx_drm_get_format(struct drm_device *drm);
63unsigned int xilinx_drm_get_align(struct drm_device *drm);
64
65#endif
66