linux/drivers/iio/adc/aspeed_adc.c
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   1/*
   2 * Aspeed AST2400/2500 ADC
   3 *
   4 * Copyright (C) 2017 Google, Inc.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2, as published by the Free Software Foundation.
   9 *
  10 */
  11
  12#include <linux/clk.h>
  13#include <linux/clk-provider.h>
  14#include <linux/err.h>
  15#include <linux/errno.h>
  16#include <linux/io.h>
  17#include <linux/module.h>
  18#include <linux/of_platform.h>
  19#include <linux/platform_device.h>
  20#include <linux/reset.h>
  21#include <linux/spinlock.h>
  22#include <linux/types.h>
  23
  24#include <linux/iio/iio.h>
  25#include <linux/iio/driver.h>
  26#include <linux/iopoll.h>
  27
  28#define ASPEED_RESOLUTION_BITS          10
  29#define ASPEED_CLOCKS_PER_SAMPLE        12
  30
  31#define ASPEED_REG_ENGINE_CONTROL       0x00
  32#define ASPEED_REG_INTERRUPT_CONTROL    0x04
  33#define ASPEED_REG_VGA_DETECT_CONTROL   0x08
  34#define ASPEED_REG_CLOCK_CONTROL        0x0C
  35#define ASPEED_REG_MAX                  0xC0
  36
  37#define ASPEED_OPERATION_MODE_POWER_DOWN        (0x0 << 1)
  38#define ASPEED_OPERATION_MODE_STANDBY           (0x1 << 1)
  39#define ASPEED_OPERATION_MODE_NORMAL            (0x7 << 1)
  40
  41#define ASPEED_ENGINE_ENABLE            BIT(0)
  42
  43#define ASPEED_ADC_CTRL_INIT_RDY        BIT(8)
  44
  45#define ASPEED_ADC_INIT_POLLING_TIME    500
  46#define ASPEED_ADC_INIT_TIMEOUT         500000
  47
  48struct aspeed_adc_model_data {
  49        const char *model_name;
  50        unsigned int min_sampling_rate; // Hz
  51        unsigned int max_sampling_rate; // Hz
  52        unsigned int vref_voltage;      // mV
  53        bool wait_init_sequence;
  54};
  55
  56struct aspeed_adc_data {
  57        struct device           *dev;
  58        void __iomem            *base;
  59        spinlock_t              clk_lock;
  60        struct clk_hw           *clk_prescaler;
  61        struct clk_hw           *clk_scaler;
  62        struct reset_control    *rst;
  63};
  64
  65#define ASPEED_CHAN(_idx, _data_reg_addr) {                     \
  66        .type = IIO_VOLTAGE,                                    \
  67        .indexed = 1,                                           \
  68        .channel = (_idx),                                      \
  69        .address = (_data_reg_addr),                            \
  70        .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
  71        .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |  \
  72                                BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
  73}
  74
  75static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
  76        ASPEED_CHAN(0, 0x10),
  77        ASPEED_CHAN(1, 0x12),
  78        ASPEED_CHAN(2, 0x14),
  79        ASPEED_CHAN(3, 0x16),
  80        ASPEED_CHAN(4, 0x18),
  81        ASPEED_CHAN(5, 0x1A),
  82        ASPEED_CHAN(6, 0x1C),
  83        ASPEED_CHAN(7, 0x1E),
  84        ASPEED_CHAN(8, 0x20),
  85        ASPEED_CHAN(9, 0x22),
  86        ASPEED_CHAN(10, 0x24),
  87        ASPEED_CHAN(11, 0x26),
  88        ASPEED_CHAN(12, 0x28),
  89        ASPEED_CHAN(13, 0x2A),
  90        ASPEED_CHAN(14, 0x2C),
  91        ASPEED_CHAN(15, 0x2E),
  92};
  93
  94static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
  95                               struct iio_chan_spec const *chan,
  96                               int *val, int *val2, long mask)
  97{
  98        struct aspeed_adc_data *data = iio_priv(indio_dev);
  99        const struct aspeed_adc_model_data *model_data =
 100                        of_device_get_match_data(data->dev);
 101
 102        switch (mask) {
 103        case IIO_CHAN_INFO_RAW:
 104                *val = readw(data->base + chan->address);
 105                return IIO_VAL_INT;
 106
 107        case IIO_CHAN_INFO_SCALE:
 108                *val = model_data->vref_voltage;
 109                *val2 = ASPEED_RESOLUTION_BITS;
 110                return IIO_VAL_FRACTIONAL_LOG2;
 111
 112        case IIO_CHAN_INFO_SAMP_FREQ:
 113                *val = clk_get_rate(data->clk_scaler->clk) /
 114                                ASPEED_CLOCKS_PER_SAMPLE;
 115                return IIO_VAL_INT;
 116
 117        default:
 118                return -EINVAL;
 119        }
 120}
 121
 122static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
 123                                struct iio_chan_spec const *chan,
 124                                int val, int val2, long mask)
 125{
 126        struct aspeed_adc_data *data = iio_priv(indio_dev);
 127        const struct aspeed_adc_model_data *model_data =
 128                        of_device_get_match_data(data->dev);
 129
 130        switch (mask) {
 131        case IIO_CHAN_INFO_SAMP_FREQ:
 132                if (val < model_data->min_sampling_rate ||
 133                        val > model_data->max_sampling_rate)
 134                        return -EINVAL;
 135
 136                clk_set_rate(data->clk_scaler->clk,
 137                                val * ASPEED_CLOCKS_PER_SAMPLE);
 138                return 0;
 139
 140        case IIO_CHAN_INFO_SCALE:
 141        case IIO_CHAN_INFO_RAW:
 142                /*
 143                 * Technically, these could be written but the only reasons
 144                 * for doing so seem better handled in userspace.  EPERM is
 145                 * returned to signal this is a policy choice rather than a
 146                 * hardware limitation.
 147                 */
 148                return -EPERM;
 149
 150        default:
 151                return -EINVAL;
 152        }
 153}
 154
 155static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
 156                                 unsigned int reg, unsigned int writeval,
 157                                 unsigned int *readval)
 158{
 159        struct aspeed_adc_data *data = iio_priv(indio_dev);
 160
 161        if (!readval || reg % 4 || reg > ASPEED_REG_MAX)
 162                return -EINVAL;
 163
 164        *readval = readl(data->base + reg);
 165
 166        return 0;
 167}
 168
 169static const struct iio_info aspeed_adc_iio_info = {
 170        .read_raw = aspeed_adc_read_raw,
 171        .write_raw = aspeed_adc_write_raw,
 172        .debugfs_reg_access = aspeed_adc_reg_access,
 173};
 174
 175static int aspeed_adc_probe(struct platform_device *pdev)
 176{
 177        struct iio_dev *indio_dev;
 178        struct aspeed_adc_data *data;
 179        const struct aspeed_adc_model_data *model_data;
 180        struct resource *res;
 181        const char *clk_parent_name;
 182        int ret;
 183        u32 adc_engine_control_reg_val;
 184
 185        indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
 186        if (!indio_dev)
 187                return -ENOMEM;
 188
 189        data = iio_priv(indio_dev);
 190        data->dev = &pdev->dev;
 191
 192        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 193        data->base = devm_ioremap_resource(&pdev->dev, res);
 194        if (IS_ERR(data->base))
 195                return PTR_ERR(data->base);
 196
 197        /* Register ADC clock prescaler with source specified by device tree. */
 198        spin_lock_init(&data->clk_lock);
 199        clk_parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
 200
 201        data->clk_prescaler = clk_hw_register_divider(
 202                                &pdev->dev, "prescaler", clk_parent_name, 0,
 203                                data->base + ASPEED_REG_CLOCK_CONTROL,
 204                                17, 15, 0, &data->clk_lock);
 205        if (IS_ERR(data->clk_prescaler))
 206                return PTR_ERR(data->clk_prescaler);
 207
 208        /*
 209         * Register ADC clock scaler downstream from the prescaler. Allow rate
 210         * setting to adjust the prescaler as well.
 211         */
 212        data->clk_scaler = clk_hw_register_divider(
 213                                &pdev->dev, "scaler", "prescaler",
 214                                CLK_SET_RATE_PARENT,
 215                                data->base + ASPEED_REG_CLOCK_CONTROL,
 216                                0, 10, 0, &data->clk_lock);
 217        if (IS_ERR(data->clk_scaler)) {
 218                ret = PTR_ERR(data->clk_scaler);
 219                goto scaler_error;
 220        }
 221
 222        data->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 223        if (IS_ERR(data->rst)) {
 224                dev_err(&pdev->dev,
 225                        "invalid or missing reset controller device tree entry");
 226                ret = PTR_ERR(data->rst);
 227                goto reset_error;
 228        }
 229        reset_control_deassert(data->rst);
 230
 231        model_data = of_device_get_match_data(&pdev->dev);
 232
 233        if (model_data->wait_init_sequence) {
 234                /* Enable engine in normal mode. */
 235                writel(ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE,
 236                       data->base + ASPEED_REG_ENGINE_CONTROL);
 237
 238                /* Wait for initial sequence complete. */
 239                ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL,
 240                                         adc_engine_control_reg_val,
 241                                         adc_engine_control_reg_val &
 242                                         ASPEED_ADC_CTRL_INIT_RDY,
 243                                         ASPEED_ADC_INIT_POLLING_TIME,
 244                                         ASPEED_ADC_INIT_TIMEOUT);
 245                if (ret)
 246                        goto poll_timeout_error;
 247        }
 248
 249        /* Start all channels in normal mode. */
 250        ret = clk_prepare_enable(data->clk_scaler->clk);
 251        if (ret)
 252                goto clk_enable_error;
 253
 254        adc_engine_control_reg_val = GENMASK(31, 16) |
 255                ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE;
 256        writel(adc_engine_control_reg_val,
 257                data->base + ASPEED_REG_ENGINE_CONTROL);
 258
 259        model_data = of_device_get_match_data(&pdev->dev);
 260        indio_dev->name = model_data->model_name;
 261        indio_dev->dev.parent = &pdev->dev;
 262        indio_dev->info = &aspeed_adc_iio_info;
 263        indio_dev->modes = INDIO_DIRECT_MODE;
 264        indio_dev->channels = aspeed_adc_iio_channels;
 265        indio_dev->num_channels = ARRAY_SIZE(aspeed_adc_iio_channels);
 266
 267        ret = iio_device_register(indio_dev);
 268        if (ret)
 269                goto iio_register_error;
 270
 271        return 0;
 272
 273iio_register_error:
 274        writel(ASPEED_OPERATION_MODE_POWER_DOWN,
 275                data->base + ASPEED_REG_ENGINE_CONTROL);
 276        clk_disable_unprepare(data->clk_scaler->clk);
 277clk_enable_error:
 278poll_timeout_error:
 279        reset_control_assert(data->rst);
 280reset_error:
 281        clk_hw_unregister_divider(data->clk_scaler);
 282scaler_error:
 283        clk_hw_unregister_divider(data->clk_prescaler);
 284        return ret;
 285}
 286
 287static int aspeed_adc_remove(struct platform_device *pdev)
 288{
 289        struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 290        struct aspeed_adc_data *data = iio_priv(indio_dev);
 291
 292        iio_device_unregister(indio_dev);
 293        writel(ASPEED_OPERATION_MODE_POWER_DOWN,
 294                data->base + ASPEED_REG_ENGINE_CONTROL);
 295        clk_disable_unprepare(data->clk_scaler->clk);
 296        reset_control_assert(data->rst);
 297        clk_hw_unregister_divider(data->clk_scaler);
 298        clk_hw_unregister_divider(data->clk_prescaler);
 299
 300        return 0;
 301}
 302
 303static const struct aspeed_adc_model_data ast2400_model_data = {
 304        .model_name = "ast2400-adc",
 305        .vref_voltage = 2500, // mV
 306        .min_sampling_rate = 10000,
 307        .max_sampling_rate = 500000,
 308};
 309
 310static const struct aspeed_adc_model_data ast2500_model_data = {
 311        .model_name = "ast2500-adc",
 312        .vref_voltage = 1800, // mV
 313        .min_sampling_rate = 1,
 314        .max_sampling_rate = 1000000,
 315        .wait_init_sequence = true,
 316};
 317
 318static const struct of_device_id aspeed_adc_matches[] = {
 319        { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data },
 320        { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data },
 321        {},
 322};
 323MODULE_DEVICE_TABLE(of, aspeed_adc_matches);
 324
 325static struct platform_driver aspeed_adc_driver = {
 326        .probe = aspeed_adc_probe,
 327        .remove = aspeed_adc_remove,
 328        .driver = {
 329                .name = KBUILD_MODNAME,
 330                .of_match_table = aspeed_adc_matches,
 331        }
 332};
 333
 334module_platform_driver(aspeed_adc_driver);
 335
 336MODULE_AUTHOR("Rick Altherr <raltherr@google.com>");
 337MODULE_DESCRIPTION("Aspeed AST2400/2500 ADC Driver");
 338MODULE_LICENSE("GPL");
 339