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10#include <linux/slab.h>
11#include <linux/module.h>
12#include <linux/interrupt.h>
13#include <linux/mtd/mtd.h>
14#include <linux/mtd/rawnand.h>
15#include <linux/mtd/partitions.h>
16#include <linux/platform_device.h>
17#include <asm/io.h>
18#include <asm/mach-au1x00/au1000.h>
19#include <asm/mach-au1x00/au1550nd.h>
20
21
22struct au1550nd_ctx {
23 struct nand_chip chip;
24
25 int cs;
26 void __iomem *base;
27 void (*write_byte)(struct mtd_info *, u_char);
28};
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34
35
36static u_char au_read_byte(struct mtd_info *mtd)
37{
38 struct nand_chip *this = mtd_to_nand(mtd);
39 u_char ret = readb(this->IO_ADDR_R);
40 wmb();
41 return ret;
42}
43
44
45
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47
48
49
50
51static void au_write_byte(struct mtd_info *mtd, u_char byte)
52{
53 struct nand_chip *this = mtd_to_nand(mtd);
54 writeb(byte, this->IO_ADDR_W);
55 wmb();
56}
57
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63
64static u_char au_read_byte16(struct mtd_info *mtd)
65{
66 struct nand_chip *this = mtd_to_nand(mtd);
67 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
68 wmb();
69 return ret;
70}
71
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78
79static void au_write_byte16(struct mtd_info *mtd, u_char byte)
80{
81 struct nand_chip *this = mtd_to_nand(mtd);
82 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
83 wmb();
84}
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90
91
92static u16 au_read_word(struct mtd_info *mtd)
93{
94 struct nand_chip *this = mtd_to_nand(mtd);
95 u16 ret = readw(this->IO_ADDR_R);
96 wmb();
97 return ret;
98}
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107
108static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
109{
110 int i;
111 struct nand_chip *this = mtd_to_nand(mtd);
112
113 for (i = 0; i < len; i++) {
114 writeb(buf[i], this->IO_ADDR_W);
115 wmb();
116 }
117}
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125
126
127static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
128{
129 int i;
130 struct nand_chip *this = mtd_to_nand(mtd);
131
132 for (i = 0; i < len; i++) {
133 buf[i] = readb(this->IO_ADDR_R);
134 wmb();
135 }
136}
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144
145
146static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
147{
148 int i;
149 struct nand_chip *this = mtd_to_nand(mtd);
150 u16 *p = (u16 *) buf;
151 len >>= 1;
152
153 for (i = 0; i < len; i++) {
154 writew(p[i], this->IO_ADDR_W);
155 wmb();
156 }
157
158}
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166
167
168static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
169{
170 int i;
171 struct nand_chip *this = mtd_to_nand(mtd);
172 u16 *p = (u16 *) buf;
173 len >>= 1;
174
175 for (i = 0; i < len; i++) {
176 p[i] = readw(this->IO_ADDR_R);
177 wmb();
178 }
179}
180
181
182#define NAND_CTL_SETNCE 1
183
184#define NAND_CTL_CLRNCE 2
185
186#define NAND_CTL_SETCLE 3
187
188#define NAND_CTL_CLRCLE 4
189
190#define NAND_CTL_SETALE 5
191
192#define NAND_CTL_CLRALE 6
193
194static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
195{
196 struct nand_chip *this = mtd_to_nand(mtd);
197 struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
198 chip);
199
200 switch (cmd) {
201
202 case NAND_CTL_SETCLE:
203 this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
204 break;
205
206 case NAND_CTL_CLRCLE:
207 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
208 break;
209
210 case NAND_CTL_SETALE:
211 this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
212 break;
213
214 case NAND_CTL_CLRALE:
215 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
216
217
218 udelay(1);
219 break;
220
221 case NAND_CTL_SETNCE:
222
223 alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
224 break;
225
226 case NAND_CTL_CLRNCE:
227
228 alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
229 break;
230 }
231
232 this->IO_ADDR_R = this->IO_ADDR_W;
233
234 wmb();
235}
236
237int au1550_device_ready(struct mtd_info *mtd)
238{
239 return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0;
240}
241
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253
254static void au1550_select_chip(struct mtd_info *mtd, int chip)
255{
256}
257
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264
265static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
266{
267 struct nand_chip *this = mtd_to_nand(mtd);
268 struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
269 chip);
270 int ce_override = 0, i;
271 unsigned long flags = 0;
272
273
274 au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
275
276
277
278 if (command == NAND_CMD_SEQIN) {
279 int readcmd;
280
281 if (column >= mtd->writesize) {
282
283 column -= mtd->writesize;
284 readcmd = NAND_CMD_READOOB;
285 } else if (column < 256) {
286
287 readcmd = NAND_CMD_READ0;
288 } else {
289 column -= 256;
290 readcmd = NAND_CMD_READ1;
291 }
292 ctx->write_byte(mtd, readcmd);
293 }
294 ctx->write_byte(mtd, command);
295
296
297 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
298
299 if (column != -1 || page_addr != -1) {
300 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
301
302
303 if (column != -1) {
304
305 if (this->options & NAND_BUSWIDTH_16 &&
306 !nand_opcode_8bits(command))
307 column >>= 1;
308 ctx->write_byte(mtd, column);
309 }
310 if (page_addr != -1) {
311 ctx->write_byte(mtd, (u8)(page_addr & 0xff));
312
313 if (command == NAND_CMD_READ0 ||
314 command == NAND_CMD_READ1 ||
315 command == NAND_CMD_READOOB) {
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323
324 ce_override = 1;
325 local_irq_save(flags);
326 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
327 }
328
329 ctx->write_byte(mtd, (u8)(page_addr >> 8));
330
331 if (this->options & NAND_ROW_ADDR_3)
332 ctx->write_byte(mtd,
333 ((page_addr >> 16) & 0x0f));
334 }
335
336 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
337 }
338
339
340
341
342
343 switch (command) {
344
345 case NAND_CMD_PAGEPROG:
346 case NAND_CMD_ERASE1:
347 case NAND_CMD_ERASE2:
348 case NAND_CMD_SEQIN:
349 case NAND_CMD_STATUS:
350 return;
351
352 case NAND_CMD_RESET:
353 break;
354
355 case NAND_CMD_READ0:
356 case NAND_CMD_READ1:
357 case NAND_CMD_READOOB:
358
359 if (unlikely(!ce_override))
360 break;
361
362
363 ndelay(100);
364
365 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
366 udelay(1);
367
368
369 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
370 local_irq_restore(flags);
371 return;
372 }
373
374 ndelay(100);
375
376 while(!this->dev_ready(mtd));
377}
378
379static int find_nand_cs(unsigned long nand_base)
380{
381 void __iomem *base =
382 (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
383 unsigned long addr, staddr, start, mask, end;
384 int i;
385
386 for (i = 0; i < 4; i++) {
387 addr = 0x1000 + (i * 0x10);
388 staddr = __raw_readl(base + addr + 0x08);
389
390 start = (staddr << 4) & 0xfffc0000;
391 mask = (staddr << 18) & 0xfffc0000;
392 end = (start | (start - 1)) & ~(start ^ mask);
393 if ((nand_base >= start) && (nand_base < end))
394 return i;
395 }
396
397 return -ENODEV;
398}
399
400static int au1550nd_probe(struct platform_device *pdev)
401{
402 struct au1550nd_platdata *pd;
403 struct au1550nd_ctx *ctx;
404 struct nand_chip *this;
405 struct mtd_info *mtd;
406 struct resource *r;
407 int ret, cs;
408
409 pd = dev_get_platdata(&pdev->dev);
410 if (!pd) {
411 dev_err(&pdev->dev, "missing platform data\n");
412 return -ENODEV;
413 }
414
415 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
416 if (!ctx)
417 return -ENOMEM;
418
419 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
420 if (!r) {
421 dev_err(&pdev->dev, "no NAND memory resource\n");
422 ret = -ENODEV;
423 goto out1;
424 }
425 if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
426 dev_err(&pdev->dev, "cannot claim NAND memory area\n");
427 ret = -ENOMEM;
428 goto out1;
429 }
430
431 ctx->base = ioremap_nocache(r->start, 0x1000);
432 if (!ctx->base) {
433 dev_err(&pdev->dev, "cannot remap NAND memory area\n");
434 ret = -ENODEV;
435 goto out2;
436 }
437
438 this = &ctx->chip;
439 mtd = nand_to_mtd(this);
440 mtd->dev.parent = &pdev->dev;
441
442
443 cs = find_nand_cs(r->start);
444 if (cs < 0) {
445 dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
446 ret = -ENODEV;
447 goto out3;
448 }
449 ctx->cs = cs;
450
451 this->dev_ready = au1550_device_ready;
452 this->select_chip = au1550_select_chip;
453 this->cmdfunc = au1550_command;
454
455
456 this->chip_delay = 30;
457 this->ecc.mode = NAND_ECC_SOFT;
458 this->ecc.algo = NAND_ECC_HAMMING;
459
460 if (pd->devwidth)
461 this->options |= NAND_BUSWIDTH_16;
462
463 this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
464 ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
465 this->read_word = au_read_word;
466 this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
467 this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
468
469 ret = nand_scan(mtd, 1);
470 if (ret) {
471 dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
472 goto out3;
473 }
474
475 mtd_device_register(mtd, pd->parts, pd->num_parts);
476
477 platform_set_drvdata(pdev, ctx);
478
479 return 0;
480
481out3:
482 iounmap(ctx->base);
483out2:
484 release_mem_region(r->start, resource_size(r));
485out1:
486 kfree(ctx);
487 return ret;
488}
489
490static int au1550nd_remove(struct platform_device *pdev)
491{
492 struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
493 struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
494
495 nand_release(nand_to_mtd(&ctx->chip));
496 iounmap(ctx->base);
497 release_mem_region(r->start, 0x1000);
498 kfree(ctx);
499 return 0;
500}
501
502static struct platform_driver au1550nd_driver = {
503 .driver = {
504 .name = "au1550-nand",
505 },
506 .probe = au1550nd_probe,
507 .remove = au1550nd_remove,
508};
509
510module_platform_driver(au1550nd_driver);
511
512MODULE_LICENSE("GPL");
513MODULE_AUTHOR("Embedded Edge, LLC");
514MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");
515