LXR linux/drivers/net/ethernet/altera/altera

   1/* Altera TSE SGDMA and MSGDMA Linux driver
   2 * Copyright (C) 2014 Altera Corporation. All rights reserved
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms and conditions of the GNU General Public License,
   6 * version 2, as published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope it will be useful, but WITHOUT
   9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11 * more details.
  12 *
  13 * You should have received a copy of the GNU General Public License along with
  14 * this program.  If not, see <http://www.gnu.org/licenses/>.
  15 */
  16
  17#ifndef __ALTERA_MSGDMAHW_H__
  18#define __ALTERA_MSGDMAHW_H__
  19
  20/* mSGDMA extended descriptor format
  21 */
  22struct msgdma_extended_desc {
  23        u32 read_addr_lo;       /* data buffer source address low bits */
  24        u32 write_addr_lo;      /* data buffer destination address low bits */
  25        u32 len;                /* the number of bytes to transfer
  26                                 * per descriptor
  27                                 */
  28        u32 burst_seq_num;      /* bit 31:24 write burst
  29                                 * bit 23:16 read burst
  30                                 * bit 15:0  sequence number
  31                                 */
  32        u32 stride;             /* bit 31:16 write stride
  33                                 * bit 15:0  read stride
  34                                 */
  35        u32 read_addr_hi;       /* data buffer source address high bits */
  36        u32 write_addr_hi;      /* data buffer destination address high bits */
  37        u32 control;            /* characteristics of the transfer */
  38};
  39
  40/* mSGDMA descriptor control field bit definitions
  41 */
  42#define MSGDMA_DESC_CTL_SET_CH(x)       ((x) & 0xff)
  43#define MSGDMA_DESC_CTL_GEN_SOP         BIT(8)
  44#define MSGDMA_DESC_CTL_GEN_EOP         BIT(9)
  45#define MSGDMA_DESC_CTL_PARK_READS      BIT(10)
  46#define MSGDMA_DESC_CTL_PARK_WRITES     BIT(11)
  47#define MSGDMA_DESC_CTL_END_ON_EOP      BIT(12)
  48#define MSGDMA_DESC_CTL_END_ON_LEN      BIT(13)
  49#define MSGDMA_DESC_CTL_TR_COMP_IRQ     BIT(14)
  50#define MSGDMA_DESC_CTL_EARLY_IRQ       BIT(15)
  51#define MSGDMA_DESC_CTL_TR_ERR_IRQ      (0xff << 16)
  52#define MSGDMA_DESC_CTL_EARLY_DONE      BIT(24)
  53/* Writing ‘1’ to the ‘go’ bit commits the entire descriptor into the
  54 * descriptor FIFO(s)
  55 */
  56#define MSGDMA_DESC_CTL_GO              BIT(31)
  57
  58/* Tx buffer control flags
  59 */
  60#define MSGDMA_DESC_CTL_TX_FIRST        (MSGDMA_DESC_CTL_GEN_SOP |      \
  61                                         MSGDMA_DESC_CTL_GO)
  62
  63#define MSGDMA_DESC_CTL_TX_MIDDLE       (MSGDMA_DESC_CTL_GO)
  64
  65#define MSGDMA_DESC_CTL_TX_LAST         (MSGDMA_DESC_CTL_GEN_EOP |      \
  66                                         MSGDMA_DESC_CTL_TR_COMP_IRQ |  \
  67                                         MSGDMA_DESC_CTL_GO)
  68
  69#define MSGDMA_DESC_CTL_TX_SINGLE       (MSGDMA_DESC_CTL_GEN_SOP |      \
  70                                         MSGDMA_DESC_CTL_GEN_EOP |      \
  71                                         MSGDMA_DESC_CTL_TR_COMP_IRQ |  \
  72                                         MSGDMA_DESC_CTL_GO)
  73
  74#define MSGDMA_DESC_CTL_RX_SINGLE       (MSGDMA_DESC_CTL_END_ON_EOP |   \
  75                                         MSGDMA_DESC_CTL_END_ON_LEN |   \
  76                                         MSGDMA_DESC_CTL_TR_COMP_IRQ |  \
  77                                         MSGDMA_DESC_CTL_EARLY_IRQ |    \
  78                                         MSGDMA_DESC_CTL_TR_ERR_IRQ |   \
  79                                         MSGDMA_DESC_CTL_GO)
  80
  81/* mSGDMA extended descriptor stride definitions
  82 */
  83#define MSGDMA_DESC_TX_STRIDE           (0x00010001)
  84#define MSGDMA_DESC_RX_STRIDE           (0x00010001)
  85
  86/* mSGDMA dispatcher control and status register map
  87 */
  88struct msgdma_csr {
  89        u32 status;             /* Read/Clear */
  90        u32 control;            /* Read/Write */
  91        u32 rw_fill_level;      /* bit 31:16 - write fill level
  92                                 * bit 15:0  - read fill level
  93                                 */
  94        u32 resp_fill_level;    /* bit 15:0 */
  95        u32 rw_seq_num;         /* bit 31:16 - write sequence number
  96                                 * bit 15:0  - read sequence number
  97                                 */
  98        u32 pad[3];             /* reserved */
  99};
 100
 101/* mSGDMA CSR status register bit definitions
 102 */
 103#define MSGDMA_CSR_STAT_BUSY                    BIT(0)
 104#define MSGDMA_CSR_STAT_DESC_BUF_EMPTY          BIT(1)
 105#define MSGDMA_CSR_STAT_DESC_BUF_FULL           BIT(2)
 106#define MSGDMA_CSR_STAT_RESP_BUF_EMPTY          BIT(3)
 107#define MSGDMA_CSR_STAT_RESP_BUF_FULL           BIT(4)
 108#define MSGDMA_CSR_STAT_STOPPED                 BIT(5)
 109#define MSGDMA_CSR_STAT_RESETTING               BIT(6)
 110#define MSGDMA_CSR_STAT_STOPPED_ON_ERR          BIT(7)
 111#define MSGDMA_CSR_STAT_STOPPED_ON_EARLY        BIT(8)
 112#define MSGDMA_CSR_STAT_IRQ                     BIT(9)
 113#define MSGDMA_CSR_STAT_MASK                    0x3FF
 114#define MSGDMA_CSR_STAT_MASK_WITHOUT_IRQ        0x1FF
 115
 116#define MSGDMA_CSR_STAT_BUSY_GET(v)                     GET_BIT_VALUE(v, 0)
 117#define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v)           GET_BIT_VALUE(v, 1)
 118#define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v)            GET_BIT_VALUE(v, 2)
 119#define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v)           GET_BIT_VALUE(v, 3)
 120#define MSGDMA_CSR_STAT_RESP_BUF_FULL_GET(v)            GET_BIT_VALUE(v, 4)
 121#define MSGDMA_CSR_STAT_STOPPED_GET(v)                  GET_BIT_VALUE(v, 5)
 122#define MSGDMA_CSR_STAT_RESETTING_GET(v)                GET_BIT_VALUE(v, 6)
 123#define MSGDMA_CSR_STAT_STOPPED_ON_ERR_GET(v)           GET_BIT_VALUE(v, 7)
 124#define MSGDMA_CSR_STAT_STOPPED_ON_EARLY_GET(v)         GET_BIT_VALUE(v, 8)
 125#define MSGDMA_CSR_STAT_IRQ_GET(v)                      GET_BIT_VALUE(v, 9)
 126
 127/* mSGDMA CSR control register bit definitions
 128 */
 129#define MSGDMA_CSR_CTL_STOP                     BIT(0)
 130#define MSGDMA_CSR_CTL_RESET                    BIT(1)
 131#define MSGDMA_CSR_CTL_STOP_ON_ERR              BIT(2)
 132#define MSGDMA_CSR_CTL_STOP_ON_EARLY            BIT(3)
 133#define MSGDMA_CSR_CTL_GLOBAL_INTR              BIT(4)
 134#define MSGDMA_CSR_CTL_STOP_DESCS               BIT(5)
 135
 136/* mSGDMA CSR fill level bits
 137 */
 138#define MSGDMA_CSR_WR_FILL_LEVEL_GET(v)         (((v) & 0xffff0000) >> 16)
 139#define MSGDMA_CSR_RD_FILL_LEVEL_GET(v)         ((v) & 0x0000ffff)
 140#define MSGDMA_CSR_RESP_FILL_LEVEL_GET(v)       ((v) & 0x0000ffff)
 141
 142/* mSGDMA response register map
 143 */
 144struct msgdma_response {
 145        u32 bytes_transferred;
 146        u32 status;
 147};
 148
 149#define msgdma_respoffs(a) (offsetof(struct msgdma_response, a))
 150#define msgdma_csroffs(a) (offsetof(struct msgdma_csr, a))
 151#define msgdma_descroffs(a) (offsetof(struct msgdma_extended_desc, a))
 152
 153/* mSGDMA response register bit definitions
 154 */
 155#define MSGDMA_RESP_EARLY_TERM  BIT(8)
 156#define MSGDMA_RESP_ERR_MASK    0xFF
 157
 158#endif /* __ALTERA_MSGDMA_H__*/
 159