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33#include "ena_com.h"
34
35
36
37
38
39#define ADMIN_CMD_TIMEOUT_US (3000000)
40
41#define ENA_ASYNC_QUEUE_DEPTH 16
42#define ENA_ADMIN_QUEUE_DEPTH 32
43
44#define MIN_ENA_VER (((ENA_COMMON_SPEC_VERSION_MAJOR) << \
45 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) \
46 | (ENA_COMMON_SPEC_VERSION_MINOR))
47
48#define ENA_CTRL_MAJOR 0
49#define ENA_CTRL_MINOR 0
50#define ENA_CTRL_SUB_MINOR 1
51
52#define MIN_ENA_CTRL_VER \
53 (((ENA_CTRL_MAJOR) << \
54 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
55 ((ENA_CTRL_MINOR) << \
56 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
57 (ENA_CTRL_SUB_MINOR))
58
59#define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x)))
60#define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32))
61
62#define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
63
64#define ENA_REGS_ADMIN_INTR_MASK 1
65
66#define ENA_POLL_MS 5
67
68
69
70
71
72enum ena_cmd_status {
73 ENA_CMD_SUBMITTED,
74 ENA_CMD_COMPLETED,
75
76 ENA_CMD_ABORTED,
77};
78
79struct ena_comp_ctx {
80 struct completion wait_event;
81 struct ena_admin_acq_entry *user_cqe;
82 u32 comp_size;
83 enum ena_cmd_status status;
84
85 u8 comp_status;
86 u8 cmd_opcode;
87 bool occupied;
88};
89
90struct ena_com_stats_ctx {
91 struct ena_admin_aq_get_stats_cmd get_cmd;
92 struct ena_admin_acq_get_stats_resp get_resp;
93};
94
95static inline int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
96 struct ena_common_mem_addr *ena_addr,
97 dma_addr_t addr)
98{
99 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
100 pr_err("dma address has more bits that the device supports\n");
101 return -EINVAL;
102 }
103
104 ena_addr->mem_addr_low = lower_32_bits(addr);
105 ena_addr->mem_addr_high = (u16)upper_32_bits(addr);
106
107 return 0;
108}
109
110static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
111{
112 struct ena_com_admin_sq *sq = &queue->sq;
113 u16 size = ADMIN_SQ_SIZE(queue->q_depth);
114
115 sq->entries = dma_zalloc_coherent(queue->q_dmadev, size, &sq->dma_addr,
116 GFP_KERNEL);
117
118 if (!sq->entries) {
119 pr_err("memory allocation failed");
120 return -ENOMEM;
121 }
122
123 sq->head = 0;
124 sq->tail = 0;
125 sq->phase = 1;
126
127 sq->db_addr = NULL;
128
129 return 0;
130}
131
132static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
133{
134 struct ena_com_admin_cq *cq = &queue->cq;
135 u16 size = ADMIN_CQ_SIZE(queue->q_depth);
136
137 cq->entries = dma_zalloc_coherent(queue->q_dmadev, size, &cq->dma_addr,
138 GFP_KERNEL);
139
140 if (!cq->entries) {
141 pr_err("memory allocation failed");
142 return -ENOMEM;
143 }
144
145 cq->head = 0;
146 cq->phase = 1;
147
148 return 0;
149}
150
151static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
152 struct ena_aenq_handlers *aenq_handlers)
153{
154 struct ena_com_aenq *aenq = &dev->aenq;
155 u32 addr_low, addr_high, aenq_caps;
156 u16 size;
157
158 dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
159 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
160 aenq->entries = dma_zalloc_coherent(dev->dmadev, size, &aenq->dma_addr,
161 GFP_KERNEL);
162
163 if (!aenq->entries) {
164 pr_err("memory allocation failed");
165 return -ENOMEM;
166 }
167
168 aenq->head = aenq->q_depth;
169 aenq->phase = 1;
170
171 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
172 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
173
174 writel(addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
175 writel(addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
176
177 aenq_caps = 0;
178 aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
179 aenq_caps |= (sizeof(struct ena_admin_aenq_entry)
180 << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
181 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
182 writel(aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
183
184 if (unlikely(!aenq_handlers)) {
185 pr_err("aenq handlers pointer is NULL\n");
186 return -EINVAL;
187 }
188
189 aenq->aenq_handlers = aenq_handlers;
190
191 return 0;
192}
193
194static inline void comp_ctxt_release(struct ena_com_admin_queue *queue,
195 struct ena_comp_ctx *comp_ctx)
196{
197 comp_ctx->occupied = false;
198 atomic_dec(&queue->outstanding_cmds);
199}
200
201static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
202 u16 command_id, bool capture)
203{
204 if (unlikely(command_id >= queue->q_depth)) {
205 pr_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
206 command_id, queue->q_depth);
207 return NULL;
208 }
209
210 if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
211 pr_err("Completion context is occupied\n");
212 return NULL;
213 }
214
215 if (capture) {
216 atomic_inc(&queue->outstanding_cmds);
217 queue->comp_ctx[command_id].occupied = true;
218 }
219
220 return &queue->comp_ctx[command_id];
221}
222
223static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
224 struct ena_admin_aq_entry *cmd,
225 size_t cmd_size_in_bytes,
226 struct ena_admin_acq_entry *comp,
227 size_t comp_size_in_bytes)
228{
229 struct ena_comp_ctx *comp_ctx;
230 u16 tail_masked, cmd_id;
231 u16 queue_size_mask;
232 u16 cnt;
233
234 queue_size_mask = admin_queue->q_depth - 1;
235
236 tail_masked = admin_queue->sq.tail & queue_size_mask;
237
238
239 cnt = atomic_read(&admin_queue->outstanding_cmds);
240 if (cnt >= admin_queue->q_depth) {
241 pr_debug("admin queue is full.\n");
242 admin_queue->stats.out_of_space++;
243 return ERR_PTR(-ENOSPC);
244 }
245
246 cmd_id = admin_queue->curr_cmd_id;
247
248 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
249 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
250
251 cmd->aq_common_descriptor.command_id |= cmd_id &
252 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
253
254 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
255 if (unlikely(!comp_ctx))
256 return ERR_PTR(-EINVAL);
257
258 comp_ctx->status = ENA_CMD_SUBMITTED;
259 comp_ctx->comp_size = (u32)comp_size_in_bytes;
260 comp_ctx->user_cqe = comp;
261 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
262
263 reinit_completion(&comp_ctx->wait_event);
264
265 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
266
267 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
268 queue_size_mask;
269
270 admin_queue->sq.tail++;
271 admin_queue->stats.submitted_cmd++;
272
273 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
274 admin_queue->sq.phase = !admin_queue->sq.phase;
275
276 writel(admin_queue->sq.tail, admin_queue->sq.db_addr);
277
278 return comp_ctx;
279}
280
281static inline int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
282{
283 size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
284 struct ena_comp_ctx *comp_ctx;
285 u16 i;
286
287 queue->comp_ctx = devm_kzalloc(queue->q_dmadev, size, GFP_KERNEL);
288 if (unlikely(!queue->comp_ctx)) {
289 pr_err("memory allocation failed");
290 return -ENOMEM;
291 }
292
293 for (i = 0; i < queue->q_depth; i++) {
294 comp_ctx = get_comp_ctxt(queue, i, false);
295 if (comp_ctx)
296 init_completion(&comp_ctx->wait_event);
297 }
298
299 return 0;
300}
301
302static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
303 struct ena_admin_aq_entry *cmd,
304 size_t cmd_size_in_bytes,
305 struct ena_admin_acq_entry *comp,
306 size_t comp_size_in_bytes)
307{
308 unsigned long flags;
309 struct ena_comp_ctx *comp_ctx;
310
311 spin_lock_irqsave(&admin_queue->q_lock, flags);
312 if (unlikely(!admin_queue->running_state)) {
313 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
314 return ERR_PTR(-ENODEV);
315 }
316 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
317 cmd_size_in_bytes,
318 comp,
319 comp_size_in_bytes);
320 if (IS_ERR(comp_ctx))
321 admin_queue->running_state = false;
322 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
323
324 return comp_ctx;
325}
326
327static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
328 struct ena_com_create_io_ctx *ctx,
329 struct ena_com_io_sq *io_sq)
330{
331 size_t size;
332 int dev_node = 0;
333
334 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
335
336 io_sq->dma_addr_bits = ena_dev->dma_addr_bits;
337 io_sq->desc_entry_size =
338 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
339 sizeof(struct ena_eth_io_tx_desc) :
340 sizeof(struct ena_eth_io_rx_desc);
341
342 size = io_sq->desc_entry_size * io_sq->q_depth;
343
344 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
345 dev_node = dev_to_node(ena_dev->dmadev);
346 set_dev_node(ena_dev->dmadev, ctx->numa_node);
347 io_sq->desc_addr.virt_addr =
348 dma_zalloc_coherent(ena_dev->dmadev, size,
349 &io_sq->desc_addr.phys_addr,
350 GFP_KERNEL);
351 set_dev_node(ena_dev->dmadev, dev_node);
352 if (!io_sq->desc_addr.virt_addr) {
353 io_sq->desc_addr.virt_addr =
354 dma_zalloc_coherent(ena_dev->dmadev, size,
355 &io_sq->desc_addr.phys_addr,
356 GFP_KERNEL);
357 }
358 } else {
359 dev_node = dev_to_node(ena_dev->dmadev);
360 set_dev_node(ena_dev->dmadev, ctx->numa_node);
361 io_sq->desc_addr.virt_addr =
362 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
363 set_dev_node(ena_dev->dmadev, dev_node);
364 if (!io_sq->desc_addr.virt_addr) {
365 io_sq->desc_addr.virt_addr =
366 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
367 }
368 }
369
370 if (!io_sq->desc_addr.virt_addr) {
371 pr_err("memory allocation failed");
372 return -ENOMEM;
373 }
374
375 io_sq->tail = 0;
376 io_sq->next_to_comp = 0;
377 io_sq->phase = 1;
378
379 return 0;
380}
381
382static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
383 struct ena_com_create_io_ctx *ctx,
384 struct ena_com_io_cq *io_cq)
385{
386 size_t size;
387 int prev_node = 0;
388
389 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
390
391
392 io_cq->cdesc_entry_size_in_bytes =
393 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
394 sizeof(struct ena_eth_io_tx_cdesc) :
395 sizeof(struct ena_eth_io_rx_cdesc_base);
396
397 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
398
399 prev_node = dev_to_node(ena_dev->dmadev);
400 set_dev_node(ena_dev->dmadev, ctx->numa_node);
401 io_cq->cdesc_addr.virt_addr =
402 dma_zalloc_coherent(ena_dev->dmadev, size,
403 &io_cq->cdesc_addr.phys_addr, GFP_KERNEL);
404 set_dev_node(ena_dev->dmadev, prev_node);
405 if (!io_cq->cdesc_addr.virt_addr) {
406 io_cq->cdesc_addr.virt_addr =
407 dma_zalloc_coherent(ena_dev->dmadev, size,
408 &io_cq->cdesc_addr.phys_addr,
409 GFP_KERNEL);
410 }
411
412 if (!io_cq->cdesc_addr.virt_addr) {
413 pr_err("memory allocation failed");
414 return -ENOMEM;
415 }
416
417 io_cq->phase = 1;
418 io_cq->head = 0;
419
420 return 0;
421}
422
423static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
424 struct ena_admin_acq_entry *cqe)
425{
426 struct ena_comp_ctx *comp_ctx;
427 u16 cmd_id;
428
429 cmd_id = cqe->acq_common_descriptor.command &
430 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
431
432 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
433 if (unlikely(!comp_ctx)) {
434 pr_err("comp_ctx is NULL. Changing the admin queue running state\n");
435 admin_queue->running_state = false;
436 return;
437 }
438
439 comp_ctx->status = ENA_CMD_COMPLETED;
440 comp_ctx->comp_status = cqe->acq_common_descriptor.status;
441
442 if (comp_ctx->user_cqe)
443 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
444
445 if (!admin_queue->polling)
446 complete(&comp_ctx->wait_event);
447}
448
449static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
450{
451 struct ena_admin_acq_entry *cqe = NULL;
452 u16 comp_num = 0;
453 u16 head_masked;
454 u8 phase;
455
456 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
457 phase = admin_queue->cq.phase;
458
459 cqe = &admin_queue->cq.entries[head_masked];
460
461
462 while ((READ_ONCE(cqe->acq_common_descriptor.flags) &
463 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
464
465
466
467 dma_rmb();
468 ena_com_handle_single_admin_completion(admin_queue, cqe);
469
470 head_masked++;
471 comp_num++;
472 if (unlikely(head_masked == admin_queue->q_depth)) {
473 head_masked = 0;
474 phase = !phase;
475 }
476
477 cqe = &admin_queue->cq.entries[head_masked];
478 }
479
480 admin_queue->cq.head += comp_num;
481 admin_queue->cq.phase = phase;
482 admin_queue->sq.head += comp_num;
483 admin_queue->stats.completed_cmd += comp_num;
484}
485
486static int ena_com_comp_status_to_errno(u8 comp_status)
487{
488 if (unlikely(comp_status != 0))
489 pr_err("admin command failed[%u]\n", comp_status);
490
491 if (unlikely(comp_status > ENA_ADMIN_UNKNOWN_ERROR))
492 return -EINVAL;
493
494 switch (comp_status) {
495 case ENA_ADMIN_SUCCESS:
496 return 0;
497 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
498 return -ENOMEM;
499 case ENA_ADMIN_UNSUPPORTED_OPCODE:
500 return -EOPNOTSUPP;
501 case ENA_ADMIN_BAD_OPCODE:
502 case ENA_ADMIN_MALFORMED_REQUEST:
503 case ENA_ADMIN_ILLEGAL_PARAMETER:
504 case ENA_ADMIN_UNKNOWN_ERROR:
505 return -EINVAL;
506 }
507
508 return 0;
509}
510
511static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
512 struct ena_com_admin_queue *admin_queue)
513{
514 unsigned long flags, timeout;
515 int ret;
516
517 timeout = jiffies + usecs_to_jiffies(admin_queue->completion_timeout);
518
519 while (1) {
520 spin_lock_irqsave(&admin_queue->q_lock, flags);
521 ena_com_handle_admin_completion(admin_queue);
522 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
523
524 if (comp_ctx->status != ENA_CMD_SUBMITTED)
525 break;
526
527 if (time_is_before_jiffies(timeout)) {
528 pr_err("Wait for completion (polling) timeout\n");
529
530 spin_lock_irqsave(&admin_queue->q_lock, flags);
531 admin_queue->stats.no_completion++;
532 admin_queue->running_state = false;
533 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
534
535 ret = -ETIME;
536 goto err;
537 }
538
539 msleep(ENA_POLL_MS);
540 }
541
542 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
543 pr_err("Command was aborted\n");
544 spin_lock_irqsave(&admin_queue->q_lock, flags);
545 admin_queue->stats.aborted_cmd++;
546 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
547 ret = -ENODEV;
548 goto err;
549 }
550
551 WARN(comp_ctx->status != ENA_CMD_COMPLETED, "Invalid comp status %d\n",
552 comp_ctx->status);
553
554 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
555err:
556 comp_ctxt_release(admin_queue, comp_ctx);
557 return ret;
558}
559
560static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
561 struct ena_com_admin_queue *admin_queue)
562{
563 unsigned long flags;
564 int ret;
565
566 wait_for_completion_timeout(&comp_ctx->wait_event,
567 usecs_to_jiffies(
568 admin_queue->completion_timeout));
569
570
571
572
573
574
575 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
576 spin_lock_irqsave(&admin_queue->q_lock, flags);
577 ena_com_handle_admin_completion(admin_queue);
578 admin_queue->stats.no_completion++;
579 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
580
581 if (comp_ctx->status == ENA_CMD_COMPLETED)
582 pr_err("The ena device have completion but the driver didn't receive any MSI-X interrupt (cmd %d)\n",
583 comp_ctx->cmd_opcode);
584 else
585 pr_err("The ena device doesn't send any completion for the admin cmd %d status %d\n",
586 comp_ctx->cmd_opcode, comp_ctx->status);
587
588 admin_queue->running_state = false;
589 ret = -ETIME;
590 goto err;
591 }
592
593 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
594err:
595 comp_ctxt_release(admin_queue, comp_ctx);
596 return ret;
597}
598
599
600
601
602
603static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
604{
605 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
606 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
607 mmio_read->read_resp;
608 u32 mmio_read_reg, ret, i;
609 unsigned long flags;
610 u32 timeout = mmio_read->reg_read_to;
611
612 might_sleep();
613
614 if (timeout == 0)
615 timeout = ENA_REG_READ_TIMEOUT;
616
617
618 if (!mmio_read->readless_supported)
619 return readl(ena_dev->reg_bar + offset);
620
621 spin_lock_irqsave(&mmio_read->lock, flags);
622 mmio_read->seq_num++;
623
624 read_resp->req_id = mmio_read->seq_num + 0xDEAD;
625 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
626 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
627 mmio_read_reg |= mmio_read->seq_num &
628 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
629
630 writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
631
632 for (i = 0; i < timeout; i++) {
633 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num)
634 break;
635
636 udelay(1);
637 }
638
639 if (unlikely(i == timeout)) {
640 pr_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
641 mmio_read->seq_num, offset, read_resp->req_id,
642 read_resp->reg_off);
643 ret = ENA_MMIO_READ_TIMEOUT;
644 goto err;
645 }
646
647 if (read_resp->reg_off != offset) {
648 pr_err("Read failure: wrong offset provided");
649 ret = ENA_MMIO_READ_TIMEOUT;
650 } else {
651 ret = read_resp->reg_val;
652 }
653err:
654 spin_unlock_irqrestore(&mmio_read->lock, flags);
655
656 return ret;
657}
658
659
660
661
662
663
664
665
666static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
667 struct ena_com_admin_queue *admin_queue)
668{
669 if (admin_queue->polling)
670 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
671 admin_queue);
672
673 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
674 admin_queue);
675}
676
677static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
678 struct ena_com_io_sq *io_sq)
679{
680 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
681 struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
682 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
683 u8 direction;
684 int ret;
685
686 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
687
688 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
689 direction = ENA_ADMIN_SQ_DIRECTION_TX;
690 else
691 direction = ENA_ADMIN_SQ_DIRECTION_RX;
692
693 destroy_cmd.sq.sq_identity |= (direction <<
694 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
695 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
696
697 destroy_cmd.sq.sq_idx = io_sq->idx;
698 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
699
700 ret = ena_com_execute_admin_command(admin_queue,
701 (struct ena_admin_aq_entry *)&destroy_cmd,
702 sizeof(destroy_cmd),
703 (struct ena_admin_acq_entry *)&destroy_resp,
704 sizeof(destroy_resp));
705
706 if (unlikely(ret && (ret != -ENODEV)))
707 pr_err("failed to destroy io sq error: %d\n", ret);
708
709 return ret;
710}
711
712static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
713 struct ena_com_io_sq *io_sq,
714 struct ena_com_io_cq *io_cq)
715{
716 size_t size;
717
718 if (io_cq->cdesc_addr.virt_addr) {
719 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
720
721 dma_free_coherent(ena_dev->dmadev, size,
722 io_cq->cdesc_addr.virt_addr,
723 io_cq->cdesc_addr.phys_addr);
724
725 io_cq->cdesc_addr.virt_addr = NULL;
726 }
727
728 if (io_sq->desc_addr.virt_addr) {
729 size = io_sq->desc_entry_size * io_sq->q_depth;
730
731 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
732 dma_free_coherent(ena_dev->dmadev, size,
733 io_sq->desc_addr.virt_addr,
734 io_sq->desc_addr.phys_addr);
735 else
736 devm_kfree(ena_dev->dmadev, io_sq->desc_addr.virt_addr);
737
738 io_sq->desc_addr.virt_addr = NULL;
739 }
740}
741
742static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
743 u16 exp_state)
744{
745 u32 val, i;
746
747
748 timeout = (timeout * 100) / ENA_POLL_MS;
749
750 for (i = 0; i < timeout; i++) {
751 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
752
753 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
754 pr_err("Reg read timeout occurred\n");
755 return -ETIME;
756 }
757
758 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
759 exp_state)
760 return 0;
761
762 msleep(ENA_POLL_MS);
763 }
764
765 return -ETIME;
766}
767
768static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
769 enum ena_admin_aq_feature_id feature_id)
770{
771 u32 feature_mask = 1 << feature_id;
772
773
774 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
775 !(ena_dev->supported_features & feature_mask))
776 return false;
777
778 return true;
779}
780
781static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
782 struct ena_admin_get_feat_resp *get_resp,
783 enum ena_admin_aq_feature_id feature_id,
784 dma_addr_t control_buf_dma_addr,
785 u32 control_buff_size)
786{
787 struct ena_com_admin_queue *admin_queue;
788 struct ena_admin_get_feat_cmd get_cmd;
789 int ret;
790
791 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
792 pr_debug("Feature %d isn't supported\n", feature_id);
793 return -EOPNOTSUPP;
794 }
795
796 memset(&get_cmd, 0x0, sizeof(get_cmd));
797 admin_queue = &ena_dev->admin_queue;
798
799 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
800
801 if (control_buff_size)
802 get_cmd.aq_common_descriptor.flags =
803 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
804 else
805 get_cmd.aq_common_descriptor.flags = 0;
806
807 ret = ena_com_mem_addr_set(ena_dev,
808 &get_cmd.control_buffer.address,
809 control_buf_dma_addr);
810 if (unlikely(ret)) {
811 pr_err("memory address set failed\n");
812 return ret;
813 }
814
815 get_cmd.control_buffer.length = control_buff_size;
816
817 get_cmd.feat_common.feature_id = feature_id;
818
819 ret = ena_com_execute_admin_command(admin_queue,
820 (struct ena_admin_aq_entry *)
821 &get_cmd,
822 sizeof(get_cmd),
823 (struct ena_admin_acq_entry *)
824 get_resp,
825 sizeof(*get_resp));
826
827 if (unlikely(ret))
828 pr_err("Failed to submit get_feature command %d error: %d\n",
829 feature_id, ret);
830
831 return ret;
832}
833
834static int ena_com_get_feature(struct ena_com_dev *ena_dev,
835 struct ena_admin_get_feat_resp *get_resp,
836 enum ena_admin_aq_feature_id feature_id)
837{
838 return ena_com_get_feature_ex(ena_dev,
839 get_resp,
840 feature_id,
841 0,
842 0);
843}
844
845static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
846{
847 struct ena_rss *rss = &ena_dev->rss;
848
849 rss->hash_key =
850 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key),
851 &rss->hash_key_dma_addr, GFP_KERNEL);
852
853 if (unlikely(!rss->hash_key))
854 return -ENOMEM;
855
856 return 0;
857}
858
859static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
860{
861 struct ena_rss *rss = &ena_dev->rss;
862
863 if (rss->hash_key)
864 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key),
865 rss->hash_key, rss->hash_key_dma_addr);
866 rss->hash_key = NULL;
867}
868
869static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
870{
871 struct ena_rss *rss = &ena_dev->rss;
872
873 rss->hash_ctrl =
874 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl),
875 &rss->hash_ctrl_dma_addr, GFP_KERNEL);
876
877 if (unlikely(!rss->hash_ctrl))
878 return -ENOMEM;
879
880 return 0;
881}
882
883static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
884{
885 struct ena_rss *rss = &ena_dev->rss;
886
887 if (rss->hash_ctrl)
888 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl),
889 rss->hash_ctrl, rss->hash_ctrl_dma_addr);
890 rss->hash_ctrl = NULL;
891}
892
893static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
894 u16 log_size)
895{
896 struct ena_rss *rss = &ena_dev->rss;
897 struct ena_admin_get_feat_resp get_resp;
898 size_t tbl_size;
899 int ret;
900
901 ret = ena_com_get_feature(ena_dev, &get_resp,
902 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
903 if (unlikely(ret))
904 return ret;
905
906 if ((get_resp.u.ind_table.min_size > log_size) ||
907 (get_resp.u.ind_table.max_size < log_size)) {
908 pr_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
909 1 << log_size, 1 << get_resp.u.ind_table.min_size,
910 1 << get_resp.u.ind_table.max_size);
911 return -EINVAL;
912 }
913
914 tbl_size = (1ULL << log_size) *
915 sizeof(struct ena_admin_rss_ind_table_entry);
916
917 rss->rss_ind_tbl =
918 dma_zalloc_coherent(ena_dev->dmadev, tbl_size,
919 &rss->rss_ind_tbl_dma_addr, GFP_KERNEL);
920 if (unlikely(!rss->rss_ind_tbl))
921 goto mem_err1;
922
923 tbl_size = (1ULL << log_size) * sizeof(u16);
924 rss->host_rss_ind_tbl =
925 devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL);
926 if (unlikely(!rss->host_rss_ind_tbl))
927 goto mem_err2;
928
929 rss->tbl_log_size = log_size;
930
931 return 0;
932
933mem_err2:
934 tbl_size = (1ULL << log_size) *
935 sizeof(struct ena_admin_rss_ind_table_entry);
936
937 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl,
938 rss->rss_ind_tbl_dma_addr);
939 rss->rss_ind_tbl = NULL;
940mem_err1:
941 rss->tbl_log_size = 0;
942 return -ENOMEM;
943}
944
945static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
946{
947 struct ena_rss *rss = &ena_dev->rss;
948 size_t tbl_size = (1ULL << rss->tbl_log_size) *
949 sizeof(struct ena_admin_rss_ind_table_entry);
950
951 if (rss->rss_ind_tbl)
952 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl,
953 rss->rss_ind_tbl_dma_addr);
954 rss->rss_ind_tbl = NULL;
955
956 if (rss->host_rss_ind_tbl)
957 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl);
958 rss->host_rss_ind_tbl = NULL;
959}
960
961static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
962 struct ena_com_io_sq *io_sq, u16 cq_idx)
963{
964 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
965 struct ena_admin_aq_create_sq_cmd create_cmd;
966 struct ena_admin_acq_create_sq_resp_desc cmd_completion;
967 u8 direction;
968 int ret;
969
970 memset(&create_cmd, 0x0, sizeof(create_cmd));
971
972 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
973
974 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
975 direction = ENA_ADMIN_SQ_DIRECTION_TX;
976 else
977 direction = ENA_ADMIN_SQ_DIRECTION_RX;
978
979 create_cmd.sq_identity |= (direction <<
980 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
981 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
982
983 create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
984 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
985
986 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
987 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
988 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
989
990 create_cmd.sq_caps_3 |=
991 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
992
993 create_cmd.cq_idx = cq_idx;
994 create_cmd.sq_depth = io_sq->q_depth;
995
996 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
997 ret = ena_com_mem_addr_set(ena_dev,
998 &create_cmd.sq_ba,
999 io_sq->desc_addr.phys_addr);
1000 if (unlikely(ret)) {
1001 pr_err("memory address set failed\n");
1002 return ret;
1003 }
1004 }
1005
1006 ret = ena_com_execute_admin_command(admin_queue,
1007 (struct ena_admin_aq_entry *)&create_cmd,
1008 sizeof(create_cmd),
1009 (struct ena_admin_acq_entry *)&cmd_completion,
1010 sizeof(cmd_completion));
1011 if (unlikely(ret)) {
1012 pr_err("Failed to create IO SQ. error: %d\n", ret);
1013 return ret;
1014 }
1015
1016 io_sq->idx = cmd_completion.sq_idx;
1017
1018 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1019 (uintptr_t)cmd_completion.sq_doorbell_offset);
1020
1021 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1022 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1023 + cmd_completion.llq_headers_offset);
1024
1025 io_sq->desc_addr.pbuf_dev_addr =
1026 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1027 cmd_completion.llq_descriptors_offset);
1028 }
1029
1030 pr_debug("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1031
1032 return ret;
1033}
1034
1035static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1036{
1037 struct ena_rss *rss = &ena_dev->rss;
1038 struct ena_com_io_sq *io_sq;
1039 u16 qid;
1040 int i;
1041
1042 for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1043 qid = rss->host_rss_ind_tbl[i];
1044 if (qid >= ENA_TOTAL_NUM_QUEUES)
1045 return -EINVAL;
1046
1047 io_sq = &ena_dev->io_sq_queues[qid];
1048
1049 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1050 return -EINVAL;
1051
1052 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1053 }
1054
1055 return 0;
1056}
1057
1058static int ena_com_ind_tbl_convert_from_device(struct ena_com_dev *ena_dev)
1059{
1060 u16 dev_idx_to_host_tbl[ENA_TOTAL_NUM_QUEUES] = { (u16)-1 };
1061 struct ena_rss *rss = &ena_dev->rss;
1062 u8 idx;
1063 u16 i;
1064
1065 for (i = 0; i < ENA_TOTAL_NUM_QUEUES; i++)
1066 dev_idx_to_host_tbl[ena_dev->io_sq_queues[i].idx] = i;
1067
1068 for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1069 if (rss->rss_ind_tbl[i].cq_idx > ENA_TOTAL_NUM_QUEUES)
1070 return -EINVAL;
1071 idx = (u8)rss->rss_ind_tbl[i].cq_idx;
1072
1073 if (dev_idx_to_host_tbl[idx] > ENA_TOTAL_NUM_QUEUES)
1074 return -EINVAL;
1075
1076 rss->host_rss_ind_tbl[i] = dev_idx_to_host_tbl[idx];
1077 }
1078
1079 return 0;
1080}
1081
1082static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev)
1083{
1084 size_t size;
1085
1086 size = sizeof(struct ena_intr_moder_entry) * ENA_INTR_MAX_NUM_OF_LEVELS;
1087
1088 ena_dev->intr_moder_tbl =
1089 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
1090 if (!ena_dev->intr_moder_tbl)
1091 return -ENOMEM;
1092
1093 ena_com_config_default_interrupt_moderation_table(ena_dev);
1094
1095 return 0;
1096}
1097
1098static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1099 u16 intr_delay_resolution)
1100{
1101 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
1102 unsigned int i;
1103
1104 if (!intr_delay_resolution) {
1105 pr_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1106 intr_delay_resolution = 1;
1107 }
1108 ena_dev->intr_delay_resolution = intr_delay_resolution;
1109
1110
1111 for (i = 0; i < ENA_INTR_MAX_NUM_OF_LEVELS; i++)
1112 intr_moder_tbl[i].intr_moder_interval /= intr_delay_resolution;
1113
1114
1115 ena_dev->intr_moder_tx_interval /= intr_delay_resolution;
1116}
1117
1118
1119
1120
1121
1122int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1123 struct ena_admin_aq_entry *cmd,
1124 size_t cmd_size,
1125 struct ena_admin_acq_entry *comp,
1126 size_t comp_size)
1127{
1128 struct ena_comp_ctx *comp_ctx;
1129 int ret;
1130
1131 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1132 comp, comp_size);
1133 if (IS_ERR(comp_ctx)) {
1134 if (comp_ctx == ERR_PTR(-ENODEV))
1135 pr_debug("Failed to submit command [%ld]\n",
1136 PTR_ERR(comp_ctx));
1137 else
1138 pr_err("Failed to submit command [%ld]\n",
1139 PTR_ERR(comp_ctx));
1140
1141 return PTR_ERR(comp_ctx);
1142 }
1143
1144 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1145 if (unlikely(ret)) {
1146 if (admin_queue->running_state)
1147 pr_err("Failed to process command. ret = %d\n", ret);
1148 else
1149 pr_debug("Failed to process command. ret = %d\n", ret);
1150 }
1151 return ret;
1152}
1153
1154int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1155 struct ena_com_io_cq *io_cq)
1156{
1157 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1158 struct ena_admin_aq_create_cq_cmd create_cmd;
1159 struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1160 int ret;
1161
1162 memset(&create_cmd, 0x0, sizeof(create_cmd));
1163
1164 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1165
1166 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1167 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1168 create_cmd.cq_caps_1 |=
1169 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1170
1171 create_cmd.msix_vector = io_cq->msix_vector;
1172 create_cmd.cq_depth = io_cq->q_depth;
1173
1174 ret = ena_com_mem_addr_set(ena_dev,
1175 &create_cmd.cq_ba,
1176 io_cq->cdesc_addr.phys_addr);
1177 if (unlikely(ret)) {
1178 pr_err("memory address set failed\n");
1179 return ret;
1180 }
1181
1182 ret = ena_com_execute_admin_command(admin_queue,
1183 (struct ena_admin_aq_entry *)&create_cmd,
1184 sizeof(create_cmd),
1185 (struct ena_admin_acq_entry *)&cmd_completion,
1186 sizeof(cmd_completion));
1187 if (unlikely(ret)) {
1188 pr_err("Failed to create IO CQ. error: %d\n", ret);
1189 return ret;
1190 }
1191
1192 io_cq->idx = cmd_completion.cq_idx;
1193
1194 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1195 cmd_completion.cq_interrupt_unmask_register_offset);
1196
1197 if (cmd_completion.cq_head_db_register_offset)
1198 io_cq->cq_head_db_reg =
1199 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1200 cmd_completion.cq_head_db_register_offset);
1201
1202 if (cmd_completion.numa_node_register_offset)
1203 io_cq->numa_node_cfg_reg =
1204 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1205 cmd_completion.numa_node_register_offset);
1206
1207 pr_debug("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1208
1209 return ret;
1210}
1211
1212int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1213 struct ena_com_io_sq **io_sq,
1214 struct ena_com_io_cq **io_cq)
1215{
1216 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1217 pr_err("Invalid queue number %d but the max is %d\n", qid,
1218 ENA_TOTAL_NUM_QUEUES);
1219 return -EINVAL;
1220 }
1221
1222 *io_sq = &ena_dev->io_sq_queues[qid];
1223 *io_cq = &ena_dev->io_cq_queues[qid];
1224
1225 return 0;
1226}
1227
1228void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1229{
1230 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1231 struct ena_comp_ctx *comp_ctx;
1232 u16 i;
1233
1234 if (!admin_queue->comp_ctx)
1235 return;
1236
1237 for (i = 0; i < admin_queue->q_depth; i++) {
1238 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1239 if (unlikely(!comp_ctx))
1240 break;
1241
1242 comp_ctx->status = ENA_CMD_ABORTED;
1243
1244 complete(&comp_ctx->wait_event);
1245 }
1246}
1247
1248void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1249{
1250 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1251 unsigned long flags;
1252
1253 spin_lock_irqsave(&admin_queue->q_lock, flags);
1254 while (atomic_read(&admin_queue->outstanding_cmds) != 0) {
1255 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1256 msleep(ENA_POLL_MS);
1257 spin_lock_irqsave(&admin_queue->q_lock, flags);
1258 }
1259 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1260}
1261
1262int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1263 struct ena_com_io_cq *io_cq)
1264{
1265 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1266 struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1267 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1268 int ret;
1269
1270 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1271
1272 destroy_cmd.cq_idx = io_cq->idx;
1273 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1274
1275 ret = ena_com_execute_admin_command(admin_queue,
1276 (struct ena_admin_aq_entry *)&destroy_cmd,
1277 sizeof(destroy_cmd),
1278 (struct ena_admin_acq_entry *)&destroy_resp,
1279 sizeof(destroy_resp));
1280
1281 if (unlikely(ret && (ret != -ENODEV)))
1282 pr_err("Failed to destroy IO CQ. error: %d\n", ret);
1283
1284 return ret;
1285}
1286
1287bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1288{
1289 return ena_dev->admin_queue.running_state;
1290}
1291
1292void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1293{
1294 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1295 unsigned long flags;
1296
1297 spin_lock_irqsave(&admin_queue->q_lock, flags);
1298 ena_dev->admin_queue.running_state = state;
1299 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1300}
1301
1302void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1303{
1304 u16 depth = ena_dev->aenq.q_depth;
1305
1306 WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1307
1308
1309
1310
1311 writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1312}
1313
1314int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1315{
1316 struct ena_com_admin_queue *admin_queue;
1317 struct ena_admin_set_feat_cmd cmd;
1318 struct ena_admin_set_feat_resp resp;
1319 struct ena_admin_get_feat_resp get_resp;
1320 int ret;
1321
1322 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG);
1323 if (ret) {
1324 pr_info("Can't get aenq configuration\n");
1325 return ret;
1326 }
1327
1328 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1329 pr_warn("Trying to set unsupported aenq events. supported flag: %x asked flag: %x\n",
1330 get_resp.u.aenq.supported_groups, groups_flag);
1331 return -EOPNOTSUPP;
1332 }
1333
1334 memset(&cmd, 0x0, sizeof(cmd));
1335 admin_queue = &ena_dev->admin_queue;
1336
1337 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1338 cmd.aq_common_descriptor.flags = 0;
1339 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1340 cmd.u.aenq.enabled_groups = groups_flag;
1341
1342 ret = ena_com_execute_admin_command(admin_queue,
1343 (struct ena_admin_aq_entry *)&cmd,
1344 sizeof(cmd),
1345 (struct ena_admin_acq_entry *)&resp,
1346 sizeof(resp));
1347
1348 if (unlikely(ret))
1349 pr_err("Failed to config AENQ ret: %d\n", ret);
1350
1351 return ret;
1352}
1353
1354int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1355{
1356 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1357 int width;
1358
1359 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1360 pr_err("Reg read timeout occurred\n");
1361 return -ETIME;
1362 }
1363
1364 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1365 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1366
1367 pr_debug("ENA dma width: %d\n", width);
1368
1369 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1370 pr_err("DMA width illegal value: %d\n", width);
1371 return -EINVAL;
1372 }
1373
1374 ena_dev->dma_addr_bits = width;
1375
1376 return width;
1377}
1378
1379int ena_com_validate_version(struct ena_com_dev *ena_dev)
1380{
1381 u32 ver;
1382 u32 ctrl_ver;
1383 u32 ctrl_ver_masked;
1384
1385
1386
1387
1388 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1389 ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1390 ENA_REGS_CONTROLLER_VERSION_OFF);
1391
1392 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1393 (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1394 pr_err("Reg read timeout occurred\n");
1395 return -ETIME;
1396 }
1397
1398 pr_info("ena device version: %d.%d\n",
1399 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1400 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1401 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1402
1403 if (ver < MIN_ENA_VER) {
1404 pr_err("ENA version is lower than the minimal version the driver supports\n");
1405 return -1;
1406 }
1407
1408 pr_info("ena controller version: %d.%d.%d implementation version %d\n",
1409 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >>
1410 ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1411 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >>
1412 ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1413 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1414 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1415 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1416
1417 ctrl_ver_masked =
1418 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1419 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1420 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1421
1422
1423 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1424 pr_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1425 return -1;
1426 }
1427
1428 return 0;
1429}
1430
1431void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1432{
1433 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1434 struct ena_com_admin_cq *cq = &admin_queue->cq;
1435 struct ena_com_admin_sq *sq = &admin_queue->sq;
1436 struct ena_com_aenq *aenq = &ena_dev->aenq;
1437 u16 size;
1438
1439 if (admin_queue->comp_ctx)
1440 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx);
1441 admin_queue->comp_ctx = NULL;
1442 size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1443 if (sq->entries)
1444 dma_free_coherent(ena_dev->dmadev, size, sq->entries,
1445 sq->dma_addr);
1446 sq->entries = NULL;
1447
1448 size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1449 if (cq->entries)
1450 dma_free_coherent(ena_dev->dmadev, size, cq->entries,
1451 cq->dma_addr);
1452 cq->entries = NULL;
1453
1454 size = ADMIN_AENQ_SIZE(aenq->q_depth);
1455 if (ena_dev->aenq.entries)
1456 dma_free_coherent(ena_dev->dmadev, size, aenq->entries,
1457 aenq->dma_addr);
1458 aenq->entries = NULL;
1459}
1460
1461void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1462{
1463 u32 mask_value = 0;
1464
1465 if (polling)
1466 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1467
1468 writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1469 ena_dev->admin_queue.polling = polling;
1470}
1471
1472int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1473{
1474 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1475
1476 spin_lock_init(&mmio_read->lock);
1477 mmio_read->read_resp =
1478 dma_zalloc_coherent(ena_dev->dmadev,
1479 sizeof(*mmio_read->read_resp),
1480 &mmio_read->read_resp_dma_addr, GFP_KERNEL);
1481 if (unlikely(!mmio_read->read_resp))
1482 return -ENOMEM;
1483
1484 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1485
1486 mmio_read->read_resp->req_id = 0x0;
1487 mmio_read->seq_num = 0x0;
1488 mmio_read->readless_supported = true;
1489
1490 return 0;
1491}
1492
1493void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1494{
1495 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1496
1497 mmio_read->readless_supported = readless_supported;
1498}
1499
1500void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1501{
1502 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1503
1504 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1505 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1506
1507 dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp),
1508 mmio_read->read_resp, mmio_read->read_resp_dma_addr);
1509
1510 mmio_read->read_resp = NULL;
1511}
1512
1513void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1514{
1515 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1516 u32 addr_low, addr_high;
1517
1518 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1519 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1520
1521 writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1522 writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1523}
1524
1525int ena_com_admin_init(struct ena_com_dev *ena_dev,
1526 struct ena_aenq_handlers *aenq_handlers,
1527 bool init_spinlock)
1528{
1529 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1530 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1531 int ret;
1532
1533 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1534
1535 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1536 pr_err("Reg read timeout occurred\n");
1537 return -ETIME;
1538 }
1539
1540 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1541 pr_err("Device isn't ready, abort com init\n");
1542 return -ENODEV;
1543 }
1544
1545 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1546
1547 admin_queue->q_dmadev = ena_dev->dmadev;
1548 admin_queue->polling = false;
1549 admin_queue->curr_cmd_id = 0;
1550
1551 atomic_set(&admin_queue->outstanding_cmds, 0);
1552
1553 if (init_spinlock)
1554 spin_lock_init(&admin_queue->q_lock);
1555
1556 ret = ena_com_init_comp_ctxt(admin_queue);
1557 if (ret)
1558 goto error;
1559
1560 ret = ena_com_admin_init_sq(admin_queue);
1561 if (ret)
1562 goto error;
1563
1564 ret = ena_com_admin_init_cq(admin_queue);
1565 if (ret)
1566 goto error;
1567
1568 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1569 ENA_REGS_AQ_DB_OFF);
1570
1571 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1572 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1573
1574 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1575 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1576
1577 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1578 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1579
1580 writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1581 writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1582
1583 aq_caps = 0;
1584 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1585 aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1586 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1587 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1588
1589 acq_caps = 0;
1590 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1591 acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1592 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1593 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1594
1595 writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1596 writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1597 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1598 if (ret)
1599 goto error;
1600
1601 admin_queue->running_state = true;
1602
1603 return 0;
1604error:
1605 ena_com_admin_destroy(ena_dev);
1606
1607 return ret;
1608}
1609
1610int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1611 struct ena_com_create_io_ctx *ctx)
1612{
1613 struct ena_com_io_sq *io_sq;
1614 struct ena_com_io_cq *io_cq;
1615 int ret;
1616
1617 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1618 pr_err("Qid (%d) is bigger than max num of queues (%d)\n",
1619 ctx->qid, ENA_TOTAL_NUM_QUEUES);
1620 return -EINVAL;
1621 }
1622
1623 io_sq = &ena_dev->io_sq_queues[ctx->qid];
1624 io_cq = &ena_dev->io_cq_queues[ctx->qid];
1625
1626 memset(io_sq, 0x0, sizeof(*io_sq));
1627 memset(io_cq, 0x0, sizeof(*io_cq));
1628
1629
1630 io_cq->q_depth = ctx->queue_size;
1631 io_cq->direction = ctx->direction;
1632 io_cq->qid = ctx->qid;
1633
1634 io_cq->msix_vector = ctx->msix_vector;
1635
1636 io_sq->q_depth = ctx->queue_size;
1637 io_sq->direction = ctx->direction;
1638 io_sq->qid = ctx->qid;
1639
1640 io_sq->mem_queue_type = ctx->mem_queue_type;
1641
1642 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1643
1644 io_sq->tx_max_header_size =
1645 min_t(u32, ena_dev->tx_max_header_size, SZ_256);
1646
1647 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1648 if (ret)
1649 goto error;
1650 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1651 if (ret)
1652 goto error;
1653
1654 ret = ena_com_create_io_cq(ena_dev, io_cq);
1655 if (ret)
1656 goto error;
1657
1658 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1659 if (ret)
1660 goto destroy_io_cq;
1661
1662 return 0;
1663
1664destroy_io_cq:
1665 ena_com_destroy_io_cq(ena_dev, io_cq);
1666error:
1667 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1668 return ret;
1669}
1670
1671void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1672{
1673 struct ena_com_io_sq *io_sq;
1674 struct ena_com_io_cq *io_cq;
1675
1676 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1677 pr_err("Qid (%d) is bigger than max num of queues (%d)\n", qid,
1678 ENA_TOTAL_NUM_QUEUES);
1679 return;
1680 }
1681
1682 io_sq = &ena_dev->io_sq_queues[qid];
1683 io_cq = &ena_dev->io_cq_queues[qid];
1684
1685 ena_com_destroy_io_sq(ena_dev, io_sq);
1686 ena_com_destroy_io_cq(ena_dev, io_cq);
1687
1688 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1689}
1690
1691int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1692 struct ena_admin_get_feat_resp *resp)
1693{
1694 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG);
1695}
1696
1697int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1698 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1699{
1700 struct ena_admin_get_feat_resp get_resp;
1701 int rc;
1702
1703 rc = ena_com_get_feature(ena_dev, &get_resp,
1704 ENA_ADMIN_DEVICE_ATTRIBUTES);
1705 if (rc)
1706 return rc;
1707
1708 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1709 sizeof(get_resp.u.dev_attr));
1710 ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1711
1712 rc = ena_com_get_feature(ena_dev, &get_resp,
1713 ENA_ADMIN_MAX_QUEUES_NUM);
1714 if (rc)
1715 return rc;
1716
1717 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1718 sizeof(get_resp.u.max_queue));
1719 ena_dev->tx_max_header_size = get_resp.u.max_queue.max_header_size;
1720
1721 rc = ena_com_get_feature(ena_dev, &get_resp,
1722 ENA_ADMIN_AENQ_CONFIG);
1723 if (rc)
1724 return rc;
1725
1726 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1727 sizeof(get_resp.u.aenq));
1728
1729 rc = ena_com_get_feature(ena_dev, &get_resp,
1730 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
1731 if (rc)
1732 return rc;
1733
1734 memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
1735 sizeof(get_resp.u.offload));
1736
1737
1738
1739
1740 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS);
1741
1742 if (!rc)
1743 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
1744 sizeof(get_resp.u.hw_hints));
1745 else if (rc == -EOPNOTSUPP)
1746 memset(&get_feat_ctx->hw_hints, 0x0,
1747 sizeof(get_feat_ctx->hw_hints));
1748 else
1749 return rc;
1750
1751 return 0;
1752}
1753
1754void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
1755{
1756 ena_com_handle_admin_completion(&ena_dev->admin_queue);
1757}
1758
1759
1760
1761
1762static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
1763 u16 group)
1764{
1765 struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
1766
1767 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
1768 return aenq_handlers->handlers[group];
1769
1770 return aenq_handlers->unimplemented_handler;
1771}
1772
1773
1774
1775
1776
1777void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
1778{
1779 struct ena_admin_aenq_entry *aenq_e;
1780 struct ena_admin_aenq_common_desc *aenq_common;
1781 struct ena_com_aenq *aenq = &dev->aenq;
1782 ena_aenq_handler handler_cb;
1783 u16 masked_head, processed = 0;
1784 u8 phase;
1785
1786 masked_head = aenq->head & (aenq->q_depth - 1);
1787 phase = aenq->phase;
1788 aenq_e = &aenq->entries[masked_head];
1789 aenq_common = &aenq_e->aenq_common_desc;
1790
1791
1792 while ((READ_ONCE(aenq_common->flags) &
1793 ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
1794
1795
1796
1797 dma_rmb();
1798
1799 pr_debug("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n",
1800 aenq_common->group, aenq_common->syndrom,
1801 (u64)aenq_common->timestamp_low +
1802 ((u64)aenq_common->timestamp_high << 32));
1803
1804
1805 handler_cb = ena_com_get_specific_aenq_cb(dev,
1806 aenq_common->group);
1807 handler_cb(data, aenq_e);
1808
1809
1810 masked_head++;
1811 processed++;
1812
1813 if (unlikely(masked_head == aenq->q_depth)) {
1814 masked_head = 0;
1815 phase = !phase;
1816 }
1817 aenq_e = &aenq->entries[masked_head];
1818 aenq_common = &aenq_e->aenq_common_desc;
1819 }
1820
1821 aenq->head += processed;
1822 aenq->phase = phase;
1823
1824
1825 if (!processed)
1826 return;
1827
1828
1829 mb();
1830 writel_relaxed((u32)aenq->head,
1831 dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1832 mmiowb();
1833}
1834
1835int ena_com_dev_reset(struct ena_com_dev *ena_dev,
1836 enum ena_regs_reset_reason_types reset_reason)
1837{
1838 u32 stat, timeout, cap, reset_val;
1839 int rc;
1840
1841 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1842 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1843
1844 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
1845 (cap == ENA_MMIO_READ_TIMEOUT))) {
1846 pr_err("Reg read32 timeout occurred\n");
1847 return -ETIME;
1848 }
1849
1850 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
1851 pr_err("Device isn't ready, can't reset device\n");
1852 return -EINVAL;
1853 }
1854
1855 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
1856 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
1857 if (timeout == 0) {
1858 pr_err("Invalid timeout value\n");
1859 return -EINVAL;
1860 }
1861
1862
1863 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
1864 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
1865 ENA_REGS_DEV_CTL_RESET_REASON_MASK;
1866 writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
1867
1868
1869 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1870
1871 rc = wait_for_reset_state(ena_dev, timeout,
1872 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
1873 if (rc != 0) {
1874 pr_err("Reset indication didn't turn on\n");
1875 return rc;
1876 }
1877
1878
1879 writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
1880 rc = wait_for_reset_state(ena_dev, timeout, 0);
1881 if (rc != 0) {
1882 pr_err("Reset indication didn't turn off\n");
1883 return rc;
1884 }
1885
1886 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
1887 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
1888 if (timeout)
1889
1890 ena_dev->admin_queue.completion_timeout = timeout * 100000;
1891 else
1892 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
1893
1894 return 0;
1895}
1896
1897static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
1898 struct ena_com_stats_ctx *ctx,
1899 enum ena_admin_get_stats_type type)
1900{
1901 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
1902 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
1903 struct ena_com_admin_queue *admin_queue;
1904 int ret;
1905
1906 admin_queue = &ena_dev->admin_queue;
1907
1908 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
1909 get_cmd->aq_common_descriptor.flags = 0;
1910 get_cmd->type = type;
1911
1912 ret = ena_com_execute_admin_command(admin_queue,
1913 (struct ena_admin_aq_entry *)get_cmd,
1914 sizeof(*get_cmd),
1915 (struct ena_admin_acq_entry *)get_resp,
1916 sizeof(*get_resp));
1917
1918 if (unlikely(ret))
1919 pr_err("Failed to get stats. error: %d\n", ret);
1920
1921 return ret;
1922}
1923
1924int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
1925 struct ena_admin_basic_stats *stats)
1926{
1927 struct ena_com_stats_ctx ctx;
1928 int ret;
1929
1930 memset(&ctx, 0x0, sizeof(ctx));
1931 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
1932 if (likely(ret == 0))
1933 memcpy(stats, &ctx.get_resp.basic_stats,
1934 sizeof(ctx.get_resp.basic_stats));
1935
1936 return ret;
1937}
1938
1939int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
1940{
1941 struct ena_com_admin_queue *admin_queue;
1942 struct ena_admin_set_feat_cmd cmd;
1943 struct ena_admin_set_feat_resp resp;
1944 int ret;
1945
1946 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
1947 pr_debug("Feature %d isn't supported\n", ENA_ADMIN_MTU);
1948 return -EOPNOTSUPP;
1949 }
1950
1951 memset(&cmd, 0x0, sizeof(cmd));
1952 admin_queue = &ena_dev->admin_queue;
1953
1954 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1955 cmd.aq_common_descriptor.flags = 0;
1956 cmd.feat_common.feature_id = ENA_ADMIN_MTU;
1957 cmd.u.mtu.mtu = mtu;
1958
1959 ret = ena_com_execute_admin_command(admin_queue,
1960 (struct ena_admin_aq_entry *)&cmd,
1961 sizeof(cmd),
1962 (struct ena_admin_acq_entry *)&resp,
1963 sizeof(resp));
1964
1965 if (unlikely(ret))
1966 pr_err("Failed to set mtu %d. error: %d\n", mtu, ret);
1967
1968 return ret;
1969}
1970
1971int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
1972 struct ena_admin_feature_offload_desc *offload)
1973{
1974 int ret;
1975 struct ena_admin_get_feat_resp resp;
1976
1977 ret = ena_com_get_feature(ena_dev, &resp,
1978 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
1979 if (unlikely(ret)) {
1980 pr_err("Failed to get offload capabilities %d\n", ret);
1981 return ret;
1982 }
1983
1984 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
1985
1986 return 0;
1987}
1988
1989int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
1990{
1991 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1992 struct ena_rss *rss = &ena_dev->rss;
1993 struct ena_admin_set_feat_cmd cmd;
1994 struct ena_admin_set_feat_resp resp;
1995 struct ena_admin_get_feat_resp get_resp;
1996 int ret;
1997
1998 if (!ena_com_check_supported_feature_id(ena_dev,
1999 ENA_ADMIN_RSS_HASH_FUNCTION)) {
2000 pr_debug("Feature %d isn't supported\n",
2001 ENA_ADMIN_RSS_HASH_FUNCTION);
2002 return -EOPNOTSUPP;
2003 }
2004
2005
2006 ret = ena_com_get_feature(ena_dev, &get_resp,
2007 ENA_ADMIN_RSS_HASH_FUNCTION);
2008 if (unlikely(ret))
2009 return ret;
2010
2011 if (get_resp.u.flow_hash_func.supported_func & (1 << rss->hash_func)) {
2012 pr_err("Func hash %d isn't supported by device, abort\n",
2013 rss->hash_func);
2014 return -EOPNOTSUPP;
2015 }
2016
2017 memset(&cmd, 0x0, sizeof(cmd));
2018
2019 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2020 cmd.aq_common_descriptor.flags =
2021 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2022 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2023 cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2024 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2025
2026 ret = ena_com_mem_addr_set(ena_dev,
2027 &cmd.control_buffer.address,
2028 rss->hash_key_dma_addr);
2029 if (unlikely(ret)) {
2030 pr_err("memory address set failed\n");
2031 return ret;
2032 }
2033
2034 cmd.control_buffer.length = sizeof(*rss->hash_key);
2035
2036 ret = ena_com_execute_admin_command(admin_queue,
2037 (struct ena_admin_aq_entry *)&cmd,
2038 sizeof(cmd),
2039 (struct ena_admin_acq_entry *)&resp,
2040 sizeof(resp));
2041 if (unlikely(ret)) {
2042 pr_err("Failed to set hash function %d. error: %d\n",
2043 rss->hash_func, ret);
2044 return -EINVAL;
2045 }
2046
2047 return 0;
2048}
2049
2050int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2051 enum ena_admin_hash_functions func,
2052 const u8 *key, u16 key_len, u32 init_val)
2053{
2054 struct ena_rss *rss = &ena_dev->rss;
2055 struct ena_admin_get_feat_resp get_resp;
2056 struct ena_admin_feature_rss_flow_hash_control *hash_key =
2057 rss->hash_key;
2058 int rc;
2059
2060
2061 if (unlikely(key_len & 0x3))
2062 return -EINVAL;
2063
2064 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2065 ENA_ADMIN_RSS_HASH_FUNCTION,
2066 rss->hash_key_dma_addr,
2067 sizeof(*rss->hash_key));
2068 if (unlikely(rc))
2069 return rc;
2070
2071 if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) {
2072 pr_err("Flow hash function %d isn't supported\n", func);
2073 return -EOPNOTSUPP;
2074 }
2075
2076 switch (func) {
2077 case ENA_ADMIN_TOEPLITZ:
2078 if (key_len > sizeof(hash_key->key)) {
2079 pr_err("key len (%hu) is bigger than the max supported (%zu)\n",
2080 key_len, sizeof(hash_key->key));
2081 return -EINVAL;
2082 }
2083
2084 memcpy(hash_key->key, key, key_len);
2085 rss->hash_init_val = init_val;
2086 hash_key->keys_num = key_len >> 2;
2087 break;
2088 case ENA_ADMIN_CRC32:
2089 rss->hash_init_val = init_val;
2090 break;
2091 default:
2092 pr_err("Invalid hash function (%d)\n", func);
2093 return -EINVAL;
2094 }
2095
2096 rc = ena_com_set_hash_function(ena_dev);
2097
2098
2099 if (unlikely(rc))
2100 ena_com_get_hash_function(ena_dev, NULL, NULL);
2101
2102 return rc;
2103}
2104
2105int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2106 enum ena_admin_hash_functions *func,
2107 u8 *key)
2108{
2109 struct ena_rss *rss = &ena_dev->rss;
2110 struct ena_admin_get_feat_resp get_resp;
2111 struct ena_admin_feature_rss_flow_hash_control *hash_key =
2112 rss->hash_key;
2113 int rc;
2114
2115 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2116 ENA_ADMIN_RSS_HASH_FUNCTION,
2117 rss->hash_key_dma_addr,
2118 sizeof(*rss->hash_key));
2119 if (unlikely(rc))
2120 return rc;
2121
2122 rss->hash_func = get_resp.u.flow_hash_func.selected_func;
2123 if (func)
2124 *func = rss->hash_func;
2125
2126 if (key)
2127 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2128
2129 return 0;
2130}
2131
2132int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2133 enum ena_admin_flow_hash_proto proto,
2134 u16 *fields)
2135{
2136 struct ena_rss *rss = &ena_dev->rss;
2137 struct ena_admin_get_feat_resp get_resp;
2138 int rc;
2139
2140 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2141 ENA_ADMIN_RSS_HASH_INPUT,
2142 rss->hash_ctrl_dma_addr,
2143 sizeof(*rss->hash_ctrl));
2144 if (unlikely(rc))
2145 return rc;
2146
2147 if (fields)
2148 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2149
2150 return 0;
2151}
2152
2153int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2154{
2155 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2156 struct ena_rss *rss = &ena_dev->rss;
2157 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2158 struct ena_admin_set_feat_cmd cmd;
2159 struct ena_admin_set_feat_resp resp;
2160 int ret;
2161
2162 if (!ena_com_check_supported_feature_id(ena_dev,
2163 ENA_ADMIN_RSS_HASH_INPUT)) {
2164 pr_debug("Feature %d isn't supported\n",
2165 ENA_ADMIN_RSS_HASH_INPUT);
2166 return -EOPNOTSUPP;
2167 }
2168
2169 memset(&cmd, 0x0, sizeof(cmd));
2170
2171 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2172 cmd.aq_common_descriptor.flags =
2173 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2174 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2175 cmd.u.flow_hash_input.enabled_input_sort =
2176 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2177 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2178
2179 ret = ena_com_mem_addr_set(ena_dev,
2180 &cmd.control_buffer.address,
2181 rss->hash_ctrl_dma_addr);
2182 if (unlikely(ret)) {
2183 pr_err("memory address set failed\n");
2184 return ret;
2185 }
2186 cmd.control_buffer.length = sizeof(*hash_ctrl);
2187
2188 ret = ena_com_execute_admin_command(admin_queue,
2189 (struct ena_admin_aq_entry *)&cmd,
2190 sizeof(cmd),
2191 (struct ena_admin_acq_entry *)&resp,
2192 sizeof(resp));
2193 if (unlikely(ret))
2194 pr_err("Failed to set hash input. error: %d\n", ret);
2195
2196 return ret;
2197}
2198
2199int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2200{
2201 struct ena_rss *rss = &ena_dev->rss;
2202 struct ena_admin_feature_rss_hash_control *hash_ctrl =
2203 rss->hash_ctrl;
2204 u16 available_fields = 0;
2205 int rc, i;
2206
2207
2208 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2209 if (unlikely(rc))
2210 return rc;
2211
2212 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2213 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2214 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2215
2216 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2217 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2218 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2219
2220 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2221 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2222 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2223
2224 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2225 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2226 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2227
2228 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2229 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2230
2231 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2232 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2233
2234 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2235 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2236
2237 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2238 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2239
2240 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2241 available_fields = hash_ctrl->selected_fields[i].fields &
2242 hash_ctrl->supported_fields[i].fields;
2243 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2244 pr_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2245 i, hash_ctrl->supported_fields[i].fields,
2246 hash_ctrl->selected_fields[i].fields);
2247 return -EOPNOTSUPP;
2248 }
2249 }
2250
2251 rc = ena_com_set_hash_ctrl(ena_dev);
2252
2253
2254 if (unlikely(rc))
2255 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2256
2257 return rc;
2258}
2259
2260int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2261 enum ena_admin_flow_hash_proto proto,
2262 u16 hash_fields)
2263{
2264 struct ena_rss *rss = &ena_dev->rss;
2265 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2266 u16 supported_fields;
2267 int rc;
2268
2269 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2270 pr_err("Invalid proto num (%u)\n", proto);
2271 return -EINVAL;
2272 }
2273
2274
2275 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2276 if (unlikely(rc))
2277 return rc;
2278
2279
2280 supported_fields = hash_ctrl->supported_fields[proto].fields;
2281 if ((hash_fields & supported_fields) != hash_fields) {
2282 pr_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2283 proto, hash_fields, supported_fields);
2284 }
2285
2286 hash_ctrl->selected_fields[proto].fields = hash_fields;
2287
2288 rc = ena_com_set_hash_ctrl(ena_dev);
2289
2290
2291 if (unlikely(rc))
2292 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2293
2294 return 0;
2295}
2296
2297int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2298 u16 entry_idx, u16 entry_value)
2299{
2300 struct ena_rss *rss = &ena_dev->rss;
2301
2302 if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2303 return -EINVAL;
2304
2305 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2306 return -EINVAL;
2307
2308 rss->host_rss_ind_tbl[entry_idx] = entry_value;
2309
2310 return 0;
2311}
2312
2313int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2314{
2315 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2316 struct ena_rss *rss = &ena_dev->rss;
2317 struct ena_admin_set_feat_cmd cmd;
2318 struct ena_admin_set_feat_resp resp;
2319 int ret;
2320
2321 if (!ena_com_check_supported_feature_id(
2322 ena_dev, ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2323 pr_debug("Feature %d isn't supported\n",
2324 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2325 return -EOPNOTSUPP;
2326 }
2327
2328 ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2329 if (ret) {
2330 pr_err("Failed to convert host indirection table to device table\n");
2331 return ret;
2332 }
2333
2334 memset(&cmd, 0x0, sizeof(cmd));
2335
2336 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2337 cmd.aq_common_descriptor.flags =
2338 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2339 cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2340 cmd.u.ind_table.size = rss->tbl_log_size;
2341 cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2342
2343 ret = ena_com_mem_addr_set(ena_dev,
2344 &cmd.control_buffer.address,
2345 rss->rss_ind_tbl_dma_addr);
2346 if (unlikely(ret)) {
2347 pr_err("memory address set failed\n");
2348 return ret;
2349 }
2350
2351 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2352 sizeof(struct ena_admin_rss_ind_table_entry);
2353
2354 ret = ena_com_execute_admin_command(admin_queue,
2355 (struct ena_admin_aq_entry *)&cmd,
2356 sizeof(cmd),
2357 (struct ena_admin_acq_entry *)&resp,
2358 sizeof(resp));
2359
2360 if (unlikely(ret))
2361 pr_err("Failed to set indirect table. error: %d\n", ret);
2362
2363 return ret;
2364}
2365
2366int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2367{
2368 struct ena_rss *rss = &ena_dev->rss;
2369 struct ena_admin_get_feat_resp get_resp;
2370 u32 tbl_size;
2371 int i, rc;
2372
2373 tbl_size = (1ULL << rss->tbl_log_size) *
2374 sizeof(struct ena_admin_rss_ind_table_entry);
2375
2376 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2377 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2378 rss->rss_ind_tbl_dma_addr,
2379 tbl_size);
2380 if (unlikely(rc))
2381 return rc;
2382
2383 if (!ind_tbl)
2384 return 0;
2385
2386 rc = ena_com_ind_tbl_convert_from_device(ena_dev);
2387 if (unlikely(rc))
2388 return rc;
2389
2390 for (i = 0; i < (1 << rss->tbl_log_size); i++)
2391 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2392
2393 return 0;
2394}
2395
2396int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2397{
2398 int rc;
2399
2400 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2401
2402 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2403 if (unlikely(rc))
2404 goto err_indr_tbl;
2405
2406 rc = ena_com_hash_key_allocate(ena_dev);
2407 if (unlikely(rc))
2408 goto err_hash_key;
2409
2410 rc = ena_com_hash_ctrl_init(ena_dev);
2411 if (unlikely(rc))
2412 goto err_hash_ctrl;
2413
2414 return 0;
2415
2416err_hash_ctrl:
2417 ena_com_hash_key_destroy(ena_dev);
2418err_hash_key:
2419 ena_com_indirect_table_destroy(ena_dev);
2420err_indr_tbl:
2421
2422 return rc;
2423}
2424
2425void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2426{
2427 ena_com_indirect_table_destroy(ena_dev);
2428 ena_com_hash_key_destroy(ena_dev);
2429 ena_com_hash_ctrl_destroy(ena_dev);
2430
2431 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2432}
2433
2434int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2435{
2436 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2437
2438 host_attr->host_info =
2439 dma_zalloc_coherent(ena_dev->dmadev, SZ_4K,
2440 &host_attr->host_info_dma_addr, GFP_KERNEL);
2441 if (unlikely(!host_attr->host_info))
2442 return -ENOMEM;
2443
2444 return 0;
2445}
2446
2447int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2448 u32 debug_area_size)
2449{
2450 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2451
2452 host_attr->debug_area_virt_addr =
2453 dma_zalloc_coherent(ena_dev->dmadev, debug_area_size,
2454 &host_attr->debug_area_dma_addr, GFP_KERNEL);
2455 if (unlikely(!host_attr->debug_area_virt_addr)) {
2456 host_attr->debug_area_size = 0;
2457 return -ENOMEM;
2458 }
2459
2460 host_attr->debug_area_size = debug_area_size;
2461
2462 return 0;
2463}
2464
2465void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2466{
2467 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2468
2469 if (host_attr->host_info) {
2470 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info,
2471 host_attr->host_info_dma_addr);
2472 host_attr->host_info = NULL;
2473 }
2474}
2475
2476void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2477{
2478 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2479
2480 if (host_attr->debug_area_virt_addr) {
2481 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size,
2482 host_attr->debug_area_virt_addr,
2483 host_attr->debug_area_dma_addr);
2484 host_attr->debug_area_virt_addr = NULL;
2485 }
2486}
2487
2488int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2489{
2490 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2491 struct ena_com_admin_queue *admin_queue;
2492 struct ena_admin_set_feat_cmd cmd;
2493 struct ena_admin_set_feat_resp resp;
2494
2495 int ret;
2496
2497
2498
2499
2500
2501 memset(&cmd, 0x0, sizeof(cmd));
2502 admin_queue = &ena_dev->admin_queue;
2503
2504 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2505 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2506
2507 ret = ena_com_mem_addr_set(ena_dev,
2508 &cmd.u.host_attr.debug_ba,
2509 host_attr->debug_area_dma_addr);
2510 if (unlikely(ret)) {
2511 pr_err("memory address set failed\n");
2512 return ret;
2513 }
2514
2515 ret = ena_com_mem_addr_set(ena_dev,
2516 &cmd.u.host_attr.os_info_ba,
2517 host_attr->host_info_dma_addr);
2518 if (unlikely(ret)) {
2519 pr_err("memory address set failed\n");
2520 return ret;
2521 }
2522
2523 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2524
2525 ret = ena_com_execute_admin_command(admin_queue,
2526 (struct ena_admin_aq_entry *)&cmd,
2527 sizeof(cmd),
2528 (struct ena_admin_acq_entry *)&resp,
2529 sizeof(resp));
2530
2531 if (unlikely(ret))
2532 pr_err("Failed to set host attributes: %d\n", ret);
2533
2534 return ret;
2535}
2536
2537
2538bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2539{
2540 return ena_com_check_supported_feature_id(ena_dev,
2541 ENA_ADMIN_INTERRUPT_MODERATION);
2542}
2543
2544int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2545 u32 tx_coalesce_usecs)
2546{
2547 if (!ena_dev->intr_delay_resolution) {
2548 pr_err("Illegal interrupt delay granularity value\n");
2549 return -EFAULT;
2550 }
2551
2552 ena_dev->intr_moder_tx_interval = tx_coalesce_usecs /
2553 ena_dev->intr_delay_resolution;
2554
2555 return 0;
2556}
2557
2558int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2559 u32 rx_coalesce_usecs)
2560{
2561 if (!ena_dev->intr_delay_resolution) {
2562 pr_err("Illegal interrupt delay granularity value\n");
2563 return -EFAULT;
2564 }
2565
2566
2567
2568
2569 ena_dev->intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2570 rx_coalesce_usecs / ena_dev->intr_delay_resolution;
2571
2572 return 0;
2573}
2574
2575void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev)
2576{
2577 if (ena_dev->intr_moder_tbl)
2578 devm_kfree(ena_dev->dmadev, ena_dev->intr_moder_tbl);
2579 ena_dev->intr_moder_tbl = NULL;
2580}
2581
2582int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2583{
2584 struct ena_admin_get_feat_resp get_resp;
2585 u16 delay_resolution;
2586 int rc;
2587
2588 rc = ena_com_get_feature(ena_dev, &get_resp,
2589 ENA_ADMIN_INTERRUPT_MODERATION);
2590
2591 if (rc) {
2592 if (rc == -EOPNOTSUPP) {
2593 pr_debug("Feature %d isn't supported\n",
2594 ENA_ADMIN_INTERRUPT_MODERATION);
2595 rc = 0;
2596 } else {
2597 pr_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2598 rc);
2599 }
2600
2601
2602 ena_com_disable_adaptive_moderation(ena_dev);
2603 return rc;
2604 }
2605
2606 rc = ena_com_init_interrupt_moderation_table(ena_dev);
2607 if (rc)
2608 goto err;
2609
2610
2611 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2612 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2613 ena_com_enable_adaptive_moderation(ena_dev);
2614
2615 return 0;
2616err:
2617 ena_com_destroy_interrupt_moderation(ena_dev);
2618 return rc;
2619}
2620
2621void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev)
2622{
2623 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2624
2625 if (!intr_moder_tbl)
2626 return;
2627
2628 intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2629 ENA_INTR_LOWEST_USECS;
2630 intr_moder_tbl[ENA_INTR_MODER_LOWEST].pkts_per_interval =
2631 ENA_INTR_LOWEST_PKTS;
2632 intr_moder_tbl[ENA_INTR_MODER_LOWEST].bytes_per_interval =
2633 ENA_INTR_LOWEST_BYTES;
2634
2635 intr_moder_tbl[ENA_INTR_MODER_LOW].intr_moder_interval =
2636 ENA_INTR_LOW_USECS;
2637 intr_moder_tbl[ENA_INTR_MODER_LOW].pkts_per_interval =
2638 ENA_INTR_LOW_PKTS;
2639 intr_moder_tbl[ENA_INTR_MODER_LOW].bytes_per_interval =
2640 ENA_INTR_LOW_BYTES;
2641
2642 intr_moder_tbl[ENA_INTR_MODER_MID].intr_moder_interval =
2643 ENA_INTR_MID_USECS;
2644 intr_moder_tbl[ENA_INTR_MODER_MID].pkts_per_interval =
2645 ENA_INTR_MID_PKTS;
2646 intr_moder_tbl[ENA_INTR_MODER_MID].bytes_per_interval =
2647 ENA_INTR_MID_BYTES;
2648
2649 intr_moder_tbl[ENA_INTR_MODER_HIGH].intr_moder_interval =
2650 ENA_INTR_HIGH_USECS;
2651 intr_moder_tbl[ENA_INTR_MODER_HIGH].pkts_per_interval =
2652 ENA_INTR_HIGH_PKTS;
2653 intr_moder_tbl[ENA_INTR_MODER_HIGH].bytes_per_interval =
2654 ENA_INTR_HIGH_BYTES;
2655
2656 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].intr_moder_interval =
2657 ENA_INTR_HIGHEST_USECS;
2658 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].pkts_per_interval =
2659 ENA_INTR_HIGHEST_PKTS;
2660 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].bytes_per_interval =
2661 ENA_INTR_HIGHEST_BYTES;
2662}
2663
2664unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2665{
2666 return ena_dev->intr_moder_tx_interval;
2667}
2668
2669unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2670{
2671 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2672
2673 if (intr_moder_tbl)
2674 return intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval;
2675
2676 return 0;
2677}
2678
2679void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev,
2680 enum ena_intr_moder_level level,
2681 struct ena_intr_moder_entry *entry)
2682{
2683 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2684
2685 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
2686 return;
2687
2688 intr_moder_tbl[level].intr_moder_interval = entry->intr_moder_interval;
2689 if (ena_dev->intr_delay_resolution)
2690 intr_moder_tbl[level].intr_moder_interval /=
2691 ena_dev->intr_delay_resolution;
2692 intr_moder_tbl[level].pkts_per_interval = entry->pkts_per_interval;
2693
2694
2695 if (entry->bytes_per_interval != ENA_INTR_BYTE_COUNT_NOT_SUPPORTED)
2696 intr_moder_tbl[level].bytes_per_interval = entry->bytes_per_interval;
2697}
2698
2699void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
2700 enum ena_intr_moder_level level,
2701 struct ena_intr_moder_entry *entry)
2702{
2703 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2704
2705 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
2706 return;
2707
2708 entry->intr_moder_interval = intr_moder_tbl[level].intr_moder_interval;
2709 if (ena_dev->intr_delay_resolution)
2710 entry->intr_moder_interval *= ena_dev->intr_delay_resolution;
2711 entry->pkts_per_interval =
2712 intr_moder_tbl[level].pkts_per_interval;
2713 entry->bytes_per_interval = intr_moder_tbl[level].bytes_per_interval;
2714}
2715
