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2
3
4#ifndef _E1000_DEFINES_H_
5#define _E1000_DEFINES_H_
6
7
8#define REQ_TX_DESCRIPTOR_MULTIPLE 8
9#define REQ_RX_DESCRIPTOR_MULTIPLE 8
10
11
12
13#define E1000_WUC_APME 0x00000001
14#define E1000_WUC_PME_EN 0x00000002
15#define E1000_WUC_PME_STATUS 0x00000004
16#define E1000_WUC_APMPME 0x00000008
17#define E1000_WUC_PHY_WAKE 0x00000100
18
19
20#define E1000_WUFC_LNKC 0x00000001
21#define E1000_WUFC_MAG 0x00000002
22#define E1000_WUFC_EX 0x00000004
23#define E1000_WUFC_MC 0x00000008
24#define E1000_WUFC_BC 0x00000010
25#define E1000_WUFC_ARP 0x00000020
26
27
28#define E1000_WUS_LNKC E1000_WUFC_LNKC
29#define E1000_WUS_MAG E1000_WUFC_MAG
30#define E1000_WUS_EX E1000_WUFC_EX
31#define E1000_WUS_MC E1000_WUFC_MC
32#define E1000_WUS_BC E1000_WUFC_BC
33
34
35#define E1000_CTRL_EXT_LPCD 0x00000004
36#define E1000_CTRL_EXT_SDP3_DATA 0x00000080
37#define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800
38#define E1000_CTRL_EXT_EE_RST 0x00002000
39#define E1000_CTRL_EXT_SPD_BYPS 0x00008000
40#define E1000_CTRL_EXT_RO_DIS 0x00020000
41#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000
42#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
43#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
44#define E1000_CTRL_EXT_EIAME 0x01000000
45#define E1000_CTRL_EXT_DRV_LOAD 0x10000000
46#define E1000_CTRL_EXT_IAME 0x08000000
47#define E1000_CTRL_EXT_PBA_CLR 0x80000000
48#define E1000_CTRL_EXT_LSECCK 0x00001000
49#define E1000_CTRL_EXT_PHYPDEN 0x00100000
50
51
52#define E1000_RXD_STAT_DD 0x01
53#define E1000_RXD_STAT_EOP 0x02
54#define E1000_RXD_STAT_IXSM 0x04
55#define E1000_RXD_STAT_VP 0x08
56#define E1000_RXD_STAT_UDPCS 0x10
57#define E1000_RXD_STAT_TCPCS 0x20
58#define E1000_RXD_ERR_CE 0x01
59#define E1000_RXD_ERR_SE 0x02
60#define E1000_RXD_ERR_SEQ 0x04
61#define E1000_RXD_ERR_CXE 0x10
62#define E1000_RXD_ERR_TCPE 0x20
63#define E1000_RXD_ERR_IPE 0x40
64#define E1000_RXD_ERR_RXE 0x80
65#define E1000_RXD_SPC_VLAN_MASK 0x0FFF
66
67#define E1000_RXDEXT_STATERR_TST 0x00000100
68#define E1000_RXDEXT_STATERR_CE 0x01000000
69#define E1000_RXDEXT_STATERR_SE 0x02000000
70#define E1000_RXDEXT_STATERR_SEQ 0x04000000
71#define E1000_RXDEXT_STATERR_CXE 0x10000000
72#define E1000_RXDEXT_STATERR_RXE 0x80000000
73
74
75#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
76 E1000_RXD_ERR_CE | \
77 E1000_RXD_ERR_SE | \
78 E1000_RXD_ERR_SEQ | \
79 E1000_RXD_ERR_CXE | \
80 E1000_RXD_ERR_RXE)
81
82
83#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
84 E1000_RXDEXT_STATERR_CE | \
85 E1000_RXDEXT_STATERR_SE | \
86 E1000_RXDEXT_STATERR_SEQ | \
87 E1000_RXDEXT_STATERR_CXE | \
88 E1000_RXDEXT_STATERR_RXE)
89
90#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
91#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
92#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
93#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
94#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
95#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
96
97#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
98
99
100#define E1000_MANC_SMBUS_EN 0x00000001
101#define E1000_MANC_ASF_EN 0x00000002
102#define E1000_MANC_ARP_EN 0x00002000
103#define E1000_MANC_RCV_TCO_EN 0x00020000
104#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000
105
106#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
107
108#define E1000_MANC_EN_MNG2HOST 0x00200000
109
110#define E1000_MANC2H_PORT_623 0x00000020
111#define E1000_MANC2H_PORT_664 0x00000040
112#define E1000_MDEF_PORT_623 0x00000800
113#define E1000_MDEF_PORT_664 0x00000400
114
115
116#define E1000_RCTL_EN 0x00000002
117#define E1000_RCTL_SBP 0x00000004
118#define E1000_RCTL_UPE 0x00000008
119#define E1000_RCTL_MPE 0x00000010
120#define E1000_RCTL_LPE 0x00000020
121#define E1000_RCTL_LBM_NO 0x00000000
122#define E1000_RCTL_LBM_MAC 0x00000040
123#define E1000_RCTL_LBM_TCVR 0x000000C0
124#define E1000_RCTL_DTYP_PS 0x00000400
125#define E1000_RCTL_RDMTS_HALF 0x00000000
126#define E1000_RCTL_RDMTS_HEX 0x00010000
127#define E1000_RCTL_MO_SHIFT 12
128#define E1000_RCTL_MO_3 0x00003000
129#define E1000_RCTL_BAM 0x00008000
130
131#define E1000_RCTL_SZ_2048 0x00000000
132#define E1000_RCTL_SZ_1024 0x00010000
133#define E1000_RCTL_SZ_512 0x00020000
134#define E1000_RCTL_SZ_256 0x00030000
135
136#define E1000_RCTL_SZ_16384 0x00010000
137#define E1000_RCTL_SZ_8192 0x00020000
138#define E1000_RCTL_SZ_4096 0x00030000
139#define E1000_RCTL_VFE 0x00040000
140#define E1000_RCTL_CFIEN 0x00080000
141#define E1000_RCTL_CFI 0x00100000
142#define E1000_RCTL_DPF 0x00400000
143#define E1000_RCTL_PMCF 0x00800000
144#define E1000_RCTL_BSEX 0x02000000
145#define E1000_RCTL_SECRC 0x04000000
146
147
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149
150
151
152
153
154
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160
161
162
163#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
164#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
165#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
166#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
167
168#define E1000_PSRCTL_BSIZE0_SHIFT 7
169#define E1000_PSRCTL_BSIZE1_SHIFT 2
170#define E1000_PSRCTL_BSIZE2_SHIFT 6
171#define E1000_PSRCTL_BSIZE3_SHIFT 14
172
173
174#define E1000_SWFW_EEP_SM 0x1
175#define E1000_SWFW_PHY0_SM 0x2
176#define E1000_SWFW_PHY1_SM 0x4
177#define E1000_SWFW_CSR_SM 0x8
178
179
180#define E1000_CTRL_FD 0x00000001
181#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004
182#define E1000_CTRL_LRST 0x00000008
183#define E1000_CTRL_ASDE 0x00000020
184#define E1000_CTRL_SLU 0x00000040
185#define E1000_CTRL_ILOS 0x00000080
186#define E1000_CTRL_SPD_SEL 0x00000300
187#define E1000_CTRL_SPD_10 0x00000000
188#define E1000_CTRL_SPD_100 0x00000100
189#define E1000_CTRL_SPD_1000 0x00000200
190#define E1000_CTRL_FRCSPD 0x00000800
191#define E1000_CTRL_FRCDPX 0x00001000
192#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000
193#define E1000_CTRL_LANPHYPC_VALUE 0x00020000
194#define E1000_CTRL_MEHE 0x00080000
195#define E1000_CTRL_SWDPIN0 0x00040000
196#define E1000_CTRL_SWDPIN1 0x00080000
197#define E1000_CTRL_ADVD3WUC 0x00100000
198#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
199#define E1000_CTRL_SWDPIO0 0x00400000
200#define E1000_CTRL_RST 0x04000000
201#define E1000_CTRL_RFCE 0x08000000
202#define E1000_CTRL_TFCE 0x10000000
203#define E1000_CTRL_VME 0x40000000
204#define E1000_CTRL_PHY_RST 0x80000000
205
206#define E1000_PCS_LCTL_FORCE_FCTRL 0x80
207
208#define E1000_PCS_LSTS_AN_COMPLETE 0x10000
209
210
211#define E1000_STATUS_FD 0x00000001
212#define E1000_STATUS_LU 0x00000002
213#define E1000_STATUS_FUNC_MASK 0x0000000C
214#define E1000_STATUS_FUNC_SHIFT 2
215#define E1000_STATUS_FUNC_1 0x00000004
216#define E1000_STATUS_TXOFF 0x00000010
217#define E1000_STATUS_SPEED_MASK 0x000000C0
218#define E1000_STATUS_SPEED_10 0x00000000
219#define E1000_STATUS_SPEED_100 0x00000040
220#define E1000_STATUS_SPEED_1000 0x00000080
221#define E1000_STATUS_LAN_INIT_DONE 0x00000200
222#define E1000_STATUS_PHYRA 0x00000400
223#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
224
225#define HALF_DUPLEX 1
226#define FULL_DUPLEX 2
227
228#define ADVERTISE_10_HALF 0x0001
229#define ADVERTISE_10_FULL 0x0002
230#define ADVERTISE_100_HALF 0x0004
231#define ADVERTISE_100_FULL 0x0008
232#define ADVERTISE_1000_HALF 0x0010
233#define ADVERTISE_1000_FULL 0x0020
234
235
236#define E1000_ALL_SPEED_DUPLEX ( \
237 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
238 ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
239#define E1000_ALL_NOT_GIG ( \
240 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
241 ADVERTISE_100_FULL)
242#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
243#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
244#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
245
246#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
247
248
249#define E1000_PHY_LED0_MODE_MASK 0x00000007
250#define E1000_PHY_LED0_IVRT 0x00000008
251#define E1000_PHY_LED0_MASK 0x0000001F
252
253#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
254#define E1000_LEDCTL_LED0_MODE_SHIFT 0
255#define E1000_LEDCTL_LED0_IVRT 0x00000040
256#define E1000_LEDCTL_LED0_BLINK 0x00000080
257
258#define E1000_LEDCTL_MODE_LINK_UP 0x2
259#define E1000_LEDCTL_MODE_LED_ON 0xE
260#define E1000_LEDCTL_MODE_LED_OFF 0xF
261
262
263#define E1000_TXD_DTYP_D 0x00100000
264#define E1000_TXD_POPTS_IXSM 0x01
265#define E1000_TXD_POPTS_TXSM 0x02
266#define E1000_TXD_CMD_EOP 0x01000000
267#define E1000_TXD_CMD_IFCS 0x02000000
268#define E1000_TXD_CMD_IC 0x04000000
269#define E1000_TXD_CMD_RS 0x08000000
270#define E1000_TXD_CMD_RPS 0x10000000
271#define E1000_TXD_CMD_DEXT 0x20000000
272#define E1000_TXD_CMD_VLE 0x40000000
273#define E1000_TXD_CMD_IDE 0x80000000
274#define E1000_TXD_STAT_DD 0x00000001
275#define E1000_TXD_STAT_EC 0x00000002
276#define E1000_TXD_STAT_LC 0x00000004
277#define E1000_TXD_STAT_TU 0x00000008
278#define E1000_TXD_CMD_TCP 0x01000000
279#define E1000_TXD_CMD_IP 0x02000000
280#define E1000_TXD_CMD_TSE 0x04000000
281#define E1000_TXD_STAT_TC 0x00000004
282#define E1000_TXD_EXTCMD_TSTAMP 0x00000010
283
284
285#define E1000_TCTL_EN 0x00000002
286#define E1000_TCTL_PSP 0x00000008
287#define E1000_TCTL_CT 0x00000ff0
288#define E1000_TCTL_COLD 0x003ff000
289#define E1000_TCTL_RTLC 0x01000000
290#define E1000_TCTL_MULR 0x10000000
291
292
293#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
294#define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410
295
296
297#define E1000_RXCSUM_TUOFL 0x00000200
298#define E1000_RXCSUM_IPPCSE 0x00001000
299#define E1000_RXCSUM_PCSD 0x00002000
300
301
302#define E1000_RFCTL_NFSW_DIS 0x00000040
303#define E1000_RFCTL_NFSR_DIS 0x00000080
304#define E1000_RFCTL_ACK_DIS 0x00001000
305#define E1000_RFCTL_EXTEN 0x00008000
306#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
307#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
308
309
310#define E1000_COLLISION_THRESHOLD 15
311#define E1000_CT_SHIFT 4
312#define E1000_COLLISION_DISTANCE 63
313#define E1000_COLD_SHIFT 12
314
315
316#define DEFAULT_82543_TIPG_IPGT_COPPER 8
317
318#define E1000_TIPG_IPGT_MASK 0x000003FF
319
320#define DEFAULT_82543_TIPG_IPGR1 8
321#define E1000_TIPG_IPGR1_SHIFT 10
322
323#define DEFAULT_82543_TIPG_IPGR2 6
324#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
325#define E1000_TIPG_IPGR2_SHIFT 20
326
327#define MAX_JUMBO_FRAME_SIZE 0x3F00
328#define E1000_TX_PTR_GAP 0x1F
329
330
331#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
332#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
333#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
334#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
335#define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
336#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
337#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
338#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
339#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
340
341#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
342#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
343#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
344#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
345
346#define E1000_KABGTXD_BGSQLBIAS 0x00050000
347
348
349#define E1000_LPIC_LPIET_SHIFT 24
350
351
352#define E1000_PBA_8K 0x0008
353#define E1000_PBA_16K 0x0010
354
355#define E1000_PBA_RXA_MASK 0xFFFF
356
357#define E1000_PBS_16K E1000_PBA_16K
358
359
360#define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF
361#define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00
362#define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8
363#define E1000_PBECCSTS_ECC_ENABLE 0x00010000
364
365#define IFS_MAX 80
366#define IFS_MIN 40
367#define IFS_RATIO 4
368#define IFS_STEP 10
369#define MIN_NUM_XMITS 1000
370
371
372#define E1000_SWSM_SMBI 0x00000001
373#define E1000_SWSM_SWESMBI 0x00000002
374#define E1000_SWSM_DRV_LOAD 0x00000008
375
376#define E1000_SWSM2_LOCK 0x00000002
377
378
379#define E1000_ICR_TXDW 0x00000001
380#define E1000_ICR_LSC 0x00000004
381#define E1000_ICR_RXSEQ 0x00000008
382#define E1000_ICR_RXDMT0 0x00000010
383#define E1000_ICR_RXO 0x00000040
384#define E1000_ICR_RXT0 0x00000080
385#define E1000_ICR_MDAC 0x00000200
386#define E1000_ICR_SRPD 0x00010000
387#define E1000_ICR_ACK 0x00020000
388#define E1000_ICR_MNG 0x00040000
389#define E1000_ICR_ECCER 0x00400000
390
391#define E1000_ICR_INT_ASSERTED 0x80000000
392#define E1000_ICR_RXQ0 0x00100000
393#define E1000_ICR_RXQ1 0x00200000
394#define E1000_ICR_TXQ0 0x00400000
395#define E1000_ICR_TXQ1 0x00800000
396#define E1000_ICR_OTHER 0x01000000
397
398
399#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000
400#define E1000_PBA_ECC_COUNTER_SHIFT 20
401#define E1000_PBA_ECC_CORR_EN 0x00000001
402#define E1000_PBA_ECC_STAT_CLR 0x00000002
403#define E1000_PBA_ECC_INT_EN 0x00000004
404
405
406
407
408
409
410
411
412
413#define IMS_ENABLE_MASK ( \
414 E1000_IMS_RXT0 | \
415 E1000_IMS_TXDW | \
416 E1000_IMS_RXDMT0 | \
417 E1000_IMS_RXSEQ | \
418 E1000_IMS_LSC)
419
420
421
422#define IMS_OTHER_MASK ( \
423 E1000_IMS_LSC | \
424 E1000_IMS_RXO | \
425 E1000_IMS_MDAC | \
426 E1000_IMS_SRPD | \
427 E1000_IMS_ACK | \
428 E1000_IMS_MNG)
429
430
431#define E1000_IMS_TXDW E1000_ICR_TXDW
432#define E1000_IMS_LSC E1000_ICR_LSC
433#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ
434#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0
435#define E1000_IMS_RXO E1000_ICR_RXO
436#define E1000_IMS_RXT0 E1000_ICR_RXT0
437#define E1000_IMS_MDAC E1000_ICR_MDAC
438#define E1000_IMS_SRPD E1000_ICR_SRPD
439#define E1000_IMS_ACK E1000_ICR_ACK
440#define E1000_IMS_MNG E1000_ICR_MNG
441#define E1000_IMS_ECCER E1000_ICR_ECCER
442#define E1000_IMS_RXQ0 E1000_ICR_RXQ0
443#define E1000_IMS_RXQ1 E1000_ICR_RXQ1
444#define E1000_IMS_TXQ0 E1000_ICR_TXQ0
445#define E1000_IMS_TXQ1 E1000_ICR_TXQ1
446#define E1000_IMS_OTHER E1000_ICR_OTHER
447
448
449#define E1000_ICS_LSC E1000_ICR_LSC
450#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ
451#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0
452#define E1000_ICS_OTHER E1000_ICR_OTHER
453
454
455#define E1000_TXDCTL_PTHRESH 0x0000003F
456#define E1000_TXDCTL_HTHRESH 0x00003F00
457#define E1000_TXDCTL_WTHRESH 0x003F0000
458#define E1000_TXDCTL_GRAN 0x01000000
459#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000
460#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F
461
462#define E1000_TXDCTL_COUNT_DESC 0x00400000
463
464
465#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
466#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
467#define FLOW_CONTROL_TYPE 0x8808
468
469
470#define E1000_VLAN_FILTER_TBL_SIZE 128
471
472
473
474
475
476
477
478
479#define E1000_RAR_ENTRIES 15
480#define E1000_RAH_AV 0x80000000
481#define E1000_RAL_MAC_ADDR_LEN 4
482#define E1000_RAH_MAC_ADDR_LEN 2
483
484
485#define E1000_ERR_NVM 1
486#define E1000_ERR_PHY 2
487#define E1000_ERR_CONFIG 3
488#define E1000_ERR_PARAM 4
489#define E1000_ERR_MAC_INIT 5
490#define E1000_ERR_PHY_TYPE 6
491#define E1000_ERR_RESET 9
492#define E1000_ERR_MASTER_REQUESTS_PENDING 10
493#define E1000_ERR_HOST_INTERFACE_COMMAND 11
494#define E1000_BLK_PHY_RESET 12
495#define E1000_ERR_SWFW_SYNC 13
496#define E1000_NOT_IMPLEMENTED 14
497#define E1000_ERR_INVALID_ARGUMENT 16
498#define E1000_ERR_NO_SPACE 17
499#define E1000_ERR_NVM_PBA_SECTION 18
500
501
502#define FIBER_LINK_UP_LIMIT 50
503#define COPPER_LINK_UP_LIMIT 10
504#define PHY_AUTO_NEG_LIMIT 45
505#define PHY_FORCE_LIMIT 20
506
507#define MASTER_DISABLE_TIMEOUT 800
508
509#define PHY_CFG_TIMEOUT 100
510
511#define MDIO_OWNERSHIP_TIMEOUT 10
512
513#define AUTO_READ_DONE_TIMEOUT 10
514
515
516#define E1000_FCRTH_RTH 0x0000FFF8
517#define E1000_FCRTL_RTL 0x0000FFF8
518#define E1000_FCRTL_XONE 0x80000000
519
520
521#define E1000_TXCW_FD 0x00000020
522#define E1000_TXCW_PAUSE 0x00000080
523#define E1000_TXCW_ASM_DIR 0x00000100
524#define E1000_TXCW_PAUSE_MASK 0x00000180
525#define E1000_TXCW_ANE 0x80000000
526
527
528#define E1000_RXCW_CW 0x0000ffff
529#define E1000_RXCW_IV 0x08000000
530#define E1000_RXCW_C 0x20000000
531#define E1000_RXCW_SYNCH 0x40000000
532
533
534#define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000
535#define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000
536#define E1000_TSYNCTXCTL_START_SYNC 0x80000000
537
538#define E1000_TSYNCTXCTL_VALID 0x00000001
539#define E1000_TSYNCTXCTL_ENABLED 0x00000010
540
541#define E1000_TSYNCRXCTL_VALID 0x00000001
542#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E
543#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
544#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
545#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
546#define E1000_TSYNCRXCTL_TYPE_ALL 0x08
547#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
548#define E1000_TSYNCRXCTL_ENABLED 0x00000010
549#define E1000_TSYNCRXCTL_SYSCFI 0x00000020
550
551#define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000
552#define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000
553
554#define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000
555#define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000
556
557#define E1000_TIMINCA_INCPERIOD_SHIFT 24
558#define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF
559
560
561#define E1000_GCR_RXD_NO_SNOOP 0x00000001
562#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
563#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
564#define E1000_GCR_TXD_NO_SNOOP 0x00000008
565#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
566#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
567
568#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
569 E1000_GCR_RXDSCW_NO_SNOOP | \
570 E1000_GCR_RXDSCR_NO_SNOOP | \
571 E1000_GCR_TXD_NO_SNOOP | \
572 E1000_GCR_TXDSCW_NO_SNOOP | \
573 E1000_GCR_TXDSCR_NO_SNOOP)
574
575
576#define E1000_EECD_SK 0x00000001
577#define E1000_EECD_CS 0x00000002
578#define E1000_EECD_DI 0x00000004
579#define E1000_EECD_DO 0x00000008
580#define E1000_EECD_REQ 0x00000040
581#define E1000_EECD_GNT 0x00000080
582#define E1000_EECD_PRES 0x00000100
583#define E1000_EECD_SIZE 0x00000200
584
585#define E1000_EECD_ADDR_BITS 0x00000400
586#define E1000_NVM_GRANT_ATTEMPTS 1000
587#define E1000_EECD_AUTO_RD 0x00000200
588#define E1000_EECD_SIZE_EX_MASK 0x00007800
589#define E1000_EECD_SIZE_EX_SHIFT 11
590#define E1000_EECD_FLUPD 0x00080000
591#define E1000_EECD_AUPDEN 0x00100000
592#define E1000_EECD_SEC1VAL 0x00400000
593#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
594
595#define E1000_NVM_RW_REG_DATA 16
596#define E1000_NVM_RW_REG_DONE 2
597#define E1000_NVM_RW_REG_START 1
598#define E1000_NVM_RW_ADDR_SHIFT 2
599#define E1000_NVM_POLL_WRITE 1
600#define E1000_NVM_POLL_READ 0
601#define E1000_FLASH_UPDATES 2000
602
603
604#define NVM_COMPAT 0x0003
605#define NVM_ID_LED_SETTINGS 0x0004
606#define NVM_FUTURE_INIT_WORD1 0x0019
607#define NVM_COMPAT_VALID_CSUM 0x0001
608#define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040
609
610#define NVM_INIT_CONTROL2_REG 0x000F
611#define NVM_INIT_CONTROL3_PORT_B 0x0014
612#define NVM_INIT_3GIO_3 0x001A
613#define NVM_INIT_CONTROL3_PORT_A 0x0024
614#define NVM_CFG 0x0012
615#define NVM_ALT_MAC_ADDR_PTR 0x0037
616#define NVM_CHECKSUM_REG 0x003F
617
618#define E1000_NVM_CFG_DONE_PORT_0 0x40000
619#define E1000_NVM_CFG_DONE_PORT_1 0x80000
620
621
622#define NVM_WORD0F_PAUSE_MASK 0x3000
623#define NVM_WORD0F_PAUSE 0x1000
624#define NVM_WORD0F_ASM_DIR 0x2000
625
626
627#define NVM_WORD1A_ASPM_MASK 0x000C
628
629
630#define NVM_COMPAT_LOM 0x0800
631
632
633#define E1000_PBANUM_LENGTH 11
634
635
636#define NVM_SUM 0xBABA
637
638
639#define NVM_PBA_OFFSET_0 8
640#define NVM_PBA_OFFSET_1 9
641#define NVM_PBA_PTR_GUARD 0xFAFA
642#define NVM_WORD_SIZE_BASE_SHIFT 6
643
644
645#define NVM_MAX_RETRY_SPI 5000
646#define NVM_READ_OPCODE_SPI 0x03
647#define NVM_WRITE_OPCODE_SPI 0x02
648#define NVM_A8_OPCODE_SPI 0x08
649#define NVM_WREN_OPCODE_SPI 0x06
650#define NVM_RDSR_OPCODE_SPI 0x05
651
652
653#define NVM_STATUS_RDY_SPI 0x01
654
655
656#define ID_LED_RESERVED_0000 0x0000
657#define ID_LED_RESERVED_FFFF 0xFFFF
658#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
659 (ID_LED_OFF1_OFF2 << 8) | \
660 (ID_LED_DEF1_DEF2 << 4) | \
661 (ID_LED_DEF1_DEF2))
662#define ID_LED_DEF1_DEF2 0x1
663#define ID_LED_DEF1_ON2 0x2
664#define ID_LED_DEF1_OFF2 0x3
665#define ID_LED_ON1_DEF2 0x4
666#define ID_LED_ON1_ON2 0x5
667#define ID_LED_ON1_OFF2 0x6
668#define ID_LED_OFF1_DEF2 0x7
669#define ID_LED_OFF1_ON2 0x8
670#define ID_LED_OFF1_OFF2 0x9
671
672#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
673#define IGP_ACTIVITY_LED_ENABLE 0x0300
674#define IGP_LED3_MODE 0x07000000
675
676
677#define PCI_HEADER_TYPE_REGISTER 0x0E
678#define PCIE_LINK_STATUS 0x12
679
680#define PCI_HEADER_TYPE_MULTIFUNC 0x80
681#define PCIE_LINK_WIDTH_MASK 0x3F0
682#define PCIE_LINK_WIDTH_SHIFT 4
683
684#define PHY_REVISION_MASK 0xFFFFFFF0
685#define MAX_PHY_REG_ADDRESS 0x1F
686#define MAX_PHY_MULTI_PAGE_REG 0xF
687
688
689
690
691
692#define M88E1000_E_PHY_ID 0x01410C50
693#define M88E1000_I_PHY_ID 0x01410C30
694#define M88E1011_I_PHY_ID 0x01410C20
695#define IGP01E1000_I_PHY_ID 0x02A80380
696#define M88E1111_I_PHY_ID 0x01410CC0
697#define GG82563_E_PHY_ID 0x01410CA0
698#define IGP03E1000_E_PHY_ID 0x02A80390
699#define IFE_E_PHY_ID 0x02A80330
700#define IFE_PLUS_E_PHY_ID 0x02A80320
701#define IFE_C_E_PHY_ID 0x02A80310
702#define BME1000_E_PHY_ID 0x01410CB0
703#define BME1000_E_PHY_ID_R2 0x01410CB1
704#define I82577_E_PHY_ID 0x01540050
705#define I82578_E_PHY_ID 0x004DD040
706#define I82579_E_PHY_ID 0x01540090
707#define I217_E_PHY_ID 0x015400A0
708
709
710#define M88E1000_PHY_SPEC_CTRL 0x10
711#define M88E1000_PHY_SPEC_STATUS 0x11
712#define M88E1000_EXT_PHY_SPEC_CTRL 0x14
713
714#define M88E1000_PHY_PAGE_SELECT 0x1D
715#define M88E1000_PHY_GEN_CONTROL 0x1E
716
717
718#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002
719#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
720
721#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020
722
723#define M88E1000_PSCR_AUTO_X_1000T 0x0040
724
725#define M88E1000_PSCR_AUTO_X_MODE 0x0060
726#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800
727
728
729#define M88E1000_PSSR_REV_POLARITY 0x0002
730#define M88E1000_PSSR_DOWNSHIFT 0x0020
731#define M88E1000_PSSR_MDIX 0x0040
732
733#define M88E1000_PSSR_CABLE_LENGTH 0x0380
734#define M88E1000_PSSR_SPEED 0xC000
735#define M88E1000_PSSR_1000MBS 0x8000
736
737#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
738
739
740
741
742#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
743#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
744
745
746
747#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
748#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
749#define M88E1000_EPSCR_TX_CLK_25 0x0070
750
751
752#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
753#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
754
755#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
756#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
757
758
759#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800
760
761
762
763
764
765#define GG82563_PAGE_SHIFT 5
766#define GG82563_REG(page, reg) \
767 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
768#define GG82563_MIN_ALT_REG 30
769
770
771#define GG82563_PHY_SPEC_CTRL \
772 GG82563_REG(0, 16)
773#define GG82563_PHY_PAGE_SELECT \
774 GG82563_REG(0, 22)
775#define GG82563_PHY_SPEC_CTRL_2 \
776 GG82563_REG(0, 26)
777#define GG82563_PHY_PAGE_SELECT_ALT \
778 GG82563_REG(0, 29)
779
780#define GG82563_PHY_MAC_SPEC_CTRL \
781 GG82563_REG(2, 21)
782
783#define GG82563_PHY_DSP_DISTANCE \
784 GG82563_REG(5, 26)
785
786
787#define GG82563_PHY_KMRN_MODE_CTRL \
788 GG82563_REG(193, 16)
789#define GG82563_PHY_PWR_MGMT_CTRL \
790 GG82563_REG(193, 20)
791
792
793#define GG82563_PHY_INBAND_CTRL \
794 GG82563_REG(194, 18)
795
796
797#define E1000_MDIC_REG_MASK 0x001F0000
798#define E1000_MDIC_REG_SHIFT 16
799#define E1000_MDIC_PHY_SHIFT 21
800#define E1000_MDIC_OP_WRITE 0x04000000
801#define E1000_MDIC_OP_READ 0x08000000
802#define E1000_MDIC_READY 0x10000000
803#define E1000_MDIC_ERROR 0x40000000
804
805
806#define E1000_GEN_POLL_TIMEOUT 640
807
808#endif
809