LXR linux/drivers/net/ethernet/stmicro/stmmac/dwmac100

   1/*******************************************************************************
   2  This is the driver for the MAC 10/100 on-chip Ethernet controller
   3  currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
   4
   5  DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
   6  this code.
   7
   8  This only implements the mac core functions for this chip.
   9
  10  Copyright (C) 2007-2009  STMicroelectronics Ltd
  11
  12  This program is free software; you can redistribute it and/or modify it
  13  under the terms and conditions of the GNU General Public License,
  14  version 2, as published by the Free Software Foundation.
  15
  16  This program is distributed in the hope it will be useful, but WITHOUT
  17  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  more details.
  20
  21  The full GNU General Public License is included in this distribution in
  22  the file called "COPYING".
  23
  24  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  25*******************************************************************************/
  26
  27#include <linux/crc32.h>
  28#include <net/dsa.h>
  29#include <asm/io.h>
  30#include "stmmac.h"
  31#include "dwmac100.h"
  32
  33static void dwmac100_core_init(struct mac_device_info *hw,
  34                               struct net_device *dev)
  35{
  36        void __iomem *ioaddr = hw->pcsr;
  37        u32 value = readl(ioaddr + MAC_CONTROL);
  38
  39        value |= MAC_CORE_INIT;
  40
  41        /* Clear ASTP bit because Ethernet switch tagging formats such as
  42         * Broadcom tags can look like invalid LLC/SNAP packets and cause the
  43         * hardware to truncate packets on reception.
  44         */
  45        if (netdev_uses_dsa(dev))
  46                value &= ~MAC_CONTROL_ASTP;
  47
  48        writel(value, ioaddr + MAC_CONTROL);
  49
  50#ifdef STMMAC_VLAN_TAG_USED
  51        writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
  52#endif
  53}
  54
  55static void dwmac100_dump_mac_regs(struct mac_device_info *hw, u32 *reg_space)
  56{
  57        void __iomem *ioaddr = hw->pcsr;
  58
  59        reg_space[MAC_CONTROL / 4] = readl(ioaddr + MAC_CONTROL);
  60        reg_space[MAC_ADDR_HIGH / 4] = readl(ioaddr + MAC_ADDR_HIGH);
  61        reg_space[MAC_ADDR_LOW / 4] = readl(ioaddr + MAC_ADDR_LOW);
  62        reg_space[MAC_HASH_HIGH / 4] = readl(ioaddr + MAC_HASH_HIGH);
  63        reg_space[MAC_HASH_LOW / 4] = readl(ioaddr + MAC_HASH_LOW);
  64        reg_space[MAC_FLOW_CTRL / 4] = readl(ioaddr + MAC_FLOW_CTRL);
  65        reg_space[MAC_VLAN1 / 4] = readl(ioaddr + MAC_VLAN1);
  66        reg_space[MAC_VLAN2 / 4] = readl(ioaddr + MAC_VLAN2);
  67}
  68
  69static int dwmac100_rx_ipc_enable(struct mac_device_info *hw)
  70{
  71        return 0;
  72}
  73
  74static int dwmac100_irq_status(struct mac_device_info *hw,
  75                               struct stmmac_extra_stats *x)
  76{
  77        return 0;
  78}
  79
  80static void dwmac100_set_umac_addr(struct mac_device_info *hw,
  81                                   unsigned char *addr,
  82                                   unsigned int reg_n)
  83{
  84        void __iomem *ioaddr = hw->pcsr;
  85        stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
  86}
  87
  88static void dwmac100_get_umac_addr(struct mac_device_info *hw,
  89                                   unsigned char *addr,
  90                                   unsigned int reg_n)
  91{
  92        void __iomem *ioaddr = hw->pcsr;
  93        stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
  94}
  95
  96static void dwmac100_set_filter(struct mac_device_info *hw,
  97                                struct net_device *dev)
  98{
  99        void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 100        u32 value = readl(ioaddr + MAC_CONTROL);
 101
 102        if (dev->flags & IFF_PROMISC) {
 103                value |= MAC_CONTROL_PR;
 104                value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
 105                           MAC_CONTROL_HP);
 106        } else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
 107                   || (dev->flags & IFF_ALLMULTI)) {
 108                value |= MAC_CONTROL_PM;
 109                value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
 110                writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
 111                writel(0xffffffff, ioaddr + MAC_HASH_LOW);
 112        } else if (netdev_mc_empty(dev)) {      /* no multicast */
 113                value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
 114                           MAC_CONTROL_HO | MAC_CONTROL_HP);
 115        } else {
 116                u32 mc_filter[2];
 117                struct netdev_hw_addr *ha;
 118
 119                /* Perfect filter mode for physical address and Hash
 120                 * filter for multicast
 121                 */
 122                value |= MAC_CONTROL_HP;
 123                value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
 124                           MAC_CONTROL_IF | MAC_CONTROL_HO);
 125
 126                memset(mc_filter, 0, sizeof(mc_filter));
 127                netdev_for_each_mc_addr(ha, dev) {
 128                        /* The upper 6 bits of the calculated CRC are used to
 129                         * index the contens of the hash table
 130                         */
 131                        int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
 132                        /* The most significant bit determines the register to
 133                         * use (H/L) while the other 5 bits determine the bit
 134                         * within the register.
 135                         */
 136                        mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 137                }
 138                writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
 139                writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
 140        }
 141
 142        writel(value, ioaddr + MAC_CONTROL);
 143}
 144
 145static void dwmac100_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 146                               unsigned int fc, unsigned int pause_time,
 147                               u32 tx_cnt)
 148{
 149        void __iomem *ioaddr = hw->pcsr;
 150        unsigned int flow = MAC_FLOW_CTRL_ENABLE;
 151
 152        if (duplex)
 153                flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
 154        writel(flow, ioaddr + MAC_FLOW_CTRL);
 155}
 156
 157/* No PMT module supported on ST boards with this Eth chip. */
 158static void dwmac100_pmt(struct mac_device_info *hw, unsigned long mode)
 159{
 160        return;
 161}
 162
 163const struct stmmac_ops dwmac100_ops = {
 164        .core_init = dwmac100_core_init,
 165        .set_mac = stmmac_set_mac,
 166        .rx_ipc = dwmac100_rx_ipc_enable,
 167        .dump_regs = dwmac100_dump_mac_regs,
 168        .host_irq_status = dwmac100_irq_status,
 169        .set_filter = dwmac100_set_filter,
 170        .flow_ctrl = dwmac100_flow_ctrl,
 171        .pmt = dwmac100_pmt,
 172        .set_umac_addr = dwmac100_set_umac_addr,
 173        .get_umac_addr = dwmac100_get_umac_addr,
 174};
 175
 176int dwmac100_setup(struct stmmac_priv *priv)
 177{
 178        struct mac_device_info *mac = priv->hw;
 179
 180        dev_info(priv->device, "\tDWMAC100\n");
 181
 182        mac->pcsr = priv->ioaddr;
 183        mac->link.duplex = MAC_CONTROL_F;
 184        mac->link.speed10 = 0;
 185        mac->link.speed100 = 0;
 186        mac->link.speed1000 = 0;
 187        mac->link.speed_mask = MAC_CONTROL_PS;
 188        mac->mii.addr = MAC_MII_ADDR;
 189        mac->mii.data = MAC_MII_DATA;
 190        mac->mii.addr_shift = 11;
 191        mac->mii.addr_mask = 0x0000F800;
 192        mac->mii.reg_shift = 6;
 193        mac->mii.reg_mask = 0x000007C0;
 194        mac->mii.clk_csr_shift = 2;
 195        mac->mii.clk_csr_mask = GENMASK(5, 2);
 196
 197        return 0;
 198}
 199