1/* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2016 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#ifndef __TARGADDRS_H__ 19#define __TARGADDRS_H__ 20 21#include "hw.h" 22 23/* 24 * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the 25 * host_interest structure. It must match the address of the _host_interest 26 * symbol (see linker script). 27 * 28 * Host Interest is shared between Host and Target in order to coordinate 29 * between the two, and is intended to remain constant (with additions only 30 * at the end) across software releases. 31 * 32 * All addresses are available here so that it's possible to 33 * write a single binary that works with all Target Types. 34 * May be used in assembler code as well as C. 35 */ 36#define QCA988X_HOST_INTEREST_ADDRESS 0x00400800 37#define HOST_INTEREST_MAX_SIZE 0x200 38 39/* 40 * These are items that the Host may need to access via BMI or via the 41 * Diagnostic Window. The position of items in this structure must remain 42 * constant across firmware revisions! Types for each item must be fixed 43 * size across target and host platforms. More items may be added at the end. 44 */ 45struct host_interest { 46 /* 47 * Pointer to application-defined area, if any. 48 * Set by Target application during startup. 49 */ 50 u32 hi_app_host_interest; /* 0x00 */ 51 52 /* Pointer to register dump area, valid after Target crash. */ 53 u32 hi_failure_state; /* 0x04 */ 54 55 /* Pointer to debug logging header */ 56 u32 hi_dbglog_hdr; /* 0x08 */ 57 58 u32 hi_unused0c; /* 0x0c */ 59 60 /* 61 * General-purpose flag bits, similar to SOC_OPTION_* flags. 62 * Can be used by application rather than by OS. 63 */ 64 u32 hi_option_flag; /* 0x10 */ 65 66 /* 67 * Boolean that determines whether or not to 68 * display messages on the serial port. 69 */ 70 u32 hi_serial_enable; /* 0x14 */ 71 72 /* Start address of DataSet index, if any */ 73 u32 hi_dset_list_head; /* 0x18 */ 74 75 /* Override Target application start address */ 76 u32 hi_app_start; /* 0x1c */ 77 78 /* Clock and voltage tuning */ 79 u32 hi_skip_clock_init; /* 0x20 */ 80 u32 hi_core_clock_setting; /* 0x24 */ 81 u32 hi_cpu_clock_setting; /* 0x28 */ 82 u32 hi_system_sleep_setting; /* 0x2c */ 83 u32 hi_xtal_control_setting; /* 0x30 */ 84 u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ 85 u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ 86 u32 hi_ref_voltage_trim_setting; /* 0x3c */ 87 u32 hi_clock_info; /* 0x40 */ 88 89 /* Host uses BE CPU or not */ 90 u32 hi_be; /* 0x44 */ 91 92 u32 hi_stack; /* normal stack */ /* 0x48 */ 93 u32 hi_err_stack; /* error stack */ /* 0x4c */ 94 u32 hi_desired_cpu_speed_hz; /* 0x50 */ 95 96 /* Pointer to Board Data */ 97 u32 hi_board_data; /* 0x54 */ 98 99 /* 100 * Indication of Board Data state: 101 * 0: board data is not yet initialized. 102 * 1: board data is initialized; unknown size 103 * >1: number of bytes of initialized board data 104 */ 105 u32 hi_board_data_initialized; /* 0x58 */ 106 107 u32 hi_dset_ram_index_table; /* 0x5c */ 108 109 u32 hi_desired_baud_rate; /* 0x60 */ 110 u32 hi_dbglog_config; /* 0x64 */ 111 u32 hi_end_ram_reserve_sz; /* 0x68 */ 112 u32 hi_mbox_io_block_sz; /* 0x6c */ 113 114 u32 hi_num_bpatch_streams; /* 0x70 -- unused */ 115 u32 hi_mbox_isr_yield_limit; /* 0x74 */ 116 117 u32 hi_refclk_hz; /* 0x78 */ 118 u32 hi_ext_clk_detected; /* 0x7c */ 119 u32 hi_dbg_uart_txpin; /* 0x80 */ 120 u32 hi_dbg_uart_rxpin; /* 0x84 */ 121 u32 hi_hci_uart_baud; /* 0x88 */ 122 u32 hi_hci_uart_pin_assignments; /* 0x8C */ 123 124 u32 hi_hci_uart_baud_scale_val; /* 0x90 */ 125 u32 hi_hci_uart_baud_step_val; /* 0x94 */ 126 127 u32 hi_allocram_start; /* 0x98 */ 128 u32 hi_allocram_sz; /* 0x9c */ 129 u32 hi_hci_bridge_flags; /* 0xa0 */ 130 u32 hi_hci_uart_support_pins; /* 0xa4 */ 131 132 u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ 133 134 /* 135 * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high 136 * [31:16]: wakeup timeout in ms 137 */ 138 /* Pointer to extended board Data */ 139 u32 hi_board_ext_data; /* 0xac */ 140 u32 hi_board_ext_data_config; /* 0xb0 */ 141 /* 142 * Bit [0] : valid 143 * Bit[31:16: size 144 */ 145 /* 146 * hi_reset_flag is used to do some stuff when target reset. 147 * such as restore app_start after warm reset or 148 * preserve host Interest area, or preserve ROM data, literals etc. 149 */ 150 u32 hi_reset_flag; /* 0xb4 */ 151 /* indicate hi_reset_flag is valid */ 152 u32 hi_reset_flag_valid; /* 0xb8 */ 153 u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */ 154 /* 0xbc - [31:0]: idle timeout in ms */ 155 /* ACS flags */ 156 u32 hi_acs_flags; /* 0xc0 */ 157 u32 hi_console_flags; /* 0xc4 */ 158 u32 hi_nvram_state; /* 0xc8 */ 159 u32 hi_option_flag2; /* 0xcc */ 160 161 /* If non-zero, override values sent to Host in WMI_READY event. */ 162 u32 hi_sw_version_override; /* 0xd0 */ 163 u32 hi_abi_version_override; /* 0xd4 */ 164 165 /* 166 * Percentage of high priority RX traffic to total expected RX traffic 167 * applicable only to ar6004 168 */ 169 u32 hi_hp_rx_traffic_ratio; /* 0xd8 */ 170 171 /* test applications flags */ 172 u32 hi_test_apps_related; /* 0xdc */ 173 /* location of test script */ 174 u32 hi_ota_testscript; /* 0xe0 */ 175 /* location of CAL data */ 176 u32 hi_cal_data; /* 0xe4 */ 177 178 /* Number of packet log buffers */ 179 u32 hi_pktlog_num_buffers; /* 0xe8 */ 180 181 /* wow extension configuration */ 182 u32 hi_wow_ext_config; /* 0xec */ 183 u32 hi_pwr_save_flags; /* 0xf0 */ 184 185 /* Spatial Multiplexing Power Save (SMPS) options */ 186 u32 hi_smps_options; /* 0xf4 */ 187 188 /* Interconnect-specific state */ 189 u32 hi_interconnect_state; /* 0xf8 */ 190 191 /* Coex configuration flags */ 192 u32 hi_coex_config; /* 0xfc */ 193 194 /* Early allocation support */ 195 u32 hi_early_alloc; /* 0x100 */ 196 /* FW swap field */ 197 /* 198 * Bits of this 32bit word will be used to pass specific swap 199 * instruction to FW 200 */ 201 /* 202 * Bit 0 -- AP Nart descriptor no swap. When this bit is set 203 * FW will not swap TX descriptor. Meaning packets are formed 204 * on the target processor. 205 */ 206 /* Bit 1 - unused */ 207 u32 hi_fw_swap; /* 0x104 */ 208 209 /* global arenas pointer address, used by host driver debug */ 210 u32 hi_dynamic_mem_arenas_addr; /* 0x108 */ 211 212 /* allocated bytes of DRAM use by allocated */ 213 u32 hi_dynamic_mem_allocated; /* 0x10C */ 214 215 /* remaining bytes of DRAM */ 216 u32 hi_dynamic_mem_remaining; /* 0x110 */ 217 218 /* memory track count, configured by host */ 219 u32 hi_dynamic_mem_track_max; /* 0x114 */ 220 221 /* minidump buffer */ 222 u32 hi_minidump; /* 0x118 */ 223 224 /* bdata's sig and key addr */ 225 u32 hi_bd_sig_key; /* 0x11c */ 226} __packed; 227 228#define HI_ITEM(item) offsetof(struct host_interest, item) 229 230/* Bits defined in hi_option_flag */ 231 232/* Enable timer workaround */ 233#define HI_OPTION_TIMER_WAR 0x01 234/* Limit BMI command credits */ 235#define HI_OPTION_BMI_CRED_LIMIT 0x02 236/* Relay Dot11 hdr to/from host */ 237#define HI_OPTION_RELAY_DOT11_HDR 0x04 238/* MAC addr method 0-locally administred 1-globally unique addrs */ 239#define HI_OPTION_MAC_ADDR_METHOD 0x08 240/* Firmware Bridging */ 241#define HI_OPTION_FW_BRIDGE 0x10 242/* Enable CPU profiling */ 243#define HI_OPTION_ENABLE_PROFILE 0x20 244/* Disable debug logging */ 245#define HI_OPTION_DISABLE_DBGLOG 0x40 246/* Skip Era Tracking */ 247#define HI_OPTION_SKIP_ERA_TRACKING 0x80 248/* Disable PAPRD (debug) */ 249#define HI_OPTION_PAPRD_DISABLE 0x100 250#define HI_OPTION_NUM_DEV_LSB 0x200 251#define HI_OPTION_NUM_DEV_MSB 0x800 252#define HI_OPTION_DEV_MODE_LSB 0x1000 253#define HI_OPTION_DEV_MODE_MSB 0x8000000 254/* Disable LowFreq Timer Stabilization */ 255#define HI_OPTION_NO_LFT_STBL 0x10000000 256/* Skip regulatory scan */ 257#define HI_OPTION_SKIP_REG_SCAN 0x20000000 258/* 259 * Do regulatory scan during init before 260 * sending WMI ready event to host 261 */ 262#define HI_OPTION_INIT_REG_SCAN 0x40000000 263 264/* REV6: Do not adjust memory map */ 265#define HI_OPTION_SKIP_MEMMAP 0x80000000 266 267#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3 268 269/* 2 bits of hi_option_flag are used to represent 3 modes */ 270#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ 271#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ 272#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ 273#define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */ 274 275/* 2 bits of hi_option flag are usedto represent 4 submodes */ 276#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */ 277#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */ 278#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */ 279#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */ 280 281/* Num dev Mask */ 282#define HI_OPTION_NUM_DEV_MASK 0x7 283#define HI_OPTION_NUM_DEV_SHIFT 0x9 284 285/* firmware bridging */ 286#define HI_OPTION_FW_BRIDGE_SHIFT 0x04 287 288/* 289 * Fw Mode/SubMode Mask 290 *----------------------------------------------------------------------------- 291 * SUB | SUB | SUB | SUB | | | | 292 *MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] 293 * (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) 294 *----------------------------------------------------------------------------- 295 */ 296#define HI_OPTION_FW_MODE_BITS 0x2 297#define HI_OPTION_FW_MODE_MASK 0x3 298#define HI_OPTION_FW_MODE_SHIFT 0xC 299#define HI_OPTION_ALL_FW_MODE_MASK 0xFF 300 301#define HI_OPTION_FW_SUBMODE_BITS 0x2 302#define HI_OPTION_FW_SUBMODE_MASK 0x3 303#define HI_OPTION_FW_SUBMODE_SHIFT 0x14 304#define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00 305#define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8 306 307/* hi_option_flag2 options */ 308#define HI_OPTION_OFFLOAD_AMSDU 0x01 309#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */ 310#define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature*/ 311#define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */ 312#define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */ 313 314#define HI_OPTION_RF_KILL_SHIFT 0x2 315#define HI_OPTION_RF_KILL_MASK 0x1 316 317/* hi_reset_flag */ 318/* preserve App Start address */ 319#define HI_RESET_FLAG_PRESERVE_APP_START 0x01 320/* preserve host interest */ 321#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 322/* preserve ROM data */ 323#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 324#define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08 325#define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10 326#define HI_RESET_FLAG_WARM_RESET 0x20 327 328/* define hi_fw_swap bits */ 329#define HI_DESC_IN_FW_BIT 0x01 330 331/* indicate the reset flag is valid */ 332#define HI_RESET_FLAG_IS_VALID 0x12345678 333 334/* ACS is enabled */ 335#define HI_ACS_FLAGS_ENABLED (1 << 0) 336/* Use physical WWAN device */ 337#define HI_ACS_FLAGS_USE_WWAN (1 << 1) 338/* Use test VAP */ 339#define HI_ACS_FLAGS_TEST_VAP (1 << 2) 340/* SDIO/mailbox ACS flag definitions */ 341#define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET (1 << 0) 342#define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET (1 << 1) 343#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2) 344#define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_FW_ACK (1 << 16) 345#define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_FW_ACK (1 << 17) 346 347/* 348 * CONSOLE FLAGS 349 * 350 * Bit Range Meaning 351 * --------- -------------------------------- 352 * 2..0 UART ID (0 = Default) 353 * 3 Baud Select (0 = 9600, 1 = 115200) 354 * 30..4 Reserved 355 * 31 Enable Console 356 * 357 */ 358 359#define HI_CONSOLE_FLAGS_ENABLE (1 << 31) 360#define HI_CONSOLE_FLAGS_UART_MASK (0x7) 361#define HI_CONSOLE_FLAGS_UART_SHIFT 0 362#define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3) 363 364/* SM power save options */ 365#define HI_SMPS_ALLOW_MASK (0x00000001) 366#define HI_SMPS_MODE_MASK (0x00000002) 367#define HI_SMPS_MODE_STATIC (0x00000000) 368#define HI_SMPS_MODE_DYNAMIC (0x00000002) 369#define HI_SMPS_DISABLE_AUTO_MODE (0x00000004) 370#define HI_SMPS_DATA_THRESH_MASK (0x000007f8) 371#define HI_SMPS_DATA_THRESH_SHIFT (3) 372#define HI_SMPS_RSSI_THRESH_MASK (0x0007f800) 373#define HI_SMPS_RSSI_THRESH_SHIFT (11) 374#define HI_SMPS_LOWPWR_CM_MASK (0x00380000) 375#define HI_SMPS_LOWPWR_CM_SHIFT (15) 376#define HI_SMPS_HIPWR_CM_MASK (0x03c00000) 377#define HI_SMPS_HIPWR_CM_SHIFT (19) 378 379/* 380 * WOW Extension configuration 381 * 382 * Bit Range Meaning 383 * --------- -------------------------------- 384 * 8..0 Size of each WOW pattern (max 511) 385 * 15..9 Number of patterns per list (max 127) 386 * 17..16 Number of lists (max 4) 387 * 30..18 Reserved 388 * 31 Enabled 389 * 390 * set values (except enable) to zeros for default settings 391 */ 392 393#define HI_WOW_EXT_ENABLED_MASK (1 << 31) 394#define HI_WOW_EXT_NUM_LIST_SHIFT 16 395#define HI_WOW_EXT_NUM_LIST_MASK (0x3 << HI_WOW_EXT_NUM_LIST_SHIFT) 396#define HI_WOW_EXT_NUM_PATTERNS_SHIFT 9 397#define HI_WOW_EXT_NUM_PATTERNS_MASK (0x7F << HI_WOW_EXT_NUM_PATTERNS_SHIFT) 398#define HI_WOW_EXT_PATTERN_SIZE_SHIFT 0 399#define HI_WOW_EXT_PATTERN_SIZE_MASK (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT) 400 401#define HI_WOW_EXT_MAKE_CONFIG(num_lists, count, size) \ 402 ((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & \ 403 HI_WOW_EXT_NUM_LIST_MASK) | \ 404 (((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & \ 405 HI_WOW_EXT_NUM_PATTERNS_MASK) | \ 406 (((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & \ 407 HI_WOW_EXT_PATTERN_SIZE_MASK)) 408 409#define HI_WOW_EXT_GET_NUM_LISTS(config) \ 410 (((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT) 411#define HI_WOW_EXT_GET_NUM_PATTERNS(config) \ 412 (((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> \ 413 HI_WOW_EXT_NUM_PATTERNS_SHIFT) 414#define HI_WOW_EXT_GET_PATTERN_SIZE(config) \ 415 (((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> \ 416 HI_WOW_EXT_PATTERN_SIZE_SHIFT) 417 418/* 419 * Early allocation configuration 420 * Support RAM bank configuration before BMI done and this eases the memory 421 * allocation at very early stage 422 * Bit Range Meaning 423 * --------- ---------------------------------- 424 * [0:3] number of bank assigned to be IRAM 425 * [4:15] reserved 426 * [16:31] magic number 427 * 428 * Note: 429 * 1. target firmware would check magic number and if it's a match, firmware 430 * would consider the bits[0:15] are valid and base on that to calculate 431 * the end of DRAM. Early allocation would be located at that area and 432 * may be reclaimed when necessary 433 * 2. if no magic number is found, early allocation would happen at "_end" 434 * symbol of ROM which is located before the app-data and might NOT be 435 * re-claimable. If this is adopted, link script should keep this in 436 * mind to avoid data corruption. 437 */ 438#define HI_EARLY_ALLOC_MAGIC 0x6d8a 439#define HI_EARLY_ALLOC_MAGIC_MASK 0xffff0000 440#define HI_EARLY_ALLOC_MAGIC_SHIFT 16 441#define HI_EARLY_ALLOC_IRAM_BANKS_MASK 0x0000000f 442#define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT 0 443 444#define HI_EARLY_ALLOC_VALID() \ 445 ((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> \ 446 HI_EARLY_ALLOC_MAGIC_SHIFT) == (HI_EARLY_ALLOC_MAGIC)) 447#define HI_EARLY_ALLOC_GET_IRAM_BANKS() \ 448 (((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) \ 449 >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) 450 451/*power save flag bit definitions*/ 452#define HI_PWR_SAVE_LPL_ENABLED 0x1 453/*b1-b3 reserved*/ 454/*b4-b5 : dev0 LPL type : 0 - none 455 * 1- Reduce Pwr Search 456 * 2- Reduce Pwr Listen 457 */ 458/*b6-b7 : dev1 LPL type and so on for Max 8 devices*/ 459#define HI_PWR_SAVE_LPL_DEV0_LSB 4 460#define HI_PWR_SAVE_LPL_DEV_MASK 0x3 461/*power save related utility macros*/ 462#define HI_LPL_ENABLED() \ 463 ((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED)) 464#define HI_DEV_LPL_TYPE_GET(_devix) \ 465 (HOST_INTEREST->hi_pwr_save_flags & ((HI_PWR_SAVE_LPL_DEV_MASK) << \ 466 (HI_PWR_SAVE_LPL_DEV0_LSB + (_devix) * 2))) 467 468#define HOST_INTEREST_SMPS_IS_ALLOWED() \ 469 ((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK)) 470 471/* Reserve 1024 bytes for extended board data */ 472#define QCA988X_BOARD_DATA_SZ 7168 473#define QCA988X_BOARD_EXT_DATA_SZ 0 474 475#define QCA9887_BOARD_DATA_SZ 7168 476#define QCA9887_BOARD_EXT_DATA_SZ 0 477 478#define QCA6174_BOARD_DATA_SZ 8192 479#define QCA6174_BOARD_EXT_DATA_SZ 0 480 481#define QCA9377_BOARD_DATA_SZ QCA6174_BOARD_DATA_SZ 482#define QCA9377_BOARD_EXT_DATA_SZ 0 483 484#define QCA99X0_BOARD_DATA_SZ 12288 485#define QCA99X0_BOARD_EXT_DATA_SZ 0 486 487#define QCA4019_BOARD_DATA_SZ 12064 488#define QCA4019_BOARD_EXT_DATA_SZ 0 489 490#endif /* __TARGADDRS_H__ */ 491