LXR linux/drivers/net/wireless/zydas/zd1211rw/zd_rf

   1/* ZD1211 USB-WLAN driver for Linux
   2 *
   3 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
   4 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#include <linux/kernel.h>
  21#include <linux/slab.h>
  22
  23#include "zd_rf.h"
  24#include "zd_usb.h"
  25#include "zd_chip.h"
  26
  27/* This RF programming code is based upon the code found in v2.16.0.0 of the
  28 * ZyDAS vendor driver. Unlike other RF's, Ubec publish full technical specs
  29 * for this RF on their website, so we're able to understand more than
  30 * usual as to what is going on. Thumbs up for Ubec for doing that. */
  31
  32/* The 3-wire serial interface provides access to 8 write-only registers.
  33 * The data format is a 4 bit register address followed by a 20 bit value. */
  34#define UW2453_REGWRITE(reg, val) ((((reg) & 0xf) << 20) | ((val) & 0xfffff))
  35
  36/* For channel tuning, we have to configure registers 1 (synthesizer), 2 (synth
  37 * fractional divide ratio) and 3 (VCO config).
  38 *
  39 * We configure the RF to produce an interrupt when the PLL is locked onto
  40 * the configured frequency. During initialization, we run through a variety
  41 * of different VCO configurations on channel 1 until we detect a PLL lock.
  42 * When this happens, we remember which VCO configuration produced the lock
  43 * and use it later. Actually, we use the configuration *after* the one that
  44 * produced the lock, which seems odd, but it works.
  45 *
  46 * If we do not see a PLL lock on any standard VCO config, we fall back on an
  47 * autocal configuration, which has a fixed (as opposed to per-channel) VCO
  48 * config and different synth values from the standard set (divide ratio
  49 * is still shared with the standard set). */
  50
  51/* The per-channel synth values for all standard VCO configurations. These get
  52 * written to register 1. */
  53static const u8 uw2453_std_synth[] = {
  54        RF_CHANNEL( 1) = 0x47,
  55        RF_CHANNEL( 2) = 0x47,
  56        RF_CHANNEL( 3) = 0x67,
  57        RF_CHANNEL( 4) = 0x67,
  58        RF_CHANNEL( 5) = 0x67,
  59        RF_CHANNEL( 6) = 0x67,
  60        RF_CHANNEL( 7) = 0x57,
  61        RF_CHANNEL( 8) = 0x57,
  62        RF_CHANNEL( 9) = 0x57,
  63        RF_CHANNEL(10) = 0x57,
  64        RF_CHANNEL(11) = 0x77,
  65        RF_CHANNEL(12) = 0x77,
  66        RF_CHANNEL(13) = 0x77,
  67        RF_CHANNEL(14) = 0x4f,
  68};
  69
  70/* This table stores the synthesizer fractional divide ratio for *all* VCO
  71 * configurations (both standard and autocal). These get written to register 2.
  72 */
  73static const u16 uw2453_synth_divide[] = {
  74        RF_CHANNEL( 1) = 0x999,
  75        RF_CHANNEL( 2) = 0x99b,
  76        RF_CHANNEL( 3) = 0x998,
  77        RF_CHANNEL( 4) = 0x99a,
  78        RF_CHANNEL( 5) = 0x999,
  79        RF_CHANNEL( 6) = 0x99b,
  80        RF_CHANNEL( 7) = 0x998,
  81        RF_CHANNEL( 8) = 0x99a,
  82        RF_CHANNEL( 9) = 0x999,
  83        RF_CHANNEL(10) = 0x99b,
  84        RF_CHANNEL(11) = 0x998,
  85        RF_CHANNEL(12) = 0x99a,
  86        RF_CHANNEL(13) = 0x999,
  87        RF_CHANNEL(14) = 0xccc,
  88};
  89
  90/* Here is the data for all the standard VCO configurations. We shrink our
  91 * table a little by observing that both channels in a consecutive pair share
  92 * the same value. We also observe that the high 4 bits ([0:3] in the specs)
  93 * are all 'Reserved' and are always set to 0x4 - we chop them off in the data
  94 * below. */
  95#define CHAN_TO_PAIRIDX(a) ((a - 1) / 2)
  96#define RF_CHANPAIR(a,b) [CHAN_TO_PAIRIDX(a)]
  97static const u16 uw2453_std_vco_cfg[][7] = {
  98        { /* table 1 */
  99                RF_CHANPAIR( 1,  2) = 0x664d,
 100                RF_CHANPAIR( 3,  4) = 0x604d,
 101                RF_CHANPAIR( 5,  6) = 0x6675,
 102                RF_CHANPAIR( 7,  8) = 0x6475,
 103                RF_CHANPAIR( 9, 10) = 0x6655,
 104                RF_CHANPAIR(11, 12) = 0x6455,
 105                RF_CHANPAIR(13, 14) = 0x6665,
 106        },
 107        { /* table 2 */
 108                RF_CHANPAIR( 1,  2) = 0x666d,
 109                RF_CHANPAIR( 3,  4) = 0x606d,
 110                RF_CHANPAIR( 5,  6) = 0x664d,
 111                RF_CHANPAIR( 7,  8) = 0x644d,
 112                RF_CHANPAIR( 9, 10) = 0x6675,
 113                RF_CHANPAIR(11, 12) = 0x6475,
 114                RF_CHANPAIR(13, 14) = 0x6655,
 115        },
 116        { /* table 3 */
 117                RF_CHANPAIR( 1,  2) = 0x665d,
 118                RF_CHANPAIR( 3,  4) = 0x605d,
 119                RF_CHANPAIR( 5,  6) = 0x666d,
 120                RF_CHANPAIR( 7,  8) = 0x646d,
 121                RF_CHANPAIR( 9, 10) = 0x664d,
 122                RF_CHANPAIR(11, 12) = 0x644d,
 123                RF_CHANPAIR(13, 14) = 0x6675,
 124        },
 125        { /* table 4 */
 126                RF_CHANPAIR( 1,  2) = 0x667d,
 127                RF_CHANPAIR( 3,  4) = 0x607d,
 128                RF_CHANPAIR( 5,  6) = 0x665d,
 129                RF_CHANPAIR( 7,  8) = 0x645d,
 130                RF_CHANPAIR( 9, 10) = 0x666d,
 131                RF_CHANPAIR(11, 12) = 0x646d,
 132                RF_CHANPAIR(13, 14) = 0x664d,
 133        },
 134        { /* table 5 */
 135                RF_CHANPAIR( 1,  2) = 0x6643,
 136                RF_CHANPAIR( 3,  4) = 0x6043,
 137                RF_CHANPAIR( 5,  6) = 0x667d,
 138                RF_CHANPAIR( 7,  8) = 0x647d,
 139                RF_CHANPAIR( 9, 10) = 0x665d,
 140                RF_CHANPAIR(11, 12) = 0x645d,
 141                RF_CHANPAIR(13, 14) = 0x666d,
 142        },
 143        { /* table 6 */
 144                RF_CHANPAIR( 1,  2) = 0x6663,
 145                RF_CHANPAIR( 3,  4) = 0x6063,
 146                RF_CHANPAIR( 5,  6) = 0x6643,
 147                RF_CHANPAIR( 7,  8) = 0x6443,
 148                RF_CHANPAIR( 9, 10) = 0x667d,
 149                RF_CHANPAIR(11, 12) = 0x647d,
 150                RF_CHANPAIR(13, 14) = 0x665d,
 151        },
 152        { /* table 7 */
 153                RF_CHANPAIR( 1,  2) = 0x6653,
 154                RF_CHANPAIR( 3,  4) = 0x6053,
 155                RF_CHANPAIR( 5,  6) = 0x6663,
 156                RF_CHANPAIR( 7,  8) = 0x6463,
 157                RF_CHANPAIR( 9, 10) = 0x6643,
 158                RF_CHANPAIR(11, 12) = 0x6443,
 159                RF_CHANPAIR(13, 14) = 0x667d,
 160        },
 161        { /* table 8 */
 162                RF_CHANPAIR( 1,  2) = 0x6673,
 163                RF_CHANPAIR( 3,  4) = 0x6073,
 164                RF_CHANPAIR( 5,  6) = 0x6653,
 165                RF_CHANPAIR( 7,  8) = 0x6453,
 166                RF_CHANPAIR( 9, 10) = 0x6663,
 167                RF_CHANPAIR(11, 12) = 0x6463,
 168                RF_CHANPAIR(13, 14) = 0x6643,
 169        },
 170        { /* table 9 */
 171                RF_CHANPAIR( 1,  2) = 0x664b,
 172                RF_CHANPAIR( 3,  4) = 0x604b,
 173                RF_CHANPAIR( 5,  6) = 0x6673,
 174                RF_CHANPAIR( 7,  8) = 0x6473,
 175                RF_CHANPAIR( 9, 10) = 0x6653,
 176                RF_CHANPAIR(11, 12) = 0x6453,
 177                RF_CHANPAIR(13, 14) = 0x6663,
 178        },
 179        { /* table 10 */
 180                RF_CHANPAIR( 1,  2) = 0x666b,
 181                RF_CHANPAIR( 3,  4) = 0x606b,
 182                RF_CHANPAIR( 5,  6) = 0x664b,
 183                RF_CHANPAIR( 7,  8) = 0x644b,
 184                RF_CHANPAIR( 9, 10) = 0x6673,
 185                RF_CHANPAIR(11, 12) = 0x6473,
 186                RF_CHANPAIR(13, 14) = 0x6653,
 187        },
 188        { /* table 11 */
 189                RF_CHANPAIR( 1,  2) = 0x665b,
 190                RF_CHANPAIR( 3,  4) = 0x605b,
 191                RF_CHANPAIR( 5,  6) = 0x666b,
 192                RF_CHANPAIR( 7,  8) = 0x646b,
 193                RF_CHANPAIR( 9, 10) = 0x664b,
 194                RF_CHANPAIR(11, 12) = 0x644b,
 195                RF_CHANPAIR(13, 14) = 0x6673,
 196        },
 197
 198};
 199
 200/* The per-channel synth values for autocal. These get written to register 1. */
 201static const u16 uw2453_autocal_synth[] = {
 202        RF_CHANNEL( 1) = 0x6847,
 203        RF_CHANNEL( 2) = 0x6847,
 204        RF_CHANNEL( 3) = 0x6867,
 205        RF_CHANNEL( 4) = 0x6867,
 206        RF_CHANNEL( 5) = 0x6867,
 207        RF_CHANNEL( 6) = 0x6867,
 208        RF_CHANNEL( 7) = 0x6857,
 209        RF_CHANNEL( 8) = 0x6857,
 210        RF_CHANNEL( 9) = 0x6857,
 211        RF_CHANNEL(10) = 0x6857,
 212        RF_CHANNEL(11) = 0x6877,
 213        RF_CHANNEL(12) = 0x6877,
 214        RF_CHANNEL(13) = 0x6877,
 215        RF_CHANNEL(14) = 0x684f,
 216};
 217
 218/* The VCO configuration for autocal (all channels) */
 219static const u16 UW2453_AUTOCAL_VCO_CFG = 0x6662;
 220
 221/* TX gain settings. The array index corresponds to the TX power integration
 222 * values found in the EEPROM. The values get written to register 7. */
 223static u32 uw2453_txgain[] = {
 224        [0x00] = 0x0e313,
 225        [0x01] = 0x0fb13,
 226        [0x02] = 0x0e093,
 227        [0x03] = 0x0f893,
 228        [0x04] = 0x0ea93,
 229        [0x05] = 0x1f093,
 230        [0x06] = 0x1f493,
 231        [0x07] = 0x1f693,
 232        [0x08] = 0x1f393,
 233        [0x09] = 0x1f35b,
 234        [0x0a] = 0x1e6db,
 235        [0x0b] = 0x1ff3f,
 236        [0x0c] = 0x1ffff,
 237        [0x0d] = 0x361d7,
 238        [0x0e] = 0x37fbf,
 239        [0x0f] = 0x3ff8b,
 240        [0x10] = 0x3ff33,
 241        [0x11] = 0x3fb3f,
 242        [0x12] = 0x3ffff,
 243};
 244
 245/* RF-specific structure */
 246struct uw2453_priv {
 247        /* index into synth/VCO config tables where PLL lock was found
 248         * -1 means autocal */
 249        int config;
 250};
 251
 252#define UW2453_PRIV(rf) ((struct uw2453_priv *) (rf)->priv)
 253
 254static int uw2453_synth_set_channel(struct zd_chip *chip, int channel,
 255        bool autocal)
 256{
 257        int r;
 258        int idx = channel - 1;
 259        u32 val;
 260
 261        if (autocal)
 262                val = UW2453_REGWRITE(1, uw2453_autocal_synth[idx]);
 263        else
 264                val = UW2453_REGWRITE(1, uw2453_std_synth[idx]);
 265
 266        r = zd_rfwrite_locked(chip, val, RF_RV_BITS);
 267        if (r)
 268                return r;
 269
 270        return zd_rfwrite_locked(chip,
 271                UW2453_REGWRITE(2, uw2453_synth_divide[idx]), RF_RV_BITS);
 272}
 273
 274static int uw2453_write_vco_cfg(struct zd_chip *chip, u16 value)
 275{
 276        /* vendor driver always sets these upper bits even though the specs say
 277         * they are reserved */
 278        u32 val = 0x40000 | value;
 279        return zd_rfwrite_locked(chip, UW2453_REGWRITE(3, val), RF_RV_BITS);
 280}
 281
 282static int uw2453_init_mode(struct zd_chip *chip)
 283{
 284        static const u32 rv[] = {
 285                UW2453_REGWRITE(0, 0x25f98), /* enter IDLE mode */
 286                UW2453_REGWRITE(0, 0x25f9a), /* enter CAL_VCO mode */
 287                UW2453_REGWRITE(0, 0x25f94), /* enter RX/TX mode */
 288                UW2453_REGWRITE(0, 0x27fd4), /* power down RSSI circuit */
 289        };
 290
 291        return zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
 292}
 293
 294static int uw2453_set_tx_gain_level(struct zd_chip *chip, int channel)
 295{
 296        u8 int_value = chip->pwr_int_values[channel - 1];
 297
 298        if (int_value >= ARRAY_SIZE(uw2453_txgain)) {
 299                dev_dbg_f(zd_chip_dev(chip), "can't configure TX gain for "
 300                          "int value %x on channel %d\n", int_value, channel);
 301                return 0;
 302        }
 303
 304        return zd_rfwrite_locked(chip,
 305                UW2453_REGWRITE(7, uw2453_txgain[int_value]), RF_RV_BITS);
 306}
 307
 308static int uw2453_init_hw(struct zd_rf *rf)
 309{
 310        int i, r;
 311        int found_config = -1;
 312        u16 intr_status;
 313        struct zd_chip *chip = zd_rf_to_chip(rf);
 314
 315        static const struct zd_ioreq16 ioreqs[] = {
 316                { ZD_CR10,  0x89 }, { ZD_CR15,  0x20 },
 317                { ZD_CR17,  0x28 }, /* 6112 no change */
 318                { ZD_CR23,  0x38 }, { ZD_CR24,  0x20 }, { ZD_CR26,  0x93 },
 319                { ZD_CR27,  0x15 }, { ZD_CR28,  0x3e }, { ZD_CR29,  0x00 },
 320                { ZD_CR33,  0x28 }, { ZD_CR34,  0x30 },
 321                { ZD_CR35,  0x43 }, /* 6112 3e->43 */
 322                { ZD_CR41,  0x24 }, { ZD_CR44,  0x32 },
 323                { ZD_CR46,  0x92 }, /* 6112 96->92 */
 324                { ZD_CR47,  0x1e },
 325                { ZD_CR48,  0x04 }, /* 5602 Roger */
 326                { ZD_CR49,  0xfa }, { ZD_CR79,  0x58 }, { ZD_CR80,  0x30 },
 327                { ZD_CR81,  0x30 }, { ZD_CR87,  0x0a }, { ZD_CR89,  0x04 },
 328                { ZD_CR91,  0x00 }, { ZD_CR92,  0x0a }, { ZD_CR98,  0x8d },
 329                { ZD_CR99,  0x28 }, { ZD_CR100, 0x02 },
 330                { ZD_CR101, 0x09 }, /* 6112 13->1f 6220 1f->13 6407 13->9 */
 331                { ZD_CR102, 0x27 },
 332                { ZD_CR106, 0x1c }, /* 5d07 5112 1f->1c 6220 1c->1f
 333                                     * 6221 1f->1c
 334                                     */
 335                { ZD_CR107, 0x1c }, /* 6220 1c->1a 5221 1a->1c */
 336                { ZD_CR109, 0x13 },
 337                { ZD_CR110, 0x1f }, /* 6112 13->1f 6221 1f->13 6407 13->0x09 */
 338                { ZD_CR111, 0x13 }, { ZD_CR112, 0x1f }, { ZD_CR113, 0x27 },
 339                { ZD_CR114, 0x23 }, /* 6221 27->23 */
 340                { ZD_CR115, 0x24 }, /* 6112 24->1c 6220 1c->24 */
 341                { ZD_CR116, 0x24 }, /* 6220 1c->24 */
 342                { ZD_CR117, 0xfa }, /* 6112 fa->f8 6220 f8->f4 6220 f4->fa */
 343                { ZD_CR118, 0xf0 }, /* 5d07 6112 f0->f2 6220 f2->f0 */
 344                { ZD_CR119, 0x1a }, /* 6112 1a->10 6220 10->14 6220 14->1a */
 345                { ZD_CR120, 0x4f },
 346                { ZD_CR121, 0x1f }, /* 6220 4f->1f */
 347                { ZD_CR122, 0xf0 }, { ZD_CR123, 0x57 }, { ZD_CR125, 0xad },
 348                { ZD_CR126, 0x6c }, { ZD_CR127, 0x03 },
 349                { ZD_CR128, 0x14 }, /* 6302 12->11 */
 350                { ZD_CR129, 0x12 }, /* 6301 10->0f */
 351                { ZD_CR130, 0x10 }, { ZD_CR137, 0x50 }, { ZD_CR138, 0xa8 },
 352                { ZD_CR144, 0xac }, { ZD_CR146, 0x20 }, { ZD_CR252, 0xff },
 353                { ZD_CR253, 0xff },
 354        };
 355
 356        static const u32 rv[] = {
 357                UW2453_REGWRITE(4, 0x2b),    /* configure receiver gain */
 358                UW2453_REGWRITE(5, 0x19e4f), /* configure transmitter gain */
 359                UW2453_REGWRITE(6, 0xf81ad), /* enable RX/TX filter tuning */
 360                UW2453_REGWRITE(7, 0x3fffe), /* disable TX gain in test mode */
 361
 362                /* enter CAL_FIL mode, TX gain set by registers, RX gain set by pins,
 363                 * RSSI circuit powered down, reduced RSSI range */
 364                UW2453_REGWRITE(0, 0x25f9c), /* 5d01 cal_fil */
 365
 366                /* synthesizer configuration for channel 1 */
 367                UW2453_REGWRITE(1, 0x47),
 368                UW2453_REGWRITE(2, 0x999),
 369
 370                /* disable manual VCO band selection */
 371                UW2453_REGWRITE(3, 0x7602),
 372
 373                /* enable manual VCO band selection, configure current level */
 374                UW2453_REGWRITE(3, 0x46063),
 375        };
 376
 377        r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 378        if (r)
 379                return r;
 380
 381        r = zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
 382        if (r)
 383                return r;
 384
 385        r = uw2453_init_mode(chip);
 386        if (r)
 387                return r;
 388
 389        /* Try all standard VCO configuration settings on channel 1 */
 390        for (i = 0; i < ARRAY_SIZE(uw2453_std_vco_cfg) - 1; i++) {
 391                /* Configure synthesizer for channel 1 */
 392                r = uw2453_synth_set_channel(chip, 1, false);
 393                if (r)
 394                        return r;
 395
 396                /* Write VCO config */
 397                r = uw2453_write_vco_cfg(chip, uw2453_std_vco_cfg[i][0]);
 398                if (r)
 399                        return r;
 400
 401                /* ack interrupt event */
 402                r = zd_iowrite16_locked(chip, 0x0f, UW2453_INTR_REG);
 403                if (r)
 404                        return r;
 405
 406                /* check interrupt status */
 407                r = zd_ioread16_locked(chip, &intr_status, UW2453_INTR_REG);
 408                if (r)
 409                        return r;
 410
 411                if (!(intr_status & 0xf)) {
 412                        dev_dbg_f(zd_chip_dev(chip),
 413                                "PLL locked on configuration %d\n", i);
 414                        found_config = i;
 415                        break;
 416                }
 417        }
 418
 419        if (found_config == -1) {
 420                /* autocal */
 421                dev_dbg_f(zd_chip_dev(chip),
 422                        "PLL did not lock, using autocal\n");
 423
 424                r = uw2453_synth_set_channel(chip, 1, true);
 425                if (r)
 426                        return r;
 427
 428                r = uw2453_write_vco_cfg(chip, UW2453_AUTOCAL_VCO_CFG);
 429                if (r)
 430                        return r;
 431        }
 432
 433        /* To match the vendor driver behaviour, we use the configuration after
 434         * the one that produced a lock. */
 435        UW2453_PRIV(rf)->config = found_config + 1;
 436
 437        return zd_iowrite16_locked(chip, 0x06, ZD_CR203);
 438}
 439
 440static int uw2453_set_channel(struct zd_rf *rf, u8 channel)
 441{
 442        int r;
 443        u16 vco_cfg;
 444        int config = UW2453_PRIV(rf)->config;
 445        bool autocal = (config == -1);
 446        struct zd_chip *chip = zd_rf_to_chip(rf);
 447
 448        static const struct zd_ioreq16 ioreqs[] = {
 449                { ZD_CR80,  0x30 }, { ZD_CR81,  0x30 }, { ZD_CR79,  0x58 },
 450                { ZD_CR12,  0xf0 }, { ZD_CR77,  0x1b }, { ZD_CR78,  0x58 },
 451        };
 452
 453        r = uw2453_synth_set_channel(chip, channel, autocal);
 454        if (r)
 455                return r;
 456
 457        if (autocal)
 458                vco_cfg = UW2453_AUTOCAL_VCO_CFG;
 459        else
 460                vco_cfg = uw2453_std_vco_cfg[config][CHAN_TO_PAIRIDX(channel)];
 461
 462        r = uw2453_write_vco_cfg(chip, vco_cfg);
 463        if (r)
 464                return r;
 465
 466        r = uw2453_init_mode(chip);
 467        if (r)
 468                return r;
 469
 470        r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 471        if (r)
 472                return r;
 473
 474        r = uw2453_set_tx_gain_level(chip, channel);
 475        if (r)
 476                return r;
 477
 478        return zd_iowrite16_locked(chip, 0x06, ZD_CR203);
 479}
 480
 481static int uw2453_switch_radio_on(struct zd_rf *rf)
 482{
 483        int r;
 484        struct zd_chip *chip = zd_rf_to_chip(rf);
 485        struct zd_ioreq16 ioreqs[] = {
 486                { ZD_CR11,  0x00 }, { ZD_CR251, 0x3f },
 487        };
 488
 489        /* enter RXTX mode */
 490        r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f94), RF_RV_BITS);
 491        if (r)
 492                return r;
 493
 494        if (zd_chip_is_zd1211b(chip))
 495                ioreqs[1].value = 0x7f;
 496
 497        return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 498}
 499
 500static int uw2453_switch_radio_off(struct zd_rf *rf)
 501{
 502        int r;
 503        struct zd_chip *chip = zd_rf_to_chip(rf);
 504        static const struct zd_ioreq16 ioreqs[] = {
 505                { ZD_CR11,  0x04 }, { ZD_CR251, 0x2f },
 506        };
 507
 508        /* enter IDLE mode */
 509        /* FIXME: shouldn't we go to SLEEP? sent email to zydas */
 510        r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f90), RF_RV_BITS);
 511        if (r)
 512                return r;
 513
 514        return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 515}
 516
 517static void uw2453_clear(struct zd_rf *rf)
 518{
 519        kfree(rf->priv);
 520}
 521
 522int zd_rf_init_uw2453(struct zd_rf *rf)
 523{
 524        rf->init_hw = uw2453_init_hw;
 525        rf->set_channel = uw2453_set_channel;
 526        rf->switch_radio_on = uw2453_switch_radio_on;
 527        rf->switch_radio_off = uw2453_switch_radio_off;
 528        rf->patch_6m_band_edge = zd_rf_generic_patch_6m;
 529        rf->clear = uw2453_clear;
 530        /* we have our own TX integration code */
 531        rf->update_channel_int = 0;
 532
 533        rf->priv = kmalloc(sizeof(struct uw2453_priv), GFP_KERNEL);
 534        if (rf->priv == NULL)
 535                return -ENOMEM;
 536
 537        return 0;
 538}
 539
 540