1
2
3
4
5#include <linux/io.h>
6#include <linux/rtc.h>
7#include <linux/module.h>
8#include <linux/slab.h>
9#include <linux/interrupt.h>
10#include <linux/platform_device.h>
11#include <linux/clk.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
14
15#define RTC_INPUT_CLK_32768HZ (0x00 << 5)
16#define RTC_INPUT_CLK_32000HZ (0x01 << 5)
17#define RTC_INPUT_CLK_38400HZ (0x02 << 5)
18
19#define RTC_SW_BIT (1 << 0)
20#define RTC_ALM_BIT (1 << 2)
21#define RTC_1HZ_BIT (1 << 4)
22#define RTC_2HZ_BIT (1 << 7)
23#define RTC_SAM0_BIT (1 << 8)
24#define RTC_SAM1_BIT (1 << 9)
25#define RTC_SAM2_BIT (1 << 10)
26#define RTC_SAM3_BIT (1 << 11)
27#define RTC_SAM4_BIT (1 << 12)
28#define RTC_SAM5_BIT (1 << 13)
29#define RTC_SAM6_BIT (1 << 14)
30#define RTC_SAM7_BIT (1 << 15)
31#define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
32 RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
33 RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)
34
35#define RTC_ENABLE_BIT (1 << 7)
36
37#define MAX_PIE_NUM 9
38#define MAX_PIE_FREQ 512
39
40#define MXC_RTC_TIME 0
41#define MXC_RTC_ALARM 1
42
43#define RTC_HOURMIN 0x00
44#define RTC_SECOND 0x04
45#define RTC_ALRM_HM 0x08
46#define RTC_ALRM_SEC 0x0C
47#define RTC_RTCCTL 0x10
48#define RTC_RTCISR 0x14
49#define RTC_RTCIENR 0x18
50#define RTC_STPWCH 0x1C
51#define RTC_DAYR 0x20
52#define RTC_DAYALARM 0x24
53#define RTC_TEST1 0x28
54#define RTC_TEST2 0x2C
55#define RTC_TEST3 0x30
56
57enum imx_rtc_type {
58 IMX1_RTC,
59 IMX21_RTC,
60};
61
62struct rtc_plat_data {
63 struct rtc_device *rtc;
64 void __iomem *ioaddr;
65 int irq;
66 struct clk *clk_ref;
67 struct clk *clk_ipg;
68 struct rtc_time g_rtc_alarm;
69 enum imx_rtc_type devtype;
70};
71
72static const struct platform_device_id imx_rtc_devtype[] = {
73 {
74 .name = "imx1-rtc",
75 .driver_data = IMX1_RTC,
76 }, {
77 .name = "imx21-rtc",
78 .driver_data = IMX21_RTC,
79 }, {
80
81 }
82};
83MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);
84
85#ifdef CONFIG_OF
86static const struct of_device_id imx_rtc_dt_ids[] = {
87 { .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },
88 { .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },
89 {}
90};
91MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);
92#endif
93
94static inline int is_imx1_rtc(struct rtc_plat_data *data)
95{
96 return data->devtype == IMX1_RTC;
97}
98
99
100
101
102
103static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
104{
105 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
106 void __iomem *ioaddr = pdata->ioaddr;
107 u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
108
109 switch (time_alarm) {
110 case MXC_RTC_TIME:
111 day = readw(ioaddr + RTC_DAYR);
112 hr_min = readw(ioaddr + RTC_HOURMIN);
113 sec = readw(ioaddr + RTC_SECOND);
114 break;
115 case MXC_RTC_ALARM:
116 day = readw(ioaddr + RTC_DAYALARM);
117 hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
118 sec = readw(ioaddr + RTC_ALRM_SEC);
119 break;
120 }
121
122 hr = hr_min >> 8;
123 min = hr_min & 0xff;
124
125 return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
126}
127
128
129
130
131static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
132{
133 u32 tod, day, hr, min, sec, temp;
134 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
135 void __iomem *ioaddr = pdata->ioaddr;
136
137 day = div_s64_rem(time, 86400, &tod);
138
139
140 hr = tod / 3600;
141 tod -= hr * 3600;
142
143
144 min = tod / 60;
145 sec = tod - min * 60;
146
147 temp = (hr << 8) + min;
148
149 switch (time_alarm) {
150 case MXC_RTC_TIME:
151 writew(day, ioaddr + RTC_DAYR);
152 writew(sec, ioaddr + RTC_SECOND);
153 writew(temp, ioaddr + RTC_HOURMIN);
154 break;
155 case MXC_RTC_ALARM:
156 writew(day, ioaddr + RTC_DAYALARM);
157 writew(sec, ioaddr + RTC_ALRM_SEC);
158 writew(temp, ioaddr + RTC_ALRM_HM);
159 break;
160 }
161}
162
163
164
165
166
167static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
168{
169 time64_t time;
170 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
171 void __iomem *ioaddr = pdata->ioaddr;
172
173 time = rtc_tm_to_time64(alrm);
174
175
176 writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
177 set_alarm_or_time(dev, MXC_RTC_ALARM, time);
178}
179
180static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
181 unsigned int enabled)
182{
183 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
184 void __iomem *ioaddr = pdata->ioaddr;
185 u32 reg;
186
187 spin_lock_irq(&pdata->rtc->irq_lock);
188 reg = readw(ioaddr + RTC_RTCIENR);
189
190 if (enabled)
191 reg |= bit;
192 else
193 reg &= ~bit;
194
195 writew(reg, ioaddr + RTC_RTCIENR);
196 spin_unlock_irq(&pdata->rtc->irq_lock);
197}
198
199
200static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
201{
202 struct platform_device *pdev = dev_id;
203 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
204 void __iomem *ioaddr = pdata->ioaddr;
205 unsigned long flags;
206 u32 status;
207 u32 events = 0;
208
209 spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
210 status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
211
212 writew(status, ioaddr + RTC_RTCISR);
213
214
215 if (status & RTC_ALM_BIT) {
216 events |= (RTC_AF | RTC_IRQF);
217
218 mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
219 }
220
221 if (status & PIT_ALL_ON)
222 events |= (RTC_PF | RTC_IRQF);
223
224 rtc_update_irq(pdata->rtc, 1, events);
225 spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
226
227 return IRQ_HANDLED;
228}
229
230static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
231{
232 mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
233 return 0;
234}
235
236
237
238
239static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
240{
241 time64_t val;
242
243
244 do {
245 val = get_alarm_or_time(dev, MXC_RTC_TIME);
246 } while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
247
248 rtc_time64_to_tm(val, tm);
249
250 return 0;
251}
252
253
254
255
256static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
257{
258 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
259
260
261
262
263 if (is_imx1_rtc(pdata)) {
264 struct rtc_time tm;
265
266 rtc_time64_to_tm(time, &tm);
267 tm.tm_year = 70;
268 time = rtc_tm_to_time64(&tm);
269 }
270
271
272 do {
273 set_alarm_or_time(dev, MXC_RTC_TIME, time);
274 } while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
275
276 return 0;
277}
278
279
280
281
282
283
284static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
285{
286 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
287 void __iomem *ioaddr = pdata->ioaddr;
288
289 rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
290 alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;
291
292 return 0;
293}
294
295
296
297
298static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
299{
300 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
301
302 rtc_update_alarm(dev, &alrm->time);
303
304 memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
305 mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);
306
307 return 0;
308}
309
310
311static const struct rtc_class_ops mxc_rtc_ops = {
312 .read_time = mxc_rtc_read_time,
313 .set_mmss64 = mxc_rtc_set_mmss,
314 .read_alarm = mxc_rtc_read_alarm,
315 .set_alarm = mxc_rtc_set_alarm,
316 .alarm_irq_enable = mxc_rtc_alarm_irq_enable,
317};
318
319static int mxc_rtc_probe(struct platform_device *pdev)
320{
321 struct resource *res;
322 struct rtc_device *rtc;
323 struct rtc_plat_data *pdata = NULL;
324 u32 reg;
325 unsigned long rate;
326 int ret;
327 const struct of_device_id *of_id;
328
329 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
330 if (!pdata)
331 return -ENOMEM;
332
333 of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev);
334 if (of_id)
335 pdata->devtype = (enum imx_rtc_type)of_id->data;
336 else
337 pdata->devtype = pdev->id_entry->driver_data;
338
339 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
340 pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
341 if (IS_ERR(pdata->ioaddr))
342 return PTR_ERR(pdata->ioaddr);
343
344 pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
345 if (IS_ERR(pdata->clk_ipg)) {
346 dev_err(&pdev->dev, "unable to get ipg clock!\n");
347 return PTR_ERR(pdata->clk_ipg);
348 }
349
350 ret = clk_prepare_enable(pdata->clk_ipg);
351 if (ret)
352 return ret;
353
354 pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
355 if (IS_ERR(pdata->clk_ref)) {
356 dev_err(&pdev->dev, "unable to get ref clock!\n");
357 ret = PTR_ERR(pdata->clk_ref);
358 goto exit_put_clk_ipg;
359 }
360
361 ret = clk_prepare_enable(pdata->clk_ref);
362 if (ret)
363 goto exit_put_clk_ipg;
364
365 rate = clk_get_rate(pdata->clk_ref);
366
367 if (rate == 32768)
368 reg = RTC_INPUT_CLK_32768HZ;
369 else if (rate == 32000)
370 reg = RTC_INPUT_CLK_32000HZ;
371 else if (rate == 38400)
372 reg = RTC_INPUT_CLK_38400HZ;
373 else {
374 dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
375 ret = -EINVAL;
376 goto exit_put_clk_ref;
377 }
378
379 reg |= RTC_ENABLE_BIT;
380 writew(reg, (pdata->ioaddr + RTC_RTCCTL));
381 if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
382 dev_err(&pdev->dev, "hardware module can't be enabled!\n");
383 ret = -EIO;
384 goto exit_put_clk_ref;
385 }
386
387 platform_set_drvdata(pdev, pdata);
388
389
390 pdata->irq = platform_get_irq(pdev, 0);
391
392 if (pdata->irq >= 0 &&
393 devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
394 IRQF_SHARED, pdev->name, pdev) < 0) {
395 dev_warn(&pdev->dev, "interrupt not available.\n");
396 pdata->irq = -1;
397 }
398
399 if (pdata->irq >= 0)
400 device_init_wakeup(&pdev->dev, 1);
401
402 rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
403 THIS_MODULE);
404 if (IS_ERR(rtc)) {
405 ret = PTR_ERR(rtc);
406 goto exit_put_clk_ref;
407 }
408
409 pdata->rtc = rtc;
410
411 return 0;
412
413exit_put_clk_ref:
414 clk_disable_unprepare(pdata->clk_ref);
415exit_put_clk_ipg:
416 clk_disable_unprepare(pdata->clk_ipg);
417
418 return ret;
419}
420
421static int mxc_rtc_remove(struct platform_device *pdev)
422{
423 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
424
425 clk_disable_unprepare(pdata->clk_ref);
426 clk_disable_unprepare(pdata->clk_ipg);
427
428 return 0;
429}
430
431#ifdef CONFIG_PM_SLEEP
432static int mxc_rtc_suspend(struct device *dev)
433{
434 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
435
436 if (device_may_wakeup(dev))
437 enable_irq_wake(pdata->irq);
438
439 return 0;
440}
441
442static int mxc_rtc_resume(struct device *dev)
443{
444 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
445
446 if (device_may_wakeup(dev))
447 disable_irq_wake(pdata->irq);
448
449 return 0;
450}
451#endif
452
453static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);
454
455static struct platform_driver mxc_rtc_driver = {
456 .driver = {
457 .name = "mxc_rtc",
458 .of_match_table = of_match_ptr(imx_rtc_dt_ids),
459 .pm = &mxc_rtc_pm_ops,
460 },
461 .id_table = imx_rtc_devtype,
462 .probe = mxc_rtc_probe,
463 .remove = mxc_rtc_remove,
464};
465
466module_platform_driver(mxc_rtc_driver)
467
468MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
469MODULE_DESCRIPTION("RTC driver for Freescale MXC");
470MODULE_LICENSE("GPL");
471
472
