1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright 2013-2016 Freescale Semiconductor Inc. 4 * Copyright 2016-2018 NXP 5 */ 6 7#ifndef _FSL_DPRTC_CMD_H 8#define _FSL_DPRTC_CMD_H 9 10/* DPRTC Version */ 11#define DPRTC_VER_MAJOR 2 12#define DPRTC_VER_MINOR 0 13 14/* Command versioning */ 15#define DPRTC_CMD_BASE_VERSION 1 16#define DPRTC_CMD_ID_OFFSET 4 17 18#define DPRTC_CMD(id) (((id) << DPRTC_CMD_ID_OFFSET) | DPRTC_CMD_BASE_VERSION) 19 20/* Command IDs */ 21#define DPRTC_CMDID_CLOSE DPRTC_CMD(0x800) 22#define DPRTC_CMDID_OPEN DPRTC_CMD(0x810) 23#define DPRTC_CMDID_CREATE DPRTC_CMD(0x910) 24#define DPRTC_CMDID_DESTROY DPRTC_CMD(0x990) 25#define DPRTC_CMDID_GET_API_VERSION DPRTC_CMD(0xa10) 26 27#define DPRTC_CMDID_ENABLE DPRTC_CMD(0x002) 28#define DPRTC_CMDID_DISABLE DPRTC_CMD(0x003) 29#define DPRTC_CMDID_GET_ATTR DPRTC_CMD(0x004) 30#define DPRTC_CMDID_RESET DPRTC_CMD(0x005) 31#define DPRTC_CMDID_IS_ENABLED DPRTC_CMD(0x006) 32 33#define DPRTC_CMDID_SET_IRQ_ENABLE DPRTC_CMD(0x012) 34#define DPRTC_CMDID_GET_IRQ_ENABLE DPRTC_CMD(0x013) 35#define DPRTC_CMDID_SET_IRQ_MASK DPRTC_CMD(0x014) 36#define DPRTC_CMDID_GET_IRQ_MASK DPRTC_CMD(0x015) 37#define DPRTC_CMDID_GET_IRQ_STATUS DPRTC_CMD(0x016) 38#define DPRTC_CMDID_CLEAR_IRQ_STATUS DPRTC_CMD(0x017) 39 40#define DPRTC_CMDID_SET_CLOCK_OFFSET DPRTC_CMD(0x1d0) 41#define DPRTC_CMDID_SET_FREQ_COMPENSATION DPRTC_CMD(0x1d1) 42#define DPRTC_CMDID_GET_FREQ_COMPENSATION DPRTC_CMD(0x1d2) 43#define DPRTC_CMDID_GET_TIME DPRTC_CMD(0x1d3) 44#define DPRTC_CMDID_SET_TIME DPRTC_CMD(0x1d4) 45#define DPRTC_CMDID_SET_ALARM DPRTC_CMD(0x1d5) 46#define DPRTC_CMDID_SET_PERIODIC_PULSE DPRTC_CMD(0x1d6) 47#define DPRTC_CMDID_CLEAR_PERIODIC_PULSE DPRTC_CMD(0x1d7) 48#define DPRTC_CMDID_SET_EXT_TRIGGER DPRTC_CMD(0x1d8) 49#define DPRTC_CMDID_CLEAR_EXT_TRIGGER DPRTC_CMD(0x1d9) 50#define DPRTC_CMDID_GET_EXT_TRIGGER_TIMESTAMP DPRTC_CMD(0x1dA) 51 52/* Macros for accessing command fields smaller than 1byte */ 53#define DPRTC_MASK(field) \ 54 GENMASK(DPRTC_##field##_SHIFT + DPRTC_##field##_SIZE - 1, \ 55 DPRTC_##field##_SHIFT) 56#define dprtc_get_field(var, field) \ 57 (((var) & DPRTC_MASK(field)) >> DPRTC_##field##_SHIFT) 58 59#pragma pack(push, 1) 60struct dprtc_cmd_open { 61 __le32 dprtc_id; 62}; 63 64struct dprtc_cmd_destroy { 65 __le32 object_id; 66}; 67 68#define DPRTC_ENABLE_SHIFT 0 69#define DPRTC_ENABLE_SIZE 1 70 71struct dprtc_rsp_is_enabled { 72 u8 en; 73}; 74 75struct dprtc_cmd_get_irq { 76 __le32 pad; 77 u8 irq_index; 78}; 79 80struct dprtc_cmd_set_irq_enable { 81 u8 en; 82 u8 pad[3]; 83 u8 irq_index; 84}; 85 86struct dprtc_rsp_get_irq_enable { 87 u8 en; 88}; 89 90struct dprtc_cmd_set_irq_mask { 91 __le32 mask; 92 u8 irq_index; 93}; 94 95struct dprtc_rsp_get_irq_mask { 96 __le32 mask; 97}; 98 99struct dprtc_cmd_get_irq_status { 100 __le32 status; 101 u8 irq_index; 102}; 103 104struct dprtc_rsp_get_irq_status { 105 __le32 status; 106}; 107 108struct dprtc_cmd_clear_irq_status { 109 __le32 status; 110 u8 irq_index; 111}; 112 113struct dprtc_rsp_get_attributes { 114 __le32 pad; 115 __le32 id; 116}; 117 118struct dprtc_cmd_set_clock_offset { 119 __le64 offset; 120}; 121 122struct dprtc_get_freq_compensation { 123 __le32 freq_compensation; 124}; 125 126struct dprtc_time { 127 __le64 time; 128}; 129 130struct dprtc_rsp_get_api_version { 131 __le16 major; 132 __le16 minor; 133}; 134 135#pragma pack(pop) 136 137#endif /* _FSL_DPRTC_CMD_H */ 138