LXR linux/drivers/staging/mt7621-pci/pci-mt7621.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/**************************************************************************
   3 *
   4 *  BRIEF MODULE DESCRIPTION
   5 *     PCI init for Ralink RT2880 solution
   6 *
   7 *  Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
   8 *
   9 *  This program is free software; you can redistribute  it and/or modify it
  10 *  under  the terms of  the GNU General  Public License as published by the
  11 *  Free Software Foundation;  either version 2 of the  License, or (at your
  12 *  option) any later version.
  13 *
  14 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  15 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  16 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  17 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  18 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  20 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  22 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24 *
  25 *  You should have received a copy of the  GNU General Public License along
  26 *  with this program; if not, write  to the Free Software Foundation, Inc.,
  27 *  675 Mass Ave, Cambridge, MA 02139, USA.
  28 *
  29 *
  30 **************************************************************************
  31 * May 2007 Bruce Chang
  32 * Initial Release
  33 *
  34 * May 2009 Bruce Chang
  35 * support RT2880/RT3883 PCIe
  36 *
  37 * May 2011 Bruce Chang
  38 * support RT6855/MT7620 PCIe
  39 *
  40 **************************************************************************
  41 */
  42
  43#include <linux/bitops.h>
  44#include <linux/clk.h>
  45#include <linux/delay.h>
  46#include <linux/module.h>
  47#include <linux/of.h>
  48#include <linux/of_address.h>
  49#include <linux/of_irq.h>
  50#include <linux/of_pci.h>
  51#include <linux/of_platform.h>
  52#include <linux/pci.h>
  53#include <linux/platform_device.h>
  54#include <linux/reset.h>
  55#include <mt7621.h>
  56#include <ralink_regs.h>
  57
  58#include "../../pci/pci.h"
  59
  60/*
  61 * These functions and structures provide the BIOS scan and mapping of the PCI
  62 * devices.
  63 */
  64
  65#define RALINK_PCIE0_CLK_EN             BIT(24)
  66#define RALINK_PCIE1_CLK_EN             BIT(25)
  67#define RALINK_PCIE2_CLK_EN             BIT(26)
  68
  69#define RALINK_PCI_CONFIG_ADDR          0x20
  70#define RALINK_PCI_CONFIG_DATA          0x24
  71#define RALINK_PCI_MEMBASE              0x28
  72#define RALINK_PCI_IOBASE               0x2C
  73#define RALINK_PCIE0_RST                BIT(24)
  74#define RALINK_PCIE1_RST                BIT(25)
  75#define RALINK_PCIE2_RST                BIT(26)
  76
  77#define RALINK_PCI_PCICFG_ADDR          0x0000
  78#define RALINK_PCI_PCIMSK_ADDR          0x000C
  79
  80#define RT6855_PCIE0_OFFSET             0x2000
  81#define RT6855_PCIE1_OFFSET             0x3000
  82#define RT6855_PCIE2_OFFSET             0x4000
  83
  84#define RALINK_PCI_BAR0SETUP_ADDR       0x0010
  85#define RALINK_PCI_IMBASEBAR0_ADDR      0x0018
  86#define RALINK_PCI_ID                   0x0030
  87#define RALINK_PCI_CLASS                0x0034
  88#define RALINK_PCI_SUBID                0x0038
  89#define RALINK_PCI_STATUS               0x0050
  90
  91#define RALINK_PCIEPHY_P0P1_CTL_OFFSET  0x9000
  92#define RALINK_PCIEPHY_P2_CTL_OFFSET    0xA000
  93
  94#define RALINK_PCI_MM_MAP_BASE          0x60000000
  95#define RALINK_PCI_IO_MAP_BASE          0x1e160000
  96
  97#define ASSERT_SYSRST_PCIE(val)         \
  98        do {                                                            \
  99                if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101)       \
 100                        rt_sysc_m32(0, val, RALINK_RSTCTRL);            \
 101                else                                                    \
 102                        rt_sysc_m32(val, 0, RALINK_RSTCTRL);            \
 103        } while (0)
 104#define DEASSERT_SYSRST_PCIE(val)       \
 105        do {                                                            \
 106                if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101)       \
 107                        rt_sysc_m32(val, 0, RALINK_RSTCTRL);            \
 108                else                                                    \
 109                        rt_sysc_m32(0, val, RALINK_RSTCTRL);            \
 110        } while (0)
 111
 112#define RALINK_CLKCFG1                  0x30
 113#define RALINK_RSTCTRL                  0x34
 114#define RALINK_GPIOMODE                 0x60
 115#define RALINK_PCIE_CLK_GEN             0x7c
 116#define RALINK_PCIE_CLK_GEN1            0x80
 117//RALINK_RSTCTRL bit
 118#define RALINK_PCIE_RST                 BIT(23)
 119#define RALINK_PCI_RST                  BIT(24)
 120//RALINK_CLKCFG1 bit
 121#define RALINK_PCI_CLK_EN               BIT(19)
 122#define RALINK_PCIE_CLK_EN              BIT(21)
 123
 124#define MEMORY_BASE 0x0
 125static int pcie_link_status = 0;
 126
 127/**
 128 * struct mt7621_pcie_port - PCIe port information
 129 * @base: IO mapped register base
 130 * @list: port list
 131 * @pcie: pointer to PCIe host info
 132 * @reset: pointer to port reset control
 133 */
 134struct mt7621_pcie_port {
 135        void __iomem *base;
 136        struct list_head list;
 137        struct mt7621_pcie *pcie;
 138        struct reset_control *reset;
 139};
 140
 141/**
 142 * struct mt7621_pcie - PCIe host information
 143 * @base: IO Mapped Register Base
 144 * @io: IO resource
 145 * @mem: non-prefetchable memory resource
 146 * @busn: bus range
 147 * @offset: IO / Memory offset
 148 * @dev: Pointer to PCIe device
 149 * @ports: pointer to PCIe port information
 150 */
 151struct mt7621_pcie {
 152        void __iomem *base;
 153        struct device *dev;
 154        struct resource io;
 155        struct resource mem;
 156        struct resource busn;
 157        struct {
 158                resource_size_t mem;
 159                resource_size_t io;
 160        } offset;
 161        struct list_head ports;
 162};
 163
 164static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
 165{
 166        return readl(pcie->base + reg);
 167}
 168
 169static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
 170{
 171        writel(val, pcie->base + reg);
 172}
 173
 174static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 175                                         unsigned int func, unsigned int where)
 176{
 177        return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |
 178                (func << 8) | (where & 0xfc) | 0x80000000;
 179}
 180
 181static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
 182                                         unsigned int devfn, int where)
 183{
 184        struct mt7621_pcie *pcie = bus->sysdata;
 185        u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 186                                             PCI_FUNC(devfn), where);
 187
 188        writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
 189
 190        return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
 191}
 192
 193struct pci_ops mt7621_pci_ops = {
 194        .map_bus        = mt7621_pcie_map_bus,
 195        .read           = pci_generic_config_read,
 196        .write          = pci_generic_config_write,
 197};
 198
 199static u32
 200read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
 201{
 202        u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 203
 204        pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
 205        return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
 206}
 207
 208static void
 209write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
 210{
 211        u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 212
 213        pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
 214        pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
 215}
 216
 217void
 218set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
 219             int start_b, int bits, int val)
 220{
 221        u32 reg = pcie_read(pcie, offset);
 222
 223        reg &= ~(((1 << bits) - 1) << start_b);
 224        reg |= val << start_b;
 225        pcie_write(pcie, reg, offset);
 226}
 227
 228void
 229bypass_pipe_rst(struct mt7621_pcie *pcie)
 230{
 231        /* PCIe Port 0 */
 232        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);      // rg_pe1_pipe_rst_b
 233        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);      // rg_pe1_pipe_cmd_frc[4]
 234        /* PCIe Port 1 */
 235        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);      // rg_pe1_pipe_rst_b
 236        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);      // rg_pe1_pipe_cmd_frc[4]
 237        /* PCIe Port 2 */
 238        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);        // rg_pe1_pipe_rst_b
 239        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);        // rg_pe1_pipe_cmd_frc[4]
 240}
 241
 242void
 243set_phy_for_ssc(struct mt7621_pcie *pcie)
 244{
 245        unsigned long reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
 246
 247        reg = (reg >> 6) & 0x7;
 248        /* Set PCIe Port0 & Port1 PHY to disable SSC */
 249        /* Debug Xtal Type */
 250        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);      // rg_pe1_frc_h_xtal_type
 251        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);      // rg_pe1_h_xtal_type
 252        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);      // rg_pe1_frc_phy_en    //Force Port 0 enable control
 253        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);      // rg_pe1_frc_phy_en    //Force Port 1 enable control
 254        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);      // rg_pe1_phy_en        //Port 0 disable
 255        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);      // rg_pe1_phy_en        //Port 1 disable
 256        if (reg <= 5 && reg >= 3) {     // 40MHz Xtal
 257                set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x01);      // RG_PE1_H_PLL_PREDIV  //Pre-divider ratio (for host mode)
 258                printk("***** Xtal 40MHz *****\n");
 259        } else {                        // 25MHz | 20MHz Xtal
 260                set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x00);      // RG_PE1_H_PLL_PREDIV  //Pre-divider ratio (for host mode)
 261                if (reg >= 6) {
 262                        printk("***** Xtal 25MHz *****\n");
 263                        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);      // RG_PE1_H_PLL_FBKSEL  //Feedback clock select
 264                        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);       // RG_PE1_H_LCDDS_PCW_NCPO      //DDS NCPO PCW (for host mode)
 265                        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);    // RG_PE1_H_LCDDS_SSC_PRD       //DDS SSC dither period control
 266                        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);     // RG_PE1_H_LCDDS_SSC_DELTA     //DDS SSC dither amplitude control
 267                        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);     // RG_PE1_H_LCDDS_SSC_DELTA1    //DDS SSC dither amplitude control for initial
 268                } else {
 269                        printk("***** Xtal 20MHz *****\n");
 270                }
 271        }
 272        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0),  5, 1, 0x01);      // RG_PE1_LCDDS_CLK_PH_INV      //DDS clock inversion
 273        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);      // RG_PE1_H_PLL_BC
 274        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);      // RG_PE1_H_PLL_BP
 275        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);      // RG_PE1_H_PLL_IR
 276        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  8, 4, 0x01);      // RG_PE1_H_PLL_IC
 277        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);      // RG_PE1_H_PLL_BR
 278        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  1, 3, 0x02);      // RG_PE1_PLL_DIVEN
 279        if (reg <= 5 && reg >= 3) {     // 40MHz Xtal
 280                set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  6, 2, 0x01);      // rg_pe1_mstckdiv              //value of da_pe1_mstckdiv when force mode enable
 281                set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  5, 1, 0x01);      // rg_pe1_frc_mstckdiv  //force mode enable of da_pe1_mstckdiv
 282        }
 283        /* Enable PHY and disable force mode */
 284        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x01);      // rg_pe1_phy_en        //Port 0 enable
 285        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);      // rg_pe1_phy_en        //Port 1 enable
 286        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);      // rg_pe1_frc_phy_en    //Force Port 0 disable control
 287        set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);      // rg_pe1_frc_phy_en    //Force Port 1 disable control
 288
 289        /* Set PCIe Port2 PHY to disable SSC */
 290        /* Debug Xtal Type */
 291        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);        // rg_pe1_frc_h_xtal_type
 292        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  9, 2, 0x00);        // rg_pe1_h_xtal_type
 293        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x01);        // rg_pe1_frc_phy_en    //Force Port 0 enable control
 294        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x00);        // rg_pe1_phy_en        //Port 0 disable
 295        if (reg <= 5 && reg >= 3) {     // 40MHz Xtal
 296                set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x01);        // RG_PE1_H_PLL_PREDIV  //Pre-divider ratio (for host mode)
 297        } else {                        // 25MHz | 20MHz Xtal
 298                set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);        // RG_PE1_H_PLL_PREDIV  //Pre-divider ratio (for host mode)
 299                if (reg >= 6) {         // 25MHz Xtal
 300                        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);        // RG_PE1_H_PLL_FBKSEL  //Feedback clock select
 301                        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO      //DDS NCPO PCW (for host mode)
 302                        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);      // RG_PE1_H_LCDDS_SSC_PRD       //DDS SSC dither period control
 303                        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);       // RG_PE1_H_LCDDS_SSC_DELTA     //DDS SSC dither amplitude control
 304                        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);       // RG_PE1_H_LCDDS_SSC_DELTA1    //DDS SSC dither amplitude control for initial
 305                }
 306        }
 307        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);        // RG_PE1_LCDDS_CLK_PH_INV      //DDS clock inversion
 308        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);        // RG_PE1_H_PLL_BC
 309        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);        // RG_PE1_H_PLL_BP
 310        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);        // RG_PE1_H_PLL_IR
 311        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  8, 4, 0x01);        // RG_PE1_H_PLL_IC
 312        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);        // RG_PE1_H_PLL_BR
 313        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  1, 3, 0x02);        // RG_PE1_PLL_DIVEN
 314        if (reg <= 5 && reg >= 3) {     // 40MHz Xtal
 315                set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  6, 2, 0x01);        // rg_pe1_mstckdiv              //value of da_pe1_mstckdiv when force mode enable
 316                set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  5, 1, 0x01);        // rg_pe1_frc_mstckdiv  //force mode enable of da_pe1_mstckdiv
 317        }
 318        /* Enable PHY and disable force mode */
 319        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);        // rg_pe1_phy_en        //Port 0 enable
 320        set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);        // rg_pe1_frc_phy_en    //Force Port 0 disable control
 321}
 322
 323static void setup_cm_memory_region(struct resource *mem_resource)
 324{
 325        resource_size_t mask;
 326
 327        if (mips_cps_numiocu(0)) {
 328                /* FIXME: hardware doesn't accept mask values with 1s after
 329                 * 0s (e.g. 0xffef), so it would be great to warn if that's
 330                 * about to happen */
 331                mask = ~(mem_resource->end - mem_resource->start);
 332
 333                write_gcr_reg1_base(mem_resource->start);
 334                write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
 335                printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
 336                        (unsigned long long)read_gcr_reg1_base(),
 337                        (unsigned long long)read_gcr_reg1_mask());
 338        }
 339}
 340
 341static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie)
 342{
 343        struct device *dev = pcie->dev;
 344        struct device_node *node = dev->of_node;
 345        struct of_pci_range_parser parser;
 346        struct of_pci_range range;
 347        int err;
 348
 349        if (of_pci_range_parser_init(&parser, node)) {
 350                dev_err(dev, "missing \"ranges\" property\n");
 351                return -EINVAL;
 352        }
 353
 354        for_each_of_pci_range(&parser, &range) {
 355                struct resource *res = NULL;
 356
 357                switch (range.flags & IORESOURCE_TYPE_BITS) {
 358                case IORESOURCE_IO:
 359                        ioremap(range.cpu_addr, range.size);
 360                        res = &pcie->io;
 361                        pcie->offset.io = 0x00000000UL;
 362                        break;
 363                case IORESOURCE_MEM:
 364                        res = &pcie->mem;
 365                        pcie->offset.mem = 0x00000000UL;
 366                        break;
 367                }
 368
 369                if (res != NULL)
 370                        of_pci_range_to_resource(&range, node, res);
 371        }
 372
 373        err = of_pci_parse_bus_range(node, &pcie->busn);
 374        if (err < 0) {
 375                dev_err(dev, "failed to parse bus ranges property: %d\n", err);
 376                pcie->busn.name = node->name;
 377                pcie->busn.start = 0;
 378                pcie->busn.end = 0xff;
 379                pcie->busn.flags = IORESOURCE_BUS;
 380        }
 381
 382        return 0;
 383}
 384
 385static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
 386{
 387        struct device *dev = pcie->dev;
 388        struct device_node *node = dev->of_node;
 389        struct resource regs;
 390        const char *type;
 391        int err;
 392
 393        type = of_get_property(node, "device_type", NULL);
 394        if (!type || strcmp(type, "pci") != 0) {
 395                dev_err(dev, "invalid \"device_type\" %s\n", type);
 396                return -EINVAL;
 397        }
 398
 399        err = of_address_to_resource(node, 0, &regs);
 400        if (err) {
 401                dev_err(dev, "missing \"reg\" property\n");
 402                return err;
 403        }
 404
 405        pcie->base = devm_ioremap_resource(dev, &regs);
 406        if (IS_ERR(pcie->base))
 407                return PTR_ERR(pcie->base);
 408
 409        return 0;
 410}
 411
 412static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
 413                                         struct list_head *res)
 414{
 415        struct device *dev = pcie->dev;
 416        int err;
 417
 418        pci_add_resource_offset(res, &pcie->io, pcie->offset.io);
 419        pci_add_resource_offset(res, &pcie->mem, pcie->offset.mem);
 420        pci_add_resource(res, &pcie->busn);
 421
 422        err = devm_request_pci_bus_resources(dev, res);
 423        if (err < 0)
 424                return err;
 425
 426        return 0;
 427}
 428
 429static int mt7621_pcie_register_host(struct pci_host_bridge *host,
 430                                     struct list_head *res)
 431{
 432        struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
 433
 434        list_splice_init(res, &host->windows);
 435        host->busnr = pcie->busn.start;
 436        host->dev.parent = pcie->dev;
 437        host->ops = &mt7621_pci_ops;
 438        host->map_irq = of_irq_parse_and_map_pci;
 439        host->swizzle_irq = pci_common_swizzle;
 440        host->sysdata = pcie;
 441
 442        return pci_host_probe(host);
 443}
 444
 445static int mt7621_pci_probe(struct platform_device *pdev)
 446{
 447        struct device *dev = &pdev->dev;
 448        struct mt7621_pcie *pcie;
 449        struct pci_host_bridge *bridge;
 450        int err;
 451        u32 val = 0;
 452        LIST_HEAD(res);
 453
 454        if (!dev->of_node)
 455                return -ENODEV;
 456
 457        bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
 458        if (!bridge)
 459                return -ENODEV;
 460
 461        pcie = pci_host_bridge_priv(bridge);
 462        pcie->dev = dev;
 463        platform_set_drvdata(pdev, pcie);
 464        INIT_LIST_HEAD(&pcie->ports);
 465
 466        err = mt7621_pcie_parse_dt(pcie);
 467        if (err) {
 468                dev_err(dev, "Parsing DT failed\n");
 469                return err;
 470        }
 471
 472        /* set resources limits */
 473        iomem_resource.start = 0;
 474        iomem_resource.end = ~0UL; /* no limit */
 475        ioport_resource.start = 0;
 476        ioport_resource.end = ~0UL; /* no limit */
 477
 478        val = RALINK_PCIE0_RST;
 479        val |= RALINK_PCIE1_RST;
 480        val |= RALINK_PCIE2_RST;
 481
 482        ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
 483
 484        *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
 485        *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
 486        mdelay(100);
 487        *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
 488        mdelay(100);
 489        *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7);          // clear DATA
 490
 491        mdelay(100);
 492
 493        val = RALINK_PCIE0_RST;
 494        val |= RALINK_PCIE1_RST;
 495        val |= RALINK_PCIE2_RST;
 496
 497        DEASSERT_SYSRST_PCIE(val);
 498
 499        if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
 500                bypass_pipe_rst(pcie);
 501        set_phy_for_ssc(pcie);
 502
 503        val = read_config(pcie, 0, 0x70c);
 504        printk("Port 0 N_FTS = %x\n", (unsigned int)val);
 505
 506        val = read_config(pcie, 1, 0x70c);
 507        printk("Port 1 N_FTS = %x\n", (unsigned int)val);
 508
 509        val = read_config(pcie, 2, 0x70c);
 510        printk("Port 2 N_FTS = %x\n", (unsigned int)val);
 511
 512        rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
 513        rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
 514
 515        rt_sysc_m32(0x80000000, 0, RALINK_PCIE_CLK_GEN);
 516        rt_sysc_m32(0x7f000000, 0xa << 24, RALINK_PCIE_CLK_GEN1);
 517        rt_sysc_m32(0, 0x80000000, RALINK_PCIE_CLK_GEN);
 518
 519        mdelay(50);
 520        rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL);
 521
 522        /* Use GPIO control instead of PERST_N */
 523        *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;             // set DATA
 524        mdelay(1000);
 525
 526        if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
 527                printk("PCIE0 no card, disable it(RST&CLK)\n");
 528                ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
 529                rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 530                pcie_link_status &= ~(1<<0);
 531        } else {
 532                pcie_link_status |= 1<<0;
 533                val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
 534                val |= (1<<20); // enable pcie1 interrupt
 535                pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
 536        }
 537
 538        if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
 539                printk("PCIE1 no card, disable it(RST&CLK)\n");
 540                ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
 541                rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
 542                pcie_link_status &= ~(1<<1);
 543        } else {
 544                pcie_link_status |= 1<<1;
 545                val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
 546                val |= (1<<21); // enable pcie1 interrupt
 547                pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
 548        }
 549
 550        if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
 551                printk("PCIE2 no card, disable it(RST&CLK)\n");
 552                ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
 553                rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1);
 554                pcie_link_status &= ~(1<<2);
 555        } else {
 556                pcie_link_status |= 1<<2;
 557                val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
 558                val |= (1<<22); // enable pcie2 interrupt
 559                pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
 560        }
 561
 562        if (pcie_link_status == 0)
 563                return 0;
 564
 565/*
 566pcie(2/1/0) link status pcie2_num       pcie1_num       pcie0_num
 5673'b000                  x               x               x
 5683'b001                  x               x               0
 5693'b010                  x               0               x
 5703'b011                  x               1               0
 5713'b100                  0               x               x
 5723'b101                  1               x               0
 5733'b110                  1               0               x
 5743'b111                  2               1               0
 575*/
 576        switch (pcie_link_status) {
 577        case 2:
 578                val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
 579                val &= ~0x00ff0000;
 580                val |= 0x1 << 16;       // port 0
 581                val |= 0x0 << 20;       // port 1
 582                pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 583                break;
 584        case 4:
 585                val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
 586                val &= ~0x0fff0000;
 587                val |= 0x1 << 16;       //port0
 588                val |= 0x2 << 20;       //port1
 589                val |= 0x0 << 24;       //port2
 590                pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 591                break;
 592        case 5:
 593                val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
 594                val &= ~0x0fff0000;
 595                val |= 0x0 << 16;       //port0
 596                val |= 0x2 << 20;       //port1
 597                val |= 0x1 << 24;       //port2
 598                pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 599                break;
 600        case 6:
 601                val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
 602                val &= ~0x0fff0000;
 603                val |= 0x2 << 16;       //port0
 604                val |= 0x0 << 20;       //port1
 605                val |= 0x1 << 24;       //port2
 606                pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 607                break;
 608        }
 609
 610/*
 611        ioport_resource.start = mt7621_res_pci_io1.start;
 612        ioport_resource.end = mt7621_res_pci_io1.end;
 613*/
 614
 615        pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
 616        pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
 617
 618        //PCIe0
 619        if ((pcie_link_status & 0x1) != 0) {
 620                /* open 7FFF:2G; ENABLE */
 621                pcie_write(pcie, 0x7FFF0001,
 622                           RT6855_PCIE0_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
 623                pcie_write(pcie, MEMORY_BASE,
 624                           RT6855_PCIE0_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
 625                pcie_write(pcie, 0x06040001,
 626                           RT6855_PCIE0_OFFSET + RALINK_PCI_CLASS);
 627                printk("PCIE0 enabled\n");
 628        }
 629
 630        //PCIe1
 631        if ((pcie_link_status & 0x2) != 0) {
 632                /* open 7FFF:2G; ENABLE */
 633                pcie_write(pcie, 0x7FFF0001,
 634                           RT6855_PCIE1_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
 635                pcie_write(pcie, MEMORY_BASE,
 636                           RT6855_PCIE1_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
 637                pcie_write(pcie, 0x06040001,
 638                           RT6855_PCIE1_OFFSET + RALINK_PCI_CLASS);
 639                printk("PCIE1 enabled\n");
 640        }
 641
 642        //PCIe2
 643        if ((pcie_link_status & 0x4) != 0) {
 644                /* open 7FFF:2G; ENABLE */
 645                pcie_write(pcie, 0x7FFF0001,
 646                           RT6855_PCIE2_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
 647                pcie_write(pcie, MEMORY_BASE,
 648                           RT6855_PCIE2_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
 649                pcie_write(pcie, 0x06040001,
 650                           RT6855_PCIE2_OFFSET + RALINK_PCI_CLASS);
 651                printk("PCIE2 enabled\n");
 652        }
 653
 654        switch (pcie_link_status) {
 655        case 7:
 656                val = read_config(pcie, 2, 0x4);
 657                write_config(pcie, 2, 0x4, val|0x4);
 658                val = read_config(pcie, 2, 0x70c);
 659                val &= ~(0xff)<<8;
 660                val |= 0x50<<8;
 661                write_config(pcie, 2, 0x70c, val);
 662        case 3:
 663        case 5:
 664        case 6:
 665                val = read_config(pcie, 1, 0x4);
 666                write_config(pcie, 1, 0x4, val|0x4);
 667                val = read_config(pcie, 1, 0x70c);
 668                val &= ~(0xff)<<8;
 669                val |= 0x50<<8;
 670                write_config(pcie, 1, 0x70c, val);
 671        default:
 672                val = read_config(pcie, 0, 0x4);
 673                write_config(pcie, 0, 0x4, val|0x4); //bus master enable
 674                val = read_config(pcie, 0, 0x70c);
 675                val &= ~(0xff)<<8;
 676                val |= 0x50<<8;
 677                write_config(pcie, 0, 0x70c, val);
 678        }
 679
 680        err = mt7621_pci_parse_request_of_pci_ranges(pcie);
 681        if (err) {
 682                dev_err(dev, "Error requesting pci resources from ranges");
 683                return err;
 684        }
 685
 686        setup_cm_memory_region(&pcie->mem);
 687
 688        err = mt7621_pcie_request_resources(pcie, &res);
 689        if (err) {
 690                dev_err(dev, "Error requesting resources\n");
 691                return err;
 692        }
 693
 694        err = mt7621_pcie_register_host(bridge, &res);
 695        if (err) {
 696                dev_err(dev, "Error registering host\n");
 697                return err;
 698        }
 699
 700        return 0;
 701}
 702
 703static const struct of_device_id mt7621_pci_ids[] = {
 704        { .compatible = "mediatek,mt7621-pci" },
 705        {},
 706};
 707MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
 708
 709static struct platform_driver mt7621_pci_driver = {
 710        .probe = mt7621_pci_probe,
 711        .driver = {
 712                .name = "mt7621-pci",
 713                .of_match_table = of_match_ptr(mt7621_pci_ids),
 714        },
 715};
 716
 717static int __init mt7621_pci_init(void)
 718{
 719        return platform_driver_register(&mt7621_pci_driver);
 720}
 721
 722arch_initcall(mt7621_pci_init);
 723