LXR linux/drivers/staging/rtlwifi/phydm/phydm

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/******************************************************************************
   3 *
   4 * Copyright(c) 2007 - 2016  Realtek Corporation.
   5 *
   6 * Contact Information:
   7 * wlanfae <wlanfae@realtek.com>
   8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
   9 * Hsinchu 300, Taiwan.
  10 *
  11 * Larry Finger <Larry.Finger@lwfinger.net>
  12 *
  13 *****************************************************************************/
  14
  15#ifndef __HALHWOUTSRC_H__
  16#define __HALHWOUTSRC_H__
  17
  18/*--------------------------Define -------------------------------------------*/
  19#define CCK_RSSI_INIT_COUNT 5
  20
  21#define RA_RSSI_STATE_INIT 0
  22#define RA_RSSI_STATE_SEND 1
  23#define RA_RSSI_STATE_HOLD 2
  24
  25#define CFO_HW_RPT_2_MHZ(val) ((val << 1) + (val >> 1))
  26/* ((X* 3125)  / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1  */
  27
  28#define AGC_DIFF_CONFIG_MP(ic, band)                                           \
  29        (odm_read_and_config_mp_##ic##_agc_tab_diff(                           \
  30                dm, array_mp_##ic##_agc_tab_diff_##band,                       \
  31                sizeof(array_mp_##ic##_agc_tab_diff_##band) / sizeof(u32)))
  32#define AGC_DIFF_CONFIG_TC(ic, band)                                           \
  33        (odm_read_and_config_tc_##ic##_agc_tab_diff(                           \
  34                dm, array_tc_##ic##_agc_tab_diff_##band,                       \
  35                sizeof(array_tc_##ic##_agc_tab_diff_##band) / sizeof(u32)))
  36
  37#define AGC_DIFF_CONFIG(ic, band)                                              \
  38        do {                                                                   \
  39                if (dm->is_mp_chip)                                            \
  40                        AGC_DIFF_CONFIG_MP(ic, band);                          \
  41                else                                                           \
  42                        AGC_DIFF_CONFIG_TC(ic, band);                          \
  43        } while (0)
  44
  45/* ************************************************************
  46 * structure and define
  47 * *************************************************************/
  48
  49struct phy_rx_agc_info {
  50#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
  51        u8 gain : 7, trsw : 1;
  52#else
  53        u8 trsw : 1, gain : 7;
  54#endif
  55};
  56
  57struct phy_status_rpt_8192cd {
  58        struct phy_rx_agc_info path_agc[2];
  59        u8 ch_corr[2];
  60        u8 cck_sig_qual_ofdm_pwdb_all;
  61        u8 cck_agc_rpt_ofdm_cfosho_a;
  62        u8 cck_rpt_b_ofdm_cfosho_b;
  63        u8 rsvd_1; /*ch_corr_msb;*/
  64        u8 noise_power_db_msb;
  65        s8 path_cfotail[2];
  66        u8 pcts_mask[2];
  67        s8 stream_rxevm[2];
  68        u8 path_rxsnr[2];
  69        u8 noise_power_db_lsb;
  70        u8 rsvd_2[3];
  71        u8 stream_csi[2];
  72        u8 stream_target_csi[2];
  73        s8 sig_evm;
  74        u8 rsvd_3;
  75
  76#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
  77        u8 antsel_rx_keep_2 : 1; /*ex_intf_flg:1;*/
  78        u8 sgi_en : 1;
  79        u8 rxsc : 2;
  80        u8 idle_long : 1;
  81        u8 r_ant_train_en : 1;
  82        u8 ant_sel_b : 1;
  83        u8 ant_sel : 1;
  84#else /*_BIG_ENDIAN_    */
  85        u8 ant_sel : 1;
  86        u8 ant_sel_b : 1;
  87        u8 r_ant_train_en : 1;
  88        u8 idle_long : 1;
  89        u8 rxsc : 2;
  90        u8 sgi_en : 1;
  91        u8 antsel_rx_keep_2 : 1; /*ex_intf_flg:1;*/
  92#endif
  93};
  94
  95struct phy_status_rpt_8812 {
  96        /*      DWORD 0*/
  97        u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/
  98        u8 chl_num_LSB; /*channel number[7:0]*/
  99#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 100        u8 chl_num_MSB : 2; /*channel number[9:8]*/
 101        u8 sub_chnl : 4; /*sub-channel location[3:0]*/
 102        u8 r_RFMOD : 2; /*RF mode[1:0]*/
 103#else /*_BIG_ENDIAN_    */
 104        u8 r_RFMOD : 2;
 105        u8 sub_chnl : 4;
 106        u8 chl_num_MSB : 2;
 107#endif
 108
 109        /*      DWORD 1*/
 110        u8 pwdb_all; /*CCK signal quality / OFDM pwdb all*/
 111        s8 cfosho[2]; /*DW1 byte 1 DW1 byte2 */
 112/*CCK AGC report and CCK_BB_Power / OFDM path-A and path-B short CFO*/
 113#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 114        /*this should be checked again
 115         *because the definition of 8812 and 8814 is different
 116         */
 117        u8 resvd_0 : 6;
 118        u8 bt_RF_ch_MSB : 2; /*8812A:2'b0, 8814A: bt rf channel keep[7:6]*/
 119#else /*_BIG_ENDIAN_*/
 120        u8 bt_RF_ch_MSB : 2;
 121        u8 resvd_0 : 6;
 122#endif
 123
 124/*      DWORD 2*/
 125#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 126        u8 ant_div_sw_a : 1; /*8812A: ant_div_sw_a, 8814A: 1'b0*/
 127        u8 ant_div_sw_b : 1; /*8812A: ant_div_sw_b, 8814A: 1'b0*/
 128        u8 bt_RF_ch_LSB : 6; /*8812A: 6'b0, 8814A: bt rf channel keep[5:0]*/
 129#else /*_BIG_ENDIAN_    */
 130        u8 bt_RF_ch_LSB : 6;
 131        u8 ant_div_sw_b : 1;
 132        u8 ant_div_sw_a : 1;
 133#endif
 134        s8 cfotail[2]; /*DW2 byte 1 DW2 byte 2  path-A and path-B CFO tail*/
 135        u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/
 136        u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/
 137
 138        /*      DWORD 3*/
 139        s8 rxevm[2]; /*DW3 byte 1 DW3 byte 2    stream 1 and stream 2 RX EVM*/
 140        s8 rxsnr[2]; /*DW3 byte 3 DW4 byte 0    path-A and path-B RX SNR*/
 141
 142        /*      DWORD 4*/
 143        u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/
 144#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 145        u8 PCTS_MSK_RPT_3 : 6; /*PCTS mask report[29:24]*/
 146        u8 pcts_rpt_valid : 1; /*pcts_rpt_valid*/
 147        u8 resvd_1 : 1; /*1'b0*/
 148#else /*_BIG_ENDIAN_*/
 149        u8 resvd_1 : 1;
 150        u8 pcts_rpt_valid : 1;
 151        u8 PCTS_MSK_RPT_3 : 6;
 152#endif
 153        s8 rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 */
 154        /* 8812A: 16'b0, 8814A: stream 3 and stream 4 RX EVM*/
 155
 156        /*      DWORD 5*/
 157        u8 csi_current[2]; /*DW5 byte 1 DW5 byte 2 */
 158        /* 8812A: stream 1 and 2 CSI, 8814A: path-C and path-D RX SNR*/
 159        u8 gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 */
 160        /* path-C and path-D {TRSW, gain[6:0] }*/
 161
 162        /*      DWORD 6*/
 163        s8 sigevm; /*signal field EVM*/
 164#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 165        u8 antidx_antc : 3; /*8812A: 3'b0       8814A: antidx_antc[2:0]*/
 166        u8 antidx_antd : 3; /*8812A: 3'b0       8814A: antidx_antd[2:0]*/
 167        u8 dpdt_ctrl_keep : 1; /*8812A: 1'b0    8814A: dpdt_ctrl_keep*/
 168        u8 GNT_BT_keep : 1; /*8812A: 1'b0       8814A: GNT_BT_keep*/
 169#else /*_BIG_ENDIAN_*/
 170        u8 GNT_BT_keep : 1;
 171        u8 dpdt_ctrl_keep : 1;
 172        u8 antidx_antd : 3;
 173        u8 antidx_antc : 3;
 174#endif
 175#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 176        u8 antidx_anta : 3; /*antidx_anta[2:0]*/
 177        u8 antidx_antb : 3; /*antidx_antb[2:0]*/
 178        u8 hw_antsw_occur : 2; /*1'b0*/
 179#else /*_BIG_ENDIAN_*/
 180        u8 hw_antsw_occur : 2;
 181        u8 antidx_antb : 3;
 182        u8 antidx_anta : 3;
 183#endif
 184};
 185
 186void phydm_reset_rssi_for_dm(struct phy_dm_struct *dm, u8 station_id);
 187
 188void odm_init_rssi_for_dm(struct phy_dm_struct *dm);
 189
 190void odm_phy_status_query(struct phy_dm_struct *dm,
 191                          struct dm_phy_status_info *phy_info, u8 *phy_status,
 192                          struct dm_per_pkt_info *pktinfo);
 193
 194void odm_mac_status_query(struct phy_dm_struct *dm, u8 *mac_status, u8 mac_id,
 195                          bool is_packet_match_bssid, bool is_packet_to_self,
 196                          bool is_packet_beacon);
 197
 198enum hal_status
 199odm_config_rf_with_tx_pwr_track_header_file(struct phy_dm_struct *dm);
 200
 201enum hal_status
 202odm_config_rf_with_header_file(struct phy_dm_struct *dm,
 203                               enum odm_rf_config_type config_type,
 204                               enum odm_rf_radio_path e_rf_path);
 205
 206enum hal_status
 207odm_config_bb_with_header_file(struct phy_dm_struct *dm,
 208                               enum odm_bb_config_type config_type);
 209
 210enum hal_status odm_config_mac_with_header_file(struct phy_dm_struct *dm);
 211
 212enum hal_status
 213odm_config_fw_with_header_file(struct phy_dm_struct *dm,
 214                               enum odm_fw_config_type config_type,
 215                               u8 *p_firmware, u32 *size);
 216
 217u32 odm_get_hw_img_version(struct phy_dm_struct *dm);
 218
 219s32 odm_signal_scale_mapping(struct phy_dm_struct *dm, s32 curr_sig);
 220
 221/*For 8822B only!! need to move to FW finally */
 222/*==============================================*/
 223void phydm_rx_phy_status_new_type(struct phy_dm_struct *phydm, u8 *phy_status,
 224                                  struct dm_per_pkt_info *pktinfo,
 225                                  struct dm_phy_status_info *phy_info);
 226
 227bool phydm_query_is_mu_api(struct phy_dm_struct *phydm, u8 ppdu_idx,
 228                           u8 *p_data_rate, u8 *p_gid);
 229
 230struct phy_status_rpt_jaguar2_type0 {
 231        /* DW0 */
 232        u8 page_num;
 233        u8 pwdb;
 234#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 235        u8 gain : 6;
 236        u8 rsvd_0 : 1;
 237        u8 trsw : 1;
 238#else
 239        u8 trsw : 1;
 240        u8 rsvd_0 : 1;
 241        u8 gain : 6;
 242#endif
 243        u8 rsvd_1;
 244
 245        /* DW1 */
 246        u8 rsvd_2;
 247#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 248        u8 rxsc : 4;
 249        u8 agc_table : 4;
 250#else
 251        u8 agc_table : 4;
 252        u8 rxsc : 4;
 253#endif
 254        u8 channel;
 255        u8 band;
 256
 257        /* DW2 */
 258        u16 length;
 259#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 260        u8 antidx_a : 3;
 261        u8 antidx_b : 3;
 262        u8 rsvd_3 : 2;
 263        u8 antidx_c : 3;
 264        u8 antidx_d : 3;
 265        u8 rsvd_4 : 2;
 266#else
 267        u8 rsvd_3 : 2;
 268        u8 antidx_b : 3;
 269        u8 antidx_a : 3;
 270        u8 rsvd_4 : 2;
 271        u8 antidx_d : 3;
 272        u8 antidx_c : 3;
 273#endif
 274
 275        /* DW3 */
 276        u8 signal_quality;
 277#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 278        u8 vga : 5;
 279        u8 lna_l : 3;
 280        u8 bb_power : 6;
 281        u8 rsvd_9 : 1;
 282        u8 lna_h : 1;
 283#else
 284        u8 lna_l : 3;
 285        u8 vga : 5;
 286        u8 lna_h : 1;
 287        u8 rsvd_9 : 1;
 288        u8 bb_power : 6;
 289#endif
 290        u8 rsvd_5;
 291
 292        /* DW4 */
 293        u32 rsvd_6;
 294
 295        /* DW5 */
 296        u32 rsvd_7;
 297
 298        /* DW6 */
 299        u32 rsvd_8;
 300};
 301
 302struct phy_status_rpt_jaguar2_type1 {
 303        /* DW0 and DW1 */
 304        u8 page_num;
 305        u8 pwdb[4];
 306#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 307        u8 l_rxsc : 4;
 308        u8 ht_rxsc : 4;
 309#else
 310        u8 ht_rxsc : 4;
 311        u8 l_rxsc : 4;
 312#endif
 313        u8 channel;
 314#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 315        u8 band : 2;
 316        u8 rsvd_0 : 1;
 317        u8 hw_antsw_occu : 1;
 318        u8 gnt_bt : 1;
 319        u8 ldpc : 1;
 320        u8 stbc : 1;
 321        u8 beamformed : 1;
 322#else
 323        u8 beamformed : 1;
 324        u8 stbc : 1;
 325        u8 ldpc : 1;
 326        u8 gnt_bt : 1;
 327        u8 hw_antsw_occu : 1;
 328        u8 rsvd_0 : 1;
 329        u8 band : 2;
 330#endif
 331
 332        /* DW2 */
 333        u16 lsig_length;
 334#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 335        u8 antidx_a : 3;
 336        u8 antidx_b : 3;
 337        u8 rsvd_1 : 2;
 338        u8 antidx_c : 3;
 339        u8 antidx_d : 3;
 340        u8 rsvd_2 : 2;
 341#else
 342        u8 rsvd_1 : 2;
 343        u8 antidx_b : 3;
 344        u8 antidx_a : 3;
 345        u8 rsvd_2 : 2;
 346        u8 antidx_d : 3;
 347        u8 antidx_c : 3;
 348#endif
 349
 350        /* DW3 */
 351        u8 paid;
 352#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 353        u8 paid_msb : 1;
 354        u8 gid : 6;
 355        u8 rsvd_3 : 1;
 356#else
 357        u8 rsvd_3 : 1;
 358        u8 gid : 6;
 359        u8 paid_msb : 1;
 360#endif
 361        u8 intf_pos;
 362#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 363        u8 intf_pos_msb : 1;
 364        u8 rsvd_4 : 2;
 365        u8 nb_intf_flag : 1;
 366        u8 rf_mode : 2;
 367        u8 rsvd_5 : 2;
 368#else
 369        u8 rsvd_5 : 2;
 370        u8 rf_mode : 2;
 371        u8 nb_intf_flag : 1;
 372        u8 rsvd_4 : 2;
 373        u8 intf_pos_msb : 1;
 374#endif
 375
 376        /* DW4 */
 377        s8 rxevm[4]; /* s(8,1) */
 378
 379        /* DW5 */
 380        s8 cfo_tail[4]; /* s(8,7) */
 381
 382        /* DW6 */
 383        s8 rxsnr[4]; /* s(8,1) */
 384};
 385
 386struct phy_status_rpt_jaguar2_type2 {
 387        /* DW0 ane DW1 */
 388        u8 page_num;
 389        u8 pwdb[4];
 390#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 391        u8 l_rxsc : 4;
 392        u8 ht_rxsc : 4;
 393#else
 394        u8 ht_rxsc : 4;
 395        u8 l_rxsc : 4;
 396#endif
 397        u8 channel;
 398#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 399        u8 band : 2;
 400        u8 rsvd_0 : 1;
 401        u8 hw_antsw_occu : 1;
 402        u8 gnt_bt : 1;
 403        u8 ldpc : 1;
 404        u8 stbc : 1;
 405        u8 beamformed : 1;
 406#else
 407        u8 beamformed : 1;
 408        u8 stbc : 1;
 409        u8 ldpc : 1;
 410        u8 gnt_bt : 1;
 411        u8 hw_antsw_occu : 1;
 412        u8 rsvd_0 : 1;
 413        u8 band : 2;
 414#endif
 415
 416/* DW2 */
 417#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 418        u8 shift_l_map : 6;
 419        u8 rsvd_1 : 2;
 420#else
 421        u8 rsvd_1 : 2;
 422        u8 shift_l_map : 6;
 423#endif
 424        u8 cnt_pw2cca;
 425#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 426        u8 agc_table_a : 4;
 427        u8 agc_table_b : 4;
 428        u8 agc_table_c : 4;
 429        u8 agc_table_d : 4;
 430#else
 431        u8 agc_table_b : 4;
 432        u8 agc_table_a : 4;
 433        u8 agc_table_d : 4;
 434        u8 agc_table_c : 4;
 435#endif
 436
 437        /* DW3 ~ DW6*/
 438        u8 cnt_cca2agc_rdy;
 439#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 440        u8 gain_a : 6;
 441        u8 rsvd_2 : 1;
 442        u8 trsw_a : 1;
 443        u8 gain_b : 6;
 444        u8 rsvd_3 : 1;
 445        u8 trsw_b : 1;
 446        u8 gain_c : 6;
 447        u8 rsvd_4 : 1;
 448        u8 trsw_c : 1;
 449        u8 gain_d : 6;
 450        u8 rsvd_5 : 1;
 451        u8 trsw_d : 1;
 452        u8 aagc_step_a : 2;
 453        u8 aagc_step_b : 2;
 454        u8 aagc_step_c : 2;
 455        u8 aagc_step_d : 2;
 456#else
 457        u8 trsw_a : 1;
 458        u8 rsvd_2 : 1;
 459        u8 gain_a : 6;
 460        u8 trsw_b : 1;
 461        u8 rsvd_3 : 1;
 462        u8 gain_b : 6;
 463        u8 trsw_c : 1;
 464        u8 rsvd_4 : 1;
 465        u8 gain_c : 6;
 466        u8 trsw_d : 1;
 467        u8 rsvd_5 : 1;
 468        u8 gain_d : 6;
 469        u8 aagc_step_d : 2;
 470        u8 aagc_step_c : 2;
 471        u8 aagc_step_b : 2;
 472        u8 aagc_step_a : 2;
 473#endif
 474        u8 ht_aagc_gain[4];
 475        u8 dagc_gain[4];
 476#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 477        u8 counter : 6;
 478        u8 rsvd_6 : 2;
 479        u8 syn_count : 5;
 480        u8 rsvd_7 : 3;
 481#else
 482        u8 rsvd_6 : 2;
 483        u8 counter : 6;
 484        u8 rsvd_7 : 3;
 485        u8 syn_count : 5;
 486#endif
 487};
 488
 489u32 query_phydm_trx_capability(struct phy_dm_struct *dm);
 490
 491u32 query_phydm_stbc_capability(struct phy_dm_struct *dm);
 492
 493u32 query_phydm_ldpc_capability(struct phy_dm_struct *dm);
 494
 495u32 query_phydm_txbf_parameters(struct phy_dm_struct *dm);
 496
 497u32 query_phydm_txbf_capability(struct phy_dm_struct *dm);
 498
 499#endif /*#ifndef        __HALHWOUTSRC_H__*/
 500