linux/drivers/tty/synclink_gt.c
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   1// SPDX-License-Identifier: GPL-1.0+
   2/*
   3 * Device driver for Microgate SyncLink GT serial adapters.
   4 *
   5 * written by Paul Fulghum for Microgate Corporation
   6 * paulkf@microgate.com
   7 *
   8 * Microgate and SyncLink are trademarks of Microgate Corporation
   9 *
  10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  13 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  20 * OF THE POSSIBILITY OF SUCH DAMAGE.
  21 */
  22
  23/*
  24 * DEBUG OUTPUT DEFINITIONS
  25 *
  26 * uncomment lines below to enable specific types of debug output
  27 *
  28 * DBGINFO   information - most verbose output
  29 * DBGERR    serious errors
  30 * DBGBH     bottom half service routine debugging
  31 * DBGISR    interrupt service routine debugging
  32 * DBGDATA   output receive and transmit data
  33 * DBGTBUF   output transmit DMA buffers and registers
  34 * DBGRBUF   output receive DMA buffers and registers
  35 */
  36
  37#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  38#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  39#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  40#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  41#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  42/*#define DBGTBUF(info) dump_tbufs(info)*/
  43/*#define DBGRBUF(info) dump_rbufs(info)*/
  44
  45
  46#include <linux/module.h>
  47#include <linux/errno.h>
  48#include <linux/signal.h>
  49#include <linux/sched.h>
  50#include <linux/timer.h>
  51#include <linux/interrupt.h>
  52#include <linux/pci.h>
  53#include <linux/tty.h>
  54#include <linux/tty_flip.h>
  55#include <linux/serial.h>
  56#include <linux/major.h>
  57#include <linux/string.h>
  58#include <linux/fcntl.h>
  59#include <linux/ptrace.h>
  60#include <linux/ioport.h>
  61#include <linux/mm.h>
  62#include <linux/seq_file.h>
  63#include <linux/slab.h>
  64#include <linux/netdevice.h>
  65#include <linux/vmalloc.h>
  66#include <linux/init.h>
  67#include <linux/delay.h>
  68#include <linux/ioctl.h>
  69#include <linux/termios.h>
  70#include <linux/bitops.h>
  71#include <linux/workqueue.h>
  72#include <linux/hdlc.h>
  73#include <linux/synclink.h>
  74
  75#include <asm/io.h>
  76#include <asm/irq.h>
  77#include <asm/dma.h>
  78#include <asm/types.h>
  79#include <linux/uaccess.h>
  80
  81#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  82#define SYNCLINK_GENERIC_HDLC 1
  83#else
  84#define SYNCLINK_GENERIC_HDLC 0
  85#endif
  86
  87/*
  88 * module identification
  89 */
  90static char *driver_name     = "SyncLink GT";
  91static char *slgt_driver_name = "synclink_gt";
  92static char *tty_dev_prefix  = "ttySLG";
  93MODULE_LICENSE("GPL");
  94#define MGSL_MAGIC 0x5401
  95#define MAX_DEVICES 32
  96
  97static const struct pci_device_id pci_table[] = {
  98        {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  99        {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 100        {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 101        {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102        {0,}, /* terminate list */
 103};
 104MODULE_DEVICE_TABLE(pci, pci_table);
 105
 106static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 107static void remove_one(struct pci_dev *dev);
 108static struct pci_driver pci_driver = {
 109        .name           = "synclink_gt",
 110        .id_table       = pci_table,
 111        .probe          = init_one,
 112        .remove         = remove_one,
 113};
 114
 115static bool pci_registered;
 116
 117/*
 118 * module configuration and status
 119 */
 120static struct slgt_info *slgt_device_list;
 121static int slgt_device_count;
 122
 123static int ttymajor;
 124static int debug_level;
 125static int maxframe[MAX_DEVICES];
 126
 127module_param(ttymajor, int, 0);
 128module_param(debug_level, int, 0);
 129module_param_array(maxframe, int, NULL, 0);
 130
 131MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 132MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 133MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 134
 135/*
 136 * tty support and callbacks
 137 */
 138static struct tty_driver *serial_driver;
 139
 140static int  open(struct tty_struct *tty, struct file * filp);
 141static void close(struct tty_struct *tty, struct file * filp);
 142static void hangup(struct tty_struct *tty);
 143static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 144
 145static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 146static int put_char(struct tty_struct *tty, unsigned char ch);
 147static void send_xchar(struct tty_struct *tty, char ch);
 148static void wait_until_sent(struct tty_struct *tty, int timeout);
 149static int  write_room(struct tty_struct *tty);
 150static void flush_chars(struct tty_struct *tty);
 151static void flush_buffer(struct tty_struct *tty);
 152static void tx_hold(struct tty_struct *tty);
 153static void tx_release(struct tty_struct *tty);
 154
 155static int  ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
 156static int  chars_in_buffer(struct tty_struct *tty);
 157static void throttle(struct tty_struct * tty);
 158static void unthrottle(struct tty_struct * tty);
 159static int set_break(struct tty_struct *tty, int break_state);
 160
 161/*
 162 * generic HDLC support and callbacks
 163 */
 164#if SYNCLINK_GENERIC_HDLC
 165#define dev_to_port(D) (dev_to_hdlc(D)->priv)
 166static void hdlcdev_tx_done(struct slgt_info *info);
 167static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 168static int  hdlcdev_init(struct slgt_info *info);
 169static void hdlcdev_exit(struct slgt_info *info);
 170#endif
 171
 172
 173/*
 174 * device specific structures, macros and functions
 175 */
 176
 177#define SLGT_MAX_PORTS 4
 178#define SLGT_REG_SIZE  256
 179
 180/*
 181 * conditional wait facility
 182 */
 183struct cond_wait {
 184        struct cond_wait *next;
 185        wait_queue_head_t q;
 186        wait_queue_entry_t wait;
 187        unsigned int data;
 188};
 189static void init_cond_wait(struct cond_wait *w, unsigned int data);
 190static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 191static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 192static void flush_cond_wait(struct cond_wait **head);
 193
 194/*
 195 * DMA buffer descriptor and access macros
 196 */
 197struct slgt_desc
 198{
 199        __le16 count;
 200        __le16 status;
 201        __le32 pbuf;  /* physical address of data buffer */
 202        __le32 next;  /* physical address of next descriptor */
 203
 204        /* driver book keeping */
 205        char *buf;          /* virtual  address of data buffer */
 206        unsigned int pdesc; /* physical address of this descriptor */
 207        dma_addr_t buf_dma_addr;
 208        unsigned short buf_count;
 209};
 210
 211#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 212#define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 213#define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 214#define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 215#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 216#define desc_count(a)      (le16_to_cpu((a).count))
 217#define desc_status(a)     (le16_to_cpu((a).status))
 218#define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 219#define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 220#define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 221#define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 222#define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 223
 224struct _input_signal_events {
 225        int ri_up;
 226        int ri_down;
 227        int dsr_up;
 228        int dsr_down;
 229        int dcd_up;
 230        int dcd_down;
 231        int cts_up;
 232        int cts_down;
 233};
 234
 235/*
 236 * device instance data structure
 237 */
 238struct slgt_info {
 239        void *if_ptr;           /* General purpose pointer (used by SPPP) */
 240        struct tty_port port;
 241
 242        struct slgt_info *next_device;  /* device list link */
 243
 244        int magic;
 245
 246        char device_name[25];
 247        struct pci_dev *pdev;
 248
 249        int port_count;  /* count of ports on adapter */
 250        int adapter_num; /* adapter instance number */
 251        int port_num;    /* port instance number */
 252
 253        /* array of pointers to port contexts on this adapter */
 254        struct slgt_info *port_array[SLGT_MAX_PORTS];
 255
 256        int                     line;           /* tty line instance number */
 257
 258        struct mgsl_icount      icount;
 259
 260        int                     timeout;
 261        int                     x_char;         /* xon/xoff character */
 262        unsigned int            read_status_mask;
 263        unsigned int            ignore_status_mask;
 264
 265        wait_queue_head_t       status_event_wait_q;
 266        wait_queue_head_t       event_wait_q;
 267        struct timer_list       tx_timer;
 268        struct timer_list       rx_timer;
 269
 270        unsigned int            gpio_present;
 271        struct cond_wait        *gpio_wait_q;
 272
 273        spinlock_t lock;        /* spinlock for synchronizing with ISR */
 274
 275        struct work_struct task;
 276        u32 pending_bh;
 277        bool bh_requested;
 278        bool bh_running;
 279
 280        int isr_overflow;
 281        bool irq_requested;     /* true if IRQ requested */
 282        bool irq_occurred;      /* for diagnostics use */
 283
 284        /* device configuration */
 285
 286        unsigned int bus_type;
 287        unsigned int irq_level;
 288        unsigned long irq_flags;
 289
 290        unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 291        u32 phys_reg_addr;
 292        bool reg_addr_requested;
 293
 294        MGSL_PARAMS params;       /* communications parameters */
 295        u32 idle_mode;
 296        u32 max_frame_size;       /* as set by device config */
 297
 298        unsigned int rbuf_fill_level;
 299        unsigned int rx_pio;
 300        unsigned int if_mode;
 301        unsigned int base_clock;
 302        unsigned int xsync;
 303        unsigned int xctrl;
 304
 305        /* device status */
 306
 307        bool rx_enabled;
 308        bool rx_restart;
 309
 310        bool tx_enabled;
 311        bool tx_active;
 312
 313        unsigned char signals;    /* serial signal states */
 314        int init_error;  /* initialization error */
 315
 316        unsigned char *tx_buf;
 317        int tx_count;
 318
 319        char *flag_buf;
 320        bool drop_rts_on_tx_done;
 321        struct  _input_signal_events    input_signal_events;
 322
 323        int dcd_chkcount;       /* check counts to prevent */
 324        int cts_chkcount;       /* too many IRQs if a signal */
 325        int dsr_chkcount;       /* is floating */
 326        int ri_chkcount;
 327
 328        char *bufs;             /* virtual address of DMA buffer lists */
 329        dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 330
 331        unsigned int rbuf_count;
 332        struct slgt_desc *rbufs;
 333        unsigned int rbuf_current;
 334        unsigned int rbuf_index;
 335        unsigned int rbuf_fill_index;
 336        unsigned short rbuf_fill_count;
 337
 338        unsigned int tbuf_count;
 339        struct slgt_desc *tbufs;
 340        unsigned int tbuf_current;
 341        unsigned int tbuf_start;
 342
 343        unsigned char *tmp_rbuf;
 344        unsigned int tmp_rbuf_count;
 345
 346        /* SPPP/Cisco HDLC device parts */
 347
 348        int netcount;
 349        spinlock_t netlock;
 350#if SYNCLINK_GENERIC_HDLC
 351        struct net_device *netdev;
 352#endif
 353
 354};
 355
 356static MGSL_PARAMS default_params = {
 357        .mode            = MGSL_MODE_HDLC,
 358        .loopback        = 0,
 359        .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 360        .encoding        = HDLC_ENCODING_NRZI_SPACE,
 361        .clock_speed     = 0,
 362        .addr_filter     = 0xff,
 363        .crc_type        = HDLC_CRC_16_CCITT,
 364        .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 365        .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 366        .data_rate       = 9600,
 367        .data_bits       = 8,
 368        .stop_bits       = 1,
 369        .parity          = ASYNC_PARITY_NONE
 370};
 371
 372
 373#define BH_RECEIVE  1
 374#define BH_TRANSMIT 2
 375#define BH_STATUS   4
 376#define IO_PIN_SHUTDOWN_LIMIT 100
 377
 378#define DMABUFSIZE 256
 379#define DESC_LIST_SIZE 4096
 380
 381#define MASK_PARITY  BIT1
 382#define MASK_FRAMING BIT0
 383#define MASK_BREAK   BIT14
 384#define MASK_OVERRUN BIT4
 385
 386#define GSR   0x00 /* global status */
 387#define JCR   0x04 /* JTAG control */
 388#define IODR  0x08 /* GPIO direction */
 389#define IOER  0x0c /* GPIO interrupt enable */
 390#define IOVR  0x10 /* GPIO value */
 391#define IOSR  0x14 /* GPIO interrupt status */
 392#define TDR   0x80 /* tx data */
 393#define RDR   0x80 /* rx data */
 394#define TCR   0x82 /* tx control */
 395#define TIR   0x84 /* tx idle */
 396#define TPR   0x85 /* tx preamble */
 397#define RCR   0x86 /* rx control */
 398#define VCR   0x88 /* V.24 control */
 399#define CCR   0x89 /* clock control */
 400#define BDR   0x8a /* baud divisor */
 401#define SCR   0x8c /* serial control */
 402#define SSR   0x8e /* serial status */
 403#define RDCSR 0x90 /* rx DMA control/status */
 404#define TDCSR 0x94 /* tx DMA control/status */
 405#define RDDAR 0x98 /* rx DMA descriptor address */
 406#define TDDAR 0x9c /* tx DMA descriptor address */
 407#define XSR   0x40 /* extended sync pattern */
 408#define XCR   0x44 /* extended control */
 409
 410#define RXIDLE      BIT14
 411#define RXBREAK     BIT14
 412#define IRQ_TXDATA  BIT13
 413#define IRQ_TXIDLE  BIT12
 414#define IRQ_TXUNDER BIT11 /* HDLC */
 415#define IRQ_RXDATA  BIT10
 416#define IRQ_RXIDLE  BIT9  /* HDLC */
 417#define IRQ_RXBREAK BIT9  /* async */
 418#define IRQ_RXOVER  BIT8
 419#define IRQ_DSR     BIT7
 420#define IRQ_CTS     BIT6
 421#define IRQ_DCD     BIT5
 422#define IRQ_RI      BIT4
 423#define IRQ_ALL     0x3ff0
 424#define IRQ_MASTER  BIT0
 425
 426#define slgt_irq_on(info, mask) \
 427        wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 428#define slgt_irq_off(info, mask) \
 429        wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 430
 431static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 432static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 433static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 434static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 435static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 436static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 437
 438static void  msc_set_vcr(struct slgt_info *info);
 439
 440static int  startup(struct slgt_info *info);
 441static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 442static void shutdown(struct slgt_info *info);
 443static void program_hw(struct slgt_info *info);
 444static void change_params(struct slgt_info *info);
 445
 446static int  register_test(struct slgt_info *info);
 447static int  irq_test(struct slgt_info *info);
 448static int  loopback_test(struct slgt_info *info);
 449static int  adapter_test(struct slgt_info *info);
 450
 451static void reset_adapter(struct slgt_info *info);
 452static void reset_port(struct slgt_info *info);
 453static void async_mode(struct slgt_info *info);
 454static void sync_mode(struct slgt_info *info);
 455
 456static void rx_stop(struct slgt_info *info);
 457static void rx_start(struct slgt_info *info);
 458static void reset_rbufs(struct slgt_info *info);
 459static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 460static void rdma_reset(struct slgt_info *info);
 461static bool rx_get_frame(struct slgt_info *info);
 462static bool rx_get_buf(struct slgt_info *info);
 463
 464static void tx_start(struct slgt_info *info);
 465static void tx_stop(struct slgt_info *info);
 466static void tx_set_idle(struct slgt_info *info);
 467static unsigned int free_tbuf_count(struct slgt_info *info);
 468static unsigned int tbuf_bytes(struct slgt_info *info);
 469static void reset_tbufs(struct slgt_info *info);
 470static void tdma_reset(struct slgt_info *info);
 471static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 472
 473static void get_signals(struct slgt_info *info);
 474static void set_signals(struct slgt_info *info);
 475static void enable_loopback(struct slgt_info *info);
 476static void set_rate(struct slgt_info *info, u32 data_rate);
 477
 478static int  bh_action(struct slgt_info *info);
 479static void bh_handler(struct work_struct *work);
 480static void bh_transmit(struct slgt_info *info);
 481static void isr_serial(struct slgt_info *info);
 482static void isr_rdma(struct slgt_info *info);
 483static void isr_txeom(struct slgt_info *info, unsigned short status);
 484static void isr_tdma(struct slgt_info *info);
 485
 486static int  alloc_dma_bufs(struct slgt_info *info);
 487static void free_dma_bufs(struct slgt_info *info);
 488static int  alloc_desc(struct slgt_info *info);
 489static void free_desc(struct slgt_info *info);
 490static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 491static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 492
 493static int  alloc_tmp_rbuf(struct slgt_info *info);
 494static void free_tmp_rbuf(struct slgt_info *info);
 495
 496static void tx_timeout(struct timer_list *t);
 497static void rx_timeout(struct timer_list *t);
 498
 499/*
 500 * ioctl handlers
 501 */
 502static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 503static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 504static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 505static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 506static int  set_txidle(struct slgt_info *info, int idle_mode);
 507static int  tx_enable(struct slgt_info *info, int enable);
 508static int  tx_abort(struct slgt_info *info);
 509static int  rx_enable(struct slgt_info *info, int enable);
 510static int  modem_input_wait(struct slgt_info *info,int arg);
 511static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 512static int  tiocmget(struct tty_struct *tty);
 513static int  tiocmset(struct tty_struct *tty,
 514                                unsigned int set, unsigned int clear);
 515static int set_break(struct tty_struct *tty, int break_state);
 516static int  get_interface(struct slgt_info *info, int __user *if_mode);
 517static int  set_interface(struct slgt_info *info, int if_mode);
 518static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 519static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 520static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 521static int  get_xsync(struct slgt_info *info, int __user *if_mode);
 522static int  set_xsync(struct slgt_info *info, int if_mode);
 523static int  get_xctrl(struct slgt_info *info, int __user *if_mode);
 524static int  set_xctrl(struct slgt_info *info, int if_mode);
 525
 526/*
 527 * driver functions
 528 */
 529static void add_device(struct slgt_info *info);
 530static void device_init(int adapter_num, struct pci_dev *pdev);
 531static int  claim_resources(struct slgt_info *info);
 532static void release_resources(struct slgt_info *info);
 533
 534/*
 535 * DEBUG OUTPUT CODE
 536 */
 537#ifndef DBGINFO
 538#define DBGINFO(fmt)
 539#endif
 540#ifndef DBGERR
 541#define DBGERR(fmt)
 542#endif
 543#ifndef DBGBH
 544#define DBGBH(fmt)
 545#endif
 546#ifndef DBGISR
 547#define DBGISR(fmt)
 548#endif
 549
 550#ifdef DBGDATA
 551static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 552{
 553        int i;
 554        int linecount;
 555        printk("%s %s data:\n",info->device_name, label);
 556        while(count) {
 557                linecount = (count > 16) ? 16 : count;
 558                for(i=0; i < linecount; i++)
 559                        printk("%02X ",(unsigned char)data[i]);
 560                for(;i<17;i++)
 561                        printk("   ");
 562                for(i=0;i<linecount;i++) {
 563                        if (data[i]>=040 && data[i]<=0176)
 564                                printk("%c",data[i]);
 565                        else
 566                                printk(".");
 567                }
 568                printk("\n");
 569                data  += linecount;
 570                count -= linecount;
 571        }
 572}
 573#else
 574#define DBGDATA(info, buf, size, label)
 575#endif
 576
 577#ifdef DBGTBUF
 578static void dump_tbufs(struct slgt_info *info)
 579{
 580        int i;
 581        printk("tbuf_current=%d\n", info->tbuf_current);
 582        for (i=0 ; i < info->tbuf_count ; i++) {
 583                printk("%d: count=%04X status=%04X\n",
 584                        i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 585        }
 586}
 587#else
 588#define DBGTBUF(info)
 589#endif
 590
 591#ifdef DBGRBUF
 592static void dump_rbufs(struct slgt_info *info)
 593{
 594        int i;
 595        printk("rbuf_current=%d\n", info->rbuf_current);
 596        for (i=0 ; i < info->rbuf_count ; i++) {
 597                printk("%d: count=%04X status=%04X\n",
 598                        i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 599        }
 600}
 601#else
 602#define DBGRBUF(info)
 603#endif
 604
 605static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 606{
 607#ifdef SANITY_CHECK
 608        if (!info) {
 609                printk("null struct slgt_info for (%s) in %s\n", devname, name);
 610                return 1;
 611        }
 612        if (info->magic != MGSL_MAGIC) {
 613                printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 614                return 1;
 615        }
 616#else
 617        if (!info)
 618                return 1;
 619#endif
 620        return 0;
 621}
 622
 623/**
 624 * line discipline callback wrappers
 625 *
 626 * The wrappers maintain line discipline references
 627 * while calling into the line discipline.
 628 *
 629 * ldisc_receive_buf  - pass receive data to line discipline
 630 */
 631static void ldisc_receive_buf(struct tty_struct *tty,
 632                              const __u8 *data, char *flags, int count)
 633{
 634        struct tty_ldisc *ld;
 635        if (!tty)
 636                return;
 637        ld = tty_ldisc_ref(tty);
 638        if (ld) {
 639                if (ld->ops->receive_buf)
 640                        ld->ops->receive_buf(tty, data, flags, count);
 641                tty_ldisc_deref(ld);
 642        }
 643}
 644
 645/* tty callbacks */
 646
 647static int open(struct tty_struct *tty, struct file *filp)
 648{
 649        struct slgt_info *info;
 650        int retval, line;
 651        unsigned long flags;
 652
 653        line = tty->index;
 654        if (line >= slgt_device_count) {
 655                DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 656                return -ENODEV;
 657        }
 658
 659        info = slgt_device_list;
 660        while(info && info->line != line)
 661                info = info->next_device;
 662        if (sanity_check(info, tty->name, "open"))
 663                return -ENODEV;
 664        if (info->init_error) {
 665                DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 666                return -ENODEV;
 667        }
 668
 669        tty->driver_data = info;
 670        info->port.tty = tty;
 671
 672        DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 673
 674        mutex_lock(&info->port.mutex);
 675        info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 676
 677        spin_lock_irqsave(&info->netlock, flags);
 678        if (info->netcount) {
 679                retval = -EBUSY;
 680                spin_unlock_irqrestore(&info->netlock, flags);
 681                mutex_unlock(&info->port.mutex);
 682                goto cleanup;
 683        }
 684        info->port.count++;
 685        spin_unlock_irqrestore(&info->netlock, flags);
 686
 687        if (info->port.count == 1) {
 688                /* 1st open on this device, init hardware */
 689                retval = startup(info);
 690                if (retval < 0) {
 691                        mutex_unlock(&info->port.mutex);
 692                        goto cleanup;
 693                }
 694        }
 695        mutex_unlock(&info->port.mutex);
 696        retval = block_til_ready(tty, filp, info);
 697        if (retval) {
 698                DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 699                goto cleanup;
 700        }
 701
 702        retval = 0;
 703
 704cleanup:
 705        if (retval) {
 706                if (tty->count == 1)
 707                        info->port.tty = NULL; /* tty layer will release tty struct */
 708                if(info->port.count)
 709                        info->port.count--;
 710        }
 711
 712        DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 713        return retval;
 714}
 715
 716static void close(struct tty_struct *tty, struct file *filp)
 717{
 718        struct slgt_info *info = tty->driver_data;
 719
 720        if (sanity_check(info, tty->name, "close"))
 721                return;
 722        DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 723
 724        if (tty_port_close_start(&info->port, tty, filp) == 0)
 725                goto cleanup;
 726
 727        mutex_lock(&info->port.mutex);
 728        if (tty_port_initialized(&info->port))
 729                wait_until_sent(tty, info->timeout);
 730        flush_buffer(tty);
 731        tty_ldisc_flush(tty);
 732
 733        shutdown(info);
 734        mutex_unlock(&info->port.mutex);
 735
 736        tty_port_close_end(&info->port, tty);
 737        info->port.tty = NULL;
 738cleanup:
 739        DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 740}
 741
 742static void hangup(struct tty_struct *tty)
 743{
 744        struct slgt_info *info = tty->driver_data;
 745        unsigned long flags;
 746
 747        if (sanity_check(info, tty->name, "hangup"))
 748                return;
 749        DBGINFO(("%s hangup\n", info->device_name));
 750
 751        flush_buffer(tty);
 752
 753        mutex_lock(&info->port.mutex);
 754        shutdown(info);
 755
 756        spin_lock_irqsave(&info->port.lock, flags);
 757        info->port.count = 0;
 758        info->port.tty = NULL;
 759        spin_unlock_irqrestore(&info->port.lock, flags);
 760        tty_port_set_active(&info->port, 0);
 761        mutex_unlock(&info->port.mutex);
 762
 763        wake_up_interruptible(&info->port.open_wait);
 764}
 765
 766static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 767{
 768        struct slgt_info *info = tty->driver_data;
 769        unsigned long flags;
 770
 771        DBGINFO(("%s set_termios\n", tty->driver->name));
 772
 773        change_params(info);
 774
 775        /* Handle transition to B0 status */
 776        if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
 777                info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
 778                spin_lock_irqsave(&info->lock,flags);
 779                set_signals(info);
 780                spin_unlock_irqrestore(&info->lock,flags);
 781        }
 782
 783        /* Handle transition away from B0 status */
 784        if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
 785                info->signals |= SerialSignal_DTR;
 786                if (!C_CRTSCTS(tty) || !tty_throttled(tty))
 787                        info->signals |= SerialSignal_RTS;
 788                spin_lock_irqsave(&info->lock,flags);
 789                set_signals(info);
 790                spin_unlock_irqrestore(&info->lock,flags);
 791        }
 792
 793        /* Handle turning off CRTSCTS */
 794        if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
 795                tty->hw_stopped = 0;
 796                tx_release(tty);
 797        }
 798}
 799
 800static void update_tx_timer(struct slgt_info *info)
 801{
 802        /*
 803         * use worst case speed of 1200bps to calculate transmit timeout
 804         * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
 805         */
 806        if (info->params.mode == MGSL_MODE_HDLC) {
 807                int timeout  = (tbuf_bytes(info) * 7) + 1000;
 808                mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
 809        }
 810}
 811
 812static int write(struct tty_struct *tty,
 813                 const unsigned char *buf, int count)
 814{
 815        int ret = 0;
 816        struct slgt_info *info = tty->driver_data;
 817        unsigned long flags;
 818
 819        if (sanity_check(info, tty->name, "write"))
 820                return -EIO;
 821
 822        DBGINFO(("%s write count=%d\n", info->device_name, count));
 823
 824        if (!info->tx_buf || (count > info->max_frame_size))
 825                return -EIO;
 826
 827        if (!count || tty->stopped || tty->hw_stopped)
 828                return 0;
 829
 830        spin_lock_irqsave(&info->lock, flags);
 831
 832        if (info->tx_count) {
 833                /* send accumulated data from send_char() */
 834                if (!tx_load(info, info->tx_buf, info->tx_count))
 835                        goto cleanup;
 836                info->tx_count = 0;
 837        }
 838
 839        if (tx_load(info, buf, count))
 840                ret = count;
 841
 842cleanup:
 843        spin_unlock_irqrestore(&info->lock, flags);
 844        DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 845        return ret;
 846}
 847
 848static int put_char(struct tty_struct *tty, unsigned char ch)
 849{
 850        struct slgt_info *info = tty->driver_data;
 851        unsigned long flags;
 852        int ret = 0;
 853
 854        if (sanity_check(info, tty->name, "put_char"))
 855                return 0;
 856        DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 857        if (!info->tx_buf)
 858                return 0;
 859        spin_lock_irqsave(&info->lock,flags);
 860        if (info->tx_count < info->max_frame_size) {
 861                info->tx_buf[info->tx_count++] = ch;
 862                ret = 1;
 863        }
 864        spin_unlock_irqrestore(&info->lock,flags);
 865        return ret;
 866}
 867
 868static void send_xchar(struct tty_struct *tty, char ch)
 869{
 870        struct slgt_info *info = tty->driver_data;
 871        unsigned long flags;
 872
 873        if (sanity_check(info, tty->name, "send_xchar"))
 874                return;
 875        DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 876        info->x_char = ch;
 877        if (ch) {
 878                spin_lock_irqsave(&info->lock,flags);
 879                if (!info->tx_enabled)
 880                        tx_start(info);
 881                spin_unlock_irqrestore(&info->lock,flags);
 882        }
 883}
 884
 885static void wait_until_sent(struct tty_struct *tty, int timeout)
 886{
 887        struct slgt_info *info = tty->driver_data;
 888        unsigned long orig_jiffies, char_time;
 889
 890        if (!info )
 891                return;
 892        if (sanity_check(info, tty->name, "wait_until_sent"))
 893                return;
 894        DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 895        if (!tty_port_initialized(&info->port))
 896                goto exit;
 897
 898        orig_jiffies = jiffies;
 899
 900        /* Set check interval to 1/5 of estimated time to
 901         * send a character, and make it at least 1. The check
 902         * interval should also be less than the timeout.
 903         * Note: use tight timings here to satisfy the NIST-PCTS.
 904         */
 905
 906        if (info->params.data_rate) {
 907                char_time = info->timeout/(32 * 5);
 908                if (!char_time)
 909                        char_time++;
 910        } else
 911                char_time = 1;
 912
 913        if (timeout)
 914                char_time = min_t(unsigned long, char_time, timeout);
 915
 916        while (info->tx_active) {
 917                msleep_interruptible(jiffies_to_msecs(char_time));
 918                if (signal_pending(current))
 919                        break;
 920                if (timeout && time_after(jiffies, orig_jiffies + timeout))
 921                        break;
 922        }
 923exit:
 924        DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 925}
 926
 927static int write_room(struct tty_struct *tty)
 928{
 929        struct slgt_info *info = tty->driver_data;
 930        int ret;
 931
 932        if (sanity_check(info, tty->name, "write_room"))
 933                return 0;
 934        ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 935        DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 936        return ret;
 937}
 938
 939static void flush_chars(struct tty_struct *tty)
 940{
 941        struct slgt_info *info = tty->driver_data;
 942        unsigned long flags;
 943
 944        if (sanity_check(info, tty->name, "flush_chars"))
 945                return;
 946        DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 947
 948        if (info->tx_count <= 0 || tty->stopped ||
 949            tty->hw_stopped || !info->tx_buf)
 950                return;
 951
 952        DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 953
 954        spin_lock_irqsave(&info->lock,flags);
 955        if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 956                info->tx_count = 0;
 957        spin_unlock_irqrestore(&info->lock,flags);
 958}
 959
 960static void flush_buffer(struct tty_struct *tty)
 961{
 962        struct slgt_info *info = tty->driver_data;
 963        unsigned long flags;
 964
 965        if (sanity_check(info, tty->name, "flush_buffer"))
 966                return;
 967        DBGINFO(("%s flush_buffer\n", info->device_name));
 968
 969        spin_lock_irqsave(&info->lock, flags);
 970        info->tx_count = 0;
 971        spin_unlock_irqrestore(&info->lock, flags);
 972
 973        tty_wakeup(tty);
 974}
 975
 976/*
 977 * throttle (stop) transmitter
 978 */
 979static void tx_hold(struct tty_struct *tty)
 980{
 981        struct slgt_info *info = tty->driver_data;
 982        unsigned long flags;
 983
 984        if (sanity_check(info, tty->name, "tx_hold"))
 985                return;
 986        DBGINFO(("%s tx_hold\n", info->device_name));
 987        spin_lock_irqsave(&info->lock,flags);
 988        if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
 989                tx_stop(info);
 990        spin_unlock_irqrestore(&info->lock,flags);
 991}
 992
 993/*
 994 * release (start) transmitter
 995 */
 996static void tx_release(struct tty_struct *tty)
 997{
 998        struct slgt_info *info = tty->driver_data;
 999        unsigned long flags;
1000
1001        if (sanity_check(info, tty->name, "tx_release"))
1002                return;
1003        DBGINFO(("%s tx_release\n", info->device_name));
1004        spin_lock_irqsave(&info->lock, flags);
1005        if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1006                info->tx_count = 0;
1007        spin_unlock_irqrestore(&info->lock, flags);
1008}
1009
1010/*
1011 * Service an IOCTL request
1012 *
1013 * Arguments
1014 *
1015 *      tty     pointer to tty instance data
1016 *      cmd     IOCTL command code
1017 *      arg     command argument/context
1018 *
1019 * Return 0 if success, otherwise error code
1020 */
1021static int ioctl(struct tty_struct *tty,
1022                 unsigned int cmd, unsigned long arg)
1023{
1024        struct slgt_info *info = tty->driver_data;
1025        void __user *argp = (void __user *)arg;
1026        int ret;
1027
1028        if (sanity_check(info, tty->name, "ioctl"))
1029                return -ENODEV;
1030        DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1031
1032        if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1033            (cmd != TIOCMIWAIT)) {
1034                if (tty_io_error(tty))
1035                    return -EIO;
1036        }
1037
1038        switch (cmd) {
1039        case MGSL_IOCWAITEVENT:
1040                return wait_mgsl_event(info, argp);
1041        case TIOCMIWAIT:
1042                return modem_input_wait(info,(int)arg);
1043        case MGSL_IOCSGPIO:
1044                return set_gpio(info, argp);
1045        case MGSL_IOCGGPIO:
1046                return get_gpio(info, argp);
1047        case MGSL_IOCWAITGPIO:
1048                return wait_gpio(info, argp);
1049        case MGSL_IOCGXSYNC:
1050                return get_xsync(info, argp);
1051        case MGSL_IOCSXSYNC:
1052                return set_xsync(info, (int)arg);
1053        case MGSL_IOCGXCTRL:
1054                return get_xctrl(info, argp);
1055        case MGSL_IOCSXCTRL:
1056                return set_xctrl(info, (int)arg);
1057        }
1058        mutex_lock(&info->port.mutex);
1059        switch (cmd) {
1060        case MGSL_IOCGPARAMS:
1061                ret = get_params(info, argp);
1062                break;
1063        case MGSL_IOCSPARAMS:
1064                ret = set_params(info, argp);
1065                break;
1066        case MGSL_IOCGTXIDLE:
1067                ret = get_txidle(info, argp);
1068                break;
1069        case MGSL_IOCSTXIDLE:
1070                ret = set_txidle(info, (int)arg);
1071                break;
1072        case MGSL_IOCTXENABLE:
1073                ret = tx_enable(info, (int)arg);
1074                break;
1075        case MGSL_IOCRXENABLE:
1076                ret = rx_enable(info, (int)arg);
1077                break;
1078        case MGSL_IOCTXABORT:
1079                ret = tx_abort(info);
1080                break;
1081        case MGSL_IOCGSTATS:
1082                ret = get_stats(info, argp);
1083                break;
1084        case MGSL_IOCGIF:
1085                ret = get_interface(info, argp);
1086                break;
1087        case MGSL_IOCSIF:
1088                ret = set_interface(info,(int)arg);
1089                break;
1090        default:
1091                ret = -ENOIOCTLCMD;
1092        }
1093        mutex_unlock(&info->port.mutex);
1094        return ret;
1095}
1096
1097static int get_icount(struct tty_struct *tty,
1098                                struct serial_icounter_struct *icount)
1099
1100{
1101        struct slgt_info *info = tty->driver_data;
1102        struct mgsl_icount cnow;        /* kernel counter temps */
1103        unsigned long flags;
1104
1105        spin_lock_irqsave(&info->lock,flags);
1106        cnow = info->icount;
1107        spin_unlock_irqrestore(&info->lock,flags);
1108
1109        icount->cts = cnow.cts;
1110        icount->dsr = cnow.dsr;
1111        icount->rng = cnow.rng;
1112        icount->dcd = cnow.dcd;
1113        icount->rx = cnow.rx;
1114        icount->tx = cnow.tx;
1115        icount->frame = cnow.frame;
1116        icount->overrun = cnow.overrun;
1117        icount->parity = cnow.parity;
1118        icount->brk = cnow.brk;
1119        icount->buf_overrun = cnow.buf_overrun;
1120
1121        return 0;
1122}
1123
1124/*
1125 * support for 32 bit ioctl calls on 64 bit systems
1126 */
1127#ifdef CONFIG_COMPAT
1128static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1129{
1130        struct MGSL_PARAMS32 tmp_params;
1131
1132        DBGINFO(("%s get_params32\n", info->device_name));
1133        memset(&tmp_params, 0, sizeof(tmp_params));
1134        tmp_params.mode            = (compat_ulong_t)info->params.mode;
1135        tmp_params.loopback        = info->params.loopback;
1136        tmp_params.flags           = info->params.flags;
1137        tmp_params.encoding        = info->params.encoding;
1138        tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1139        tmp_params.addr_filter     = info->params.addr_filter;
1140        tmp_params.crc_type        = info->params.crc_type;
1141        tmp_params.preamble_length = info->params.preamble_length;
1142        tmp_params.preamble        = info->params.preamble;
1143        tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1144        tmp_params.data_bits       = info->params.data_bits;
1145        tmp_params.stop_bits       = info->params.stop_bits;
1146        tmp_params.parity          = info->params.parity;
1147        if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1148                return -EFAULT;
1149        return 0;
1150}
1151
1152static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1153{
1154        struct MGSL_PARAMS32 tmp_params;
1155
1156        DBGINFO(("%s set_params32\n", info->device_name));
1157        if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1158                return -EFAULT;
1159
1160        spin_lock(&info->lock);
1161        if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1162                info->base_clock = tmp_params.clock_speed;
1163        } else {
1164                info->params.mode            = tmp_params.mode;
1165                info->params.loopback        = tmp_params.loopback;
1166                info->params.flags           = tmp_params.flags;
1167                info->params.encoding        = tmp_params.encoding;
1168                info->params.clock_speed     = tmp_params.clock_speed;
1169                info->params.addr_filter     = tmp_params.addr_filter;
1170                info->params.crc_type        = tmp_params.crc_type;
1171                info->params.preamble_length = tmp_params.preamble_length;
1172                info->params.preamble        = tmp_params.preamble;
1173                info->params.data_rate       = tmp_params.data_rate;
1174                info->params.data_bits       = tmp_params.data_bits;
1175                info->params.stop_bits       = tmp_params.stop_bits;
1176                info->params.parity          = tmp_params.parity;
1177        }
1178        spin_unlock(&info->lock);
1179
1180        program_hw(info);
1181
1182        return 0;
1183}
1184
1185static long slgt_compat_ioctl(struct tty_struct *tty,
1186                         unsigned int cmd, unsigned long arg)
1187{
1188        struct slgt_info *info = tty->driver_data;
1189        int rc = -ENOIOCTLCMD;
1190
1191        if (sanity_check(info, tty->name, "compat_ioctl"))
1192                return -ENODEV;
1193        DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1194
1195        switch (cmd) {
1196
1197        case MGSL_IOCSPARAMS32:
1198                rc = set_params32(info, compat_ptr(arg));
1199                break;
1200
1201        case MGSL_IOCGPARAMS32:
1202                rc = get_params32(info, compat_ptr(arg));
1203                break;
1204
1205        case MGSL_IOCGPARAMS:
1206        case MGSL_IOCSPARAMS:
1207        case MGSL_IOCGTXIDLE:
1208        case MGSL_IOCGSTATS:
1209        case MGSL_IOCWAITEVENT:
1210        case MGSL_IOCGIF:
1211        case MGSL_IOCSGPIO:
1212        case MGSL_IOCGGPIO:
1213        case MGSL_IOCWAITGPIO:
1214        case MGSL_IOCGXSYNC:
1215        case MGSL_IOCGXCTRL:
1216        case MGSL_IOCSTXIDLE:
1217        case MGSL_IOCTXENABLE:
1218        case MGSL_IOCRXENABLE:
1219        case MGSL_IOCTXABORT:
1220        case TIOCMIWAIT:
1221        case MGSL_IOCSIF:
1222        case MGSL_IOCSXSYNC:
1223        case MGSL_IOCSXCTRL:
1224                rc = ioctl(tty, cmd, arg);
1225                break;
1226        }
1227
1228        DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1229        return rc;
1230}
1231#else
1232#define slgt_compat_ioctl NULL
1233#endif /* ifdef CONFIG_COMPAT */
1234
1235/*
1236 * proc fs support
1237 */
1238static inline void line_info(struct seq_file *m, struct slgt_info *info)
1239{
1240        char stat_buf[30];
1241        unsigned long flags;
1242
1243        seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1244                      info->device_name, info->phys_reg_addr,
1245                      info->irq_level, info->max_frame_size);
1246
1247        /* output current serial signal states */
1248        spin_lock_irqsave(&info->lock,flags);
1249        get_signals(info);
1250        spin_unlock_irqrestore(&info->lock,flags);
1251
1252        stat_buf[0] = 0;
1253        stat_buf[1] = 0;
1254        if (info->signals & SerialSignal_RTS)
1255                strcat(stat_buf, "|RTS");
1256        if (info->signals & SerialSignal_CTS)
1257                strcat(stat_buf, "|CTS");
1258        if (info->signals & SerialSignal_DTR)
1259                strcat(stat_buf, "|DTR");
1260        if (info->signals & SerialSignal_DSR)
1261                strcat(stat_buf, "|DSR");
1262        if (info->signals & SerialSignal_DCD)
1263                strcat(stat_buf, "|CD");
1264        if (info->signals & SerialSignal_RI)
1265                strcat(stat_buf, "|RI");
1266
1267        if (info->params.mode != MGSL_MODE_ASYNC) {
1268                seq_printf(m, "\tHDLC txok:%d rxok:%d",
1269                               info->icount.txok, info->icount.rxok);
1270                if (info->icount.txunder)
1271                        seq_printf(m, " txunder:%d", info->icount.txunder);
1272                if (info->icount.txabort)
1273                        seq_printf(m, " txabort:%d", info->icount.txabort);
1274                if (info->icount.rxshort)
1275                        seq_printf(m, " rxshort:%d", info->icount.rxshort);
1276                if (info->icount.rxlong)
1277                        seq_printf(m, " rxlong:%d", info->icount.rxlong);
1278                if (info->icount.rxover)
1279                        seq_printf(m, " rxover:%d", info->icount.rxover);
1280                if (info->icount.rxcrc)
1281                        seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1282        } else {
1283                seq_printf(m, "\tASYNC tx:%d rx:%d",
1284                               info->icount.tx, info->icount.rx);
1285                if (info->icount.frame)
1286                        seq_printf(m, " fe:%d", info->icount.frame);
1287                if (info->icount.parity)
1288                        seq_printf(m, " pe:%d", info->icount.parity);
1289                if (info->icount.brk)
1290                        seq_printf(m, " brk:%d", info->icount.brk);
1291                if (info->icount.overrun)
1292                        seq_printf(m, " oe:%d", info->icount.overrun);
1293        }
1294
1295        /* Append serial signal status to end */
1296        seq_printf(m, " %s\n", stat_buf+1);
1297
1298        seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1299                       info->tx_active,info->bh_requested,info->bh_running,
1300                       info->pending_bh);
1301}
1302
1303/* Called to print information about devices
1304 */
1305static int synclink_gt_proc_show(struct seq_file *m, void *v)
1306{
1307        struct slgt_info *info;
1308
1309        seq_puts(m, "synclink_gt driver\n");
1310
1311        info = slgt_device_list;
1312        while( info ) {
1313                line_info(m, info);
1314                info = info->next_device;
1315        }
1316        return 0;
1317}
1318
1319/*
1320 * return count of bytes in transmit buffer
1321 */
1322static int chars_in_buffer(struct tty_struct *tty)
1323{
1324        struct slgt_info *info = tty->driver_data;
1325        int count;
1326        if (sanity_check(info, tty->name, "chars_in_buffer"))
1327                return 0;
1328        count = tbuf_bytes(info);
1329        DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1330        return count;
1331}
1332
1333/*
1334 * signal remote device to throttle send data (our receive data)
1335 */
1336static void throttle(struct tty_struct * tty)
1337{
1338        struct slgt_info *info = tty->driver_data;
1339        unsigned long flags;
1340
1341        if (sanity_check(info, tty->name, "throttle"))
1342                return;
1343        DBGINFO(("%s throttle\n", info->device_name));
1344        if (I_IXOFF(tty))
1345                send_xchar(tty, STOP_CHAR(tty));
1346        if (C_CRTSCTS(tty)) {
1347                spin_lock_irqsave(&info->lock,flags);
1348                info->signals &= ~SerialSignal_RTS;
1349                set_signals(info);
1350                spin_unlock_irqrestore(&info->lock,flags);
1351        }
1352}
1353
1354/*
1355 * signal remote device to stop throttling send data (our receive data)
1356 */
1357static void unthrottle(struct tty_struct * tty)
1358{
1359        struct slgt_info *info = tty->driver_data;
1360        unsigned long flags;
1361
1362        if (sanity_check(info, tty->name, "unthrottle"))
1363                return;
1364        DBGINFO(("%s unthrottle\n", info->device_name));
1365        if (I_IXOFF(tty)) {
1366                if (info->x_char)
1367                        info->x_char = 0;
1368                else
1369                        send_xchar(tty, START_CHAR(tty));
1370        }
1371        if (C_CRTSCTS(tty)) {
1372                spin_lock_irqsave(&info->lock,flags);
1373                info->signals |= SerialSignal_RTS;
1374                set_signals(info);
1375                spin_unlock_irqrestore(&info->lock,flags);
1376        }
1377}
1378
1379/*
1380 * set or clear transmit break condition
1381 * break_state  -1=set break condition, 0=clear
1382 */
1383static int set_break(struct tty_struct *tty, int break_state)
1384{
1385        struct slgt_info *info = tty->driver_data;
1386        unsigned short value;
1387        unsigned long flags;
1388
1389        if (sanity_check(info, tty->name, "set_break"))
1390                return -EINVAL;
1391        DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1392
1393        spin_lock_irqsave(&info->lock,flags);
1394        value = rd_reg16(info, TCR);
1395        if (break_state == -1)
1396                value |= BIT6;
1397        else
1398                value &= ~BIT6;
1399        wr_reg16(info, TCR, value);
1400        spin_unlock_irqrestore(&info->lock,flags);
1401        return 0;
1402}
1403
1404#if SYNCLINK_GENERIC_HDLC
1405
1406/**
1407 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1408 * set encoding and frame check sequence (FCS) options
1409 *
1410 * dev       pointer to network device structure
1411 * encoding  serial encoding setting
1412 * parity    FCS setting
1413 *
1414 * returns 0 if success, otherwise error code
1415 */
1416static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1417                          unsigned short parity)
1418{
1419        struct slgt_info *info = dev_to_port(dev);
1420        unsigned char  new_encoding;
1421        unsigned short new_crctype;
1422
1423        /* return error if TTY interface open */
1424        if (info->port.count)
1425                return -EBUSY;
1426
1427        DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1428
1429        switch (encoding)
1430        {
1431        case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1432        case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1433        case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1434        case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1435        case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1436        default: return -EINVAL;
1437        }
1438
1439        switch (parity)
1440        {
1441        case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1442        case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1443        case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1444        default: return -EINVAL;
1445        }
1446
1447        info->params.encoding = new_encoding;
1448        info->params.crc_type = new_crctype;
1449
1450        /* if network interface up, reprogram hardware */
1451        if (info->netcount)
1452                program_hw(info);
1453
1454        return 0;
1455}
1456
1457/**
1458 * called by generic HDLC layer to send frame
1459 *
1460 * skb  socket buffer containing HDLC frame
1461 * dev  pointer to network device structure
1462 */
1463static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1464                                      struct net_device *dev)
1465{
1466        struct slgt_info *info = dev_to_port(dev);
1467        unsigned long flags;
1468
1469        DBGINFO(("%s hdlc_xmit\n", dev->name));
1470
1471        if (!skb->len)
1472                return NETDEV_TX_OK;
1473
1474        /* stop sending until this frame completes */
1475        netif_stop_queue(dev);
1476
1477        /* update network statistics */
1478        dev->stats.tx_packets++;
1479        dev->stats.tx_bytes += skb->len;
1480
1481        /* save start time for transmit timeout detection */
1482        netif_trans_update(dev);
1483
1484        spin_lock_irqsave(&info->lock, flags);
1485        tx_load(info, skb->data, skb->len);
1486        spin_unlock_irqrestore(&info->lock, flags);
1487
1488        /* done with socket buffer, so free it */
1489        dev_kfree_skb(skb);
1490
1491        return NETDEV_TX_OK;
1492}
1493
1494/**
1495 * called by network layer when interface enabled
1496 * claim resources and initialize hardware
1497 *
1498 * dev  pointer to network device structure
1499 *
1500 * returns 0 if success, otherwise error code
1501 */
1502static int hdlcdev_open(struct net_device *dev)
1503{
1504        struct slgt_info *info = dev_to_port(dev);
1505        int rc;
1506        unsigned long flags;
1507
1508        if (!try_module_get(THIS_MODULE))
1509                return -EBUSY;
1510
1511        DBGINFO(("%s hdlcdev_open\n", dev->name));
1512
1513        /* generic HDLC layer open processing */
1514        rc = hdlc_open(dev);
1515        if (rc)
1516                return rc;
1517
1518        /* arbitrate between network and tty opens */
1519        spin_lock_irqsave(&info->netlock, flags);
1520        if (info->port.count != 0 || info->netcount != 0) {
1521                DBGINFO(("%s hdlc_open busy\n", dev->name));
1522                spin_unlock_irqrestore(&info->netlock, flags);
1523                return -EBUSY;
1524        }
1525        info->netcount=1;
1526        spin_unlock_irqrestore(&info->netlock, flags);
1527
1528        /* claim resources and init adapter */
1529        if ((rc = startup(info)) != 0) {
1530                spin_lock_irqsave(&info->netlock, flags);
1531                info->netcount=0;
1532                spin_unlock_irqrestore(&info->netlock, flags);
1533                return rc;
1534        }
1535
1536        /* assert RTS and DTR, apply hardware settings */
1537        info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1538        program_hw(info);
1539
1540        /* enable network layer transmit */
1541        netif_trans_update(dev);
1542        netif_start_queue(dev);
1543
1544        /* inform generic HDLC layer of current DCD status */
1545        spin_lock_irqsave(&info->lock, flags);
1546        get_signals(info);
1547        spin_unlock_irqrestore(&info->lock, flags);
1548        if (info->signals & SerialSignal_DCD)
1549                netif_carrier_on(dev);
1550        else
1551                netif_carrier_off(dev);
1552        return 0;
1553}
1554
1555/**
1556 * called by network layer when interface is disabled
1557 * shutdown hardware and release resources
1558 *
1559 * dev  pointer to network device structure
1560 *
1561 * returns 0 if success, otherwise error code
1562 */
1563static int hdlcdev_close(struct net_device *dev)
1564{
1565        struct slgt_info *info = dev_to_port(dev);
1566        unsigned long flags;
1567
1568        DBGINFO(("%s hdlcdev_close\n", dev->name));
1569
1570        netif_stop_queue(dev);
1571
1572        /* shutdown adapter and release resources */
1573        shutdown(info);
1574
1575        hdlc_close(dev);
1576
1577        spin_lock_irqsave(&info->netlock, flags);
1578        info->netcount=0;
1579        spin_unlock_irqrestore(&info->netlock, flags);
1580
1581        module_put(THIS_MODULE);
1582        return 0;
1583}
1584
1585/**
1586 * called by network layer to process IOCTL call to network device
1587 *
1588 * dev  pointer to network device structure
1589 * ifr  pointer to network interface request structure
1590 * cmd  IOCTL command code
1591 *
1592 * returns 0 if success, otherwise error code
1593 */
1594static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1595{
1596        const size_t size = sizeof(sync_serial_settings);
1597        sync_serial_settings new_line;
1598        sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1599        struct slgt_info *info = dev_to_port(dev);
1600        unsigned int flags;
1601
1602        DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1603
1604        /* return error if TTY interface open */
1605        if (info->port.count)
1606                return -EBUSY;
1607
1608        if (cmd != SIOCWANDEV)
1609                return hdlc_ioctl(dev, ifr, cmd);
1610
1611        memset(&new_line, 0, sizeof(new_line));
1612
1613        switch(ifr->ifr_settings.type) {
1614        case IF_GET_IFACE: /* return current sync_serial_settings */
1615
1616                ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1617                if (ifr->ifr_settings.size < size) {
1618                        ifr->ifr_settings.size = size; /* data size wanted */
1619                        return -ENOBUFS;
1620                }
1621
1622                flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1623                                              HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1624                                              HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1625                                              HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1626
1627                switch (flags){
1628                case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1629                case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1630                case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1631                case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1632                default: new_line.clock_type = CLOCK_DEFAULT;
1633                }
1634
1635                new_line.clock_rate = info->params.clock_speed;
1636                new_line.loopback   = info->params.loopback ? 1:0;
1637
1638                if (copy_to_user(line, &new_line, size))
1639                        return -EFAULT;
1640                return 0;
1641
1642        case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1643
1644                if(!capable(CAP_NET_ADMIN))
1645                        return -EPERM;
1646                if (copy_from_user(&new_line, line, size))
1647                        return -EFAULT;
1648
1649                switch (new_line.clock_type)
1650                {
1651                case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1652                case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1653                case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1654                case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1655                case CLOCK_DEFAULT:  flags = info->params.flags &
1656                                             (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1657                                              HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1658                                              HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1659                                              HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1660                default: return -EINVAL;
1661                }
1662
1663                if (new_line.loopback != 0 && new_line.loopback != 1)
1664                        return -EINVAL;
1665
1666                info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1667                                        HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1668                                        HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1669                                        HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1670                info->params.flags |= flags;
1671
1672                info->params.loopback = new_line.loopback;
1673
1674                if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1675                        info->params.clock_speed = new_line.clock_rate;
1676                else
1677                        info->params.clock_speed = 0;
1678
1679                /* if network interface up, reprogram hardware */
1680                if (info->netcount)
1681                        program_hw(info);
1682                return 0;
1683
1684        default:
1685                return hdlc_ioctl(dev, ifr, cmd);
1686        }
1687}
1688
1689/**
1690 * called by network layer when transmit timeout is detected
1691 *
1692 * dev  pointer to network device structure
1693 */
1694static void hdlcdev_tx_timeout(struct net_device *dev)
1695{
1696        struct slgt_info *info = dev_to_port(dev);
1697        unsigned long flags;
1698
1699        DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1700
1701        dev->stats.tx_errors++;
1702        dev->stats.tx_aborted_errors++;
1703
1704        spin_lock_irqsave(&info->lock,flags);
1705        tx_stop(info);
1706        spin_unlock_irqrestore(&info->lock,flags);
1707
1708        netif_wake_queue(dev);
1709}
1710
1711/**
1712 * called by device driver when transmit completes
1713 * reenable network layer transmit if stopped
1714 *
1715 * info  pointer to device instance information
1716 */
1717static void hdlcdev_tx_done(struct slgt_info *info)
1718{
1719        if (netif_queue_stopped(info->netdev))
1720                netif_wake_queue(info->netdev);
1721}
1722
1723/**
1724 * called by device driver when frame received
1725 * pass frame to network layer
1726 *
1727 * info  pointer to device instance information
1728 * buf   pointer to buffer contianing frame data
1729 * size  count of data bytes in buf
1730 */
1731static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1732{
1733        struct sk_buff *skb = dev_alloc_skb(size);
1734        struct net_device *dev = info->netdev;
1735
1736        DBGINFO(("%s hdlcdev_rx\n", dev->name));
1737
1738        if (skb == NULL) {
1739                DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1740                dev->stats.rx_dropped++;
1741                return;
1742        }
1743
1744        skb_put_data(skb, buf, size);
1745
1746        skb->protocol = hdlc_type_trans(skb, dev);
1747
1748        dev->stats.rx_packets++;
1749        dev->stats.rx_bytes += size;
1750
1751        netif_rx(skb);
1752}
1753
1754static const struct net_device_ops hdlcdev_ops = {
1755        .ndo_open       = hdlcdev_open,
1756        .ndo_stop       = hdlcdev_close,
1757        .ndo_start_xmit = hdlc_start_xmit,
1758        .ndo_do_ioctl   = hdlcdev_ioctl,
1759        .ndo_tx_timeout = hdlcdev_tx_timeout,
1760};
1761
1762/**
1763 * called by device driver when adding device instance
1764 * do generic HDLC initialization
1765 *
1766 * info  pointer to device instance information
1767 *
1768 * returns 0 if success, otherwise error code
1769 */
1770static int hdlcdev_init(struct slgt_info *info)
1771{
1772        int rc;
1773        struct net_device *dev;
1774        hdlc_device *hdlc;
1775
1776        /* allocate and initialize network and HDLC layer objects */
1777
1778        dev = alloc_hdlcdev(info);
1779        if (!dev) {
1780                printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1781                return -ENOMEM;
1782        }
1783
1784        /* for network layer reporting purposes only */
1785        dev->mem_start = info->phys_reg_addr;
1786        dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1787        dev->irq       = info->irq_level;
1788
1789        /* network layer callbacks and settings */
1790        dev->netdev_ops     = &hdlcdev_ops;
1791        dev->watchdog_timeo = 10 * HZ;
1792        dev->tx_queue_len   = 50;
1793
1794        /* generic HDLC layer callbacks and settings */
1795        hdlc         = dev_to_hdlc(dev);
1796        hdlc->attach = hdlcdev_attach;
1797        hdlc->xmit   = hdlcdev_xmit;
1798
1799        /* register objects with HDLC layer */
1800        rc = register_hdlc_device(dev);
1801        if (rc) {
1802                printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1803                free_netdev(dev);
1804                return rc;
1805        }
1806
1807        info->netdev = dev;
1808        return 0;
1809}
1810
1811/**
1812 * called by device driver when removing device instance
1813 * do generic HDLC cleanup
1814 *
1815 * info  pointer to device instance information
1816 */
1817static void hdlcdev_exit(struct slgt_info *info)
1818{
1819        unregister_hdlc_device(info->netdev);
1820        free_netdev(info->netdev);
1821        info->netdev = NULL;
1822}
1823
1824#endif /* ifdef CONFIG_HDLC */
1825
1826/*
1827 * get async data from rx DMA buffers
1828 */
1829static void rx_async(struct slgt_info *info)
1830{
1831        struct mgsl_icount *icount = &info->icount;
1832        unsigned int start, end;
1833        unsigned char *p;
1834        unsigned char status;
1835        struct slgt_desc *bufs = info->rbufs;
1836        int i, count;
1837        int chars = 0;
1838        int stat;
1839        unsigned char ch;
1840
1841        start = end = info->rbuf_current;
1842
1843        while(desc_complete(bufs[end])) {
1844                count = desc_count(bufs[end]) - info->rbuf_index;
1845                p     = bufs[end].buf + info->rbuf_index;
1846
1847                DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1848                DBGDATA(info, p, count, "rx");
1849
1850                for(i=0 ; i < count; i+=2, p+=2) {
1851                        ch = *p;
1852                        icount->rx++;
1853
1854                        stat = 0;
1855
1856                        status = *(p + 1) & (BIT1 + BIT0);
1857                        if (status) {
1858                                if (status & BIT1)
1859                                        icount->parity++;
1860                                else if (status & BIT0)
1861                                        icount->frame++;
1862                                /* discard char if tty control flags say so */
1863                                if (status & info->ignore_status_mask)
1864                                        continue;
1865                                if (status & BIT1)
1866                                        stat = TTY_PARITY;
1867                                else if (status & BIT0)
1868                                        stat = TTY_FRAME;
1869                        }
1870                        tty_insert_flip_char(&info->port, ch, stat);
1871                        chars++;
1872                }
1873
1874                if (i < count) {
1875                        /* receive buffer not completed */
1876                        info->rbuf_index += i;
1877                        mod_timer(&info->rx_timer, jiffies + 1);
1878                        break;
1879                }
1880
1881                info->rbuf_index = 0;
1882                free_rbufs(info, end, end);
1883
1884                if (++end == info->rbuf_count)
1885                        end = 0;
1886
1887                /* if entire list searched then no frame available */
1888                if (end == start)
1889                        break;
1890        }
1891
1892        if (chars)
1893                tty_flip_buffer_push(&info->port);
1894}
1895
1896/*
1897 * return next bottom half action to perform
1898 */
1899static int bh_action(struct slgt_info *info)
1900{
1901        unsigned long flags;
1902        int rc;
1903
1904        spin_lock_irqsave(&info->lock,flags);
1905
1906        if (info->pending_bh & BH_RECEIVE) {
1907                info->pending_bh &= ~BH_RECEIVE;
1908                rc = BH_RECEIVE;
1909        } else if (info->pending_bh & BH_TRANSMIT) {
1910                info->pending_bh &= ~BH_TRANSMIT;
1911                rc = BH_TRANSMIT;
1912        } else if (info->pending_bh & BH_STATUS) {
1913                info->pending_bh &= ~BH_STATUS;
1914                rc = BH_STATUS;
1915        } else {
1916                /* Mark BH routine as complete */
1917                info->bh_running = false;
1918                info->bh_requested = false;
1919                rc = 0;
1920        }
1921
1922        spin_unlock_irqrestore(&info->lock,flags);
1923
1924        return rc;
1925}
1926
1927/*
1928 * perform bottom half processing
1929 */
1930static void bh_handler(struct work_struct *work)
1931{
1932        struct slgt_info *info = container_of(work, struct slgt_info, task);
1933        int action;
1934
1935        info->bh_running = true;
1936
1937        while((action = bh_action(info))) {
1938                switch (action) {
1939                case BH_RECEIVE:
1940                        DBGBH(("%s bh receive\n", info->device_name));
1941                        switch(info->params.mode) {
1942                        case MGSL_MODE_ASYNC:
1943                                rx_async(info);
1944                                break;
1945                        case MGSL_MODE_HDLC:
1946                                while(rx_get_frame(info));
1947                                break;
1948                        case MGSL_MODE_RAW:
1949                        case MGSL_MODE_MONOSYNC:
1950                        case MGSL_MODE_BISYNC:
1951                        case MGSL_MODE_XSYNC:
1952                                while(rx_get_buf(info));
1953                                break;
1954                        }
1955                        /* restart receiver if rx DMA buffers exhausted */
1956                        if (info->rx_restart)
1957                                rx_start(info);
1958                        break;
1959                case BH_TRANSMIT:
1960                        bh_transmit(info);
1961                        break;
1962                case BH_STATUS:
1963                        DBGBH(("%s bh status\n", info->device_name));
1964                        info->ri_chkcount = 0;
1965                        info->dsr_chkcount = 0;
1966                        info->dcd_chkcount = 0;
1967                        info->cts_chkcount = 0;
1968                        break;
1969                default:
1970                        DBGBH(("%s unknown action\n", info->device_name));
1971                        break;
1972                }
1973        }
1974        DBGBH(("%s bh_handler exit\n", info->device_name));
1975}
1976
1977static void bh_transmit(struct slgt_info *info)
1978{
1979        struct tty_struct *tty = info->port.tty;
1980
1981        DBGBH(("%s bh_transmit\n", info->device_name));
1982        if (tty)
1983                tty_wakeup(tty);
1984}
1985
1986static void dsr_change(struct slgt_info *info, unsigned short status)
1987{
1988        if (status & BIT3) {
1989                info->signals |= SerialSignal_DSR;
1990                info->input_signal_events.dsr_up++;
1991        } else {
1992                info->signals &= ~SerialSignal_DSR;
1993                info->input_signal_events.dsr_down++;
1994        }
1995        DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1996        if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1997                slgt_irq_off(info, IRQ_DSR);
1998                return;
1999        }
2000        info->icount.dsr++;
2001        wake_up_interruptible(&info->status_event_wait_q);
2002        wake_up_interruptible(&info->event_wait_q);
2003        info->pending_bh |= BH_STATUS;
2004}
2005
2006static void cts_change(struct slgt_info *info, unsigned short status)
2007{
2008        if (status & BIT2) {
2009                info->signals |= SerialSignal_CTS;
2010                info->input_signal_events.cts_up++;
2011        } else {
2012                info->signals &= ~SerialSignal_CTS;
2013                info->input_signal_events.cts_down++;
2014        }
2015        DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2016        if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2017                slgt_irq_off(info, IRQ_CTS);
2018                return;
2019        }
2020        info->icount.cts++;
2021        wake_up_interruptible(&info->status_event_wait_q);
2022        wake_up_interruptible(&info->event_wait_q);
2023        info->pending_bh |= BH_STATUS;
2024
2025        if (tty_port_cts_enabled(&info->port)) {
2026                if (info->port.tty) {
2027                        if (info->port.tty->hw_stopped) {
2028                                if (info->signals & SerialSignal_CTS) {
2029                                        info->port.tty->hw_stopped = 0;
2030                                        info->pending_bh |= BH_TRANSMIT;
2031                                        return;
2032                                }
2033                        } else {
2034                                if (!(info->signals & SerialSignal_CTS))
2035                                        info->port.tty->hw_stopped = 1;
2036                        }
2037                }
2038        }
2039}
2040
2041static void dcd_change(struct slgt_info *info, unsigned short status)
2042{
2043        if (status & BIT1) {
2044                info->signals |= SerialSignal_DCD;
2045                info->input_signal_events.dcd_up++;
2046        } else {
2047                info->signals &= ~SerialSignal_DCD;
2048                info->input_signal_events.dcd_down++;
2049        }
2050        DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2051        if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2052                slgt_irq_off(info, IRQ_DCD);
2053                return;
2054        }
2055        info->icount.dcd++;
2056#if SYNCLINK_GENERIC_HDLC
2057        if (info->netcount) {
2058                if (info->signals & SerialSignal_DCD)
2059                        netif_carrier_on(info->netdev);
2060                else
2061                        netif_carrier_off(info->netdev);
2062        }
2063#endif
2064        wake_up_interruptible(&info->status_event_wait_q);
2065        wake_up_interruptible(&info->event_wait_q);
2066        info->pending_bh |= BH_STATUS;
2067
2068        if (tty_port_check_carrier(&info->port)) {
2069                if (info->signals & SerialSignal_DCD)
2070                        wake_up_interruptible(&info->port.open_wait);
2071                else {
2072                        if (info->port.tty)
2073                                tty_hangup(info->port.tty);
2074                }
2075        }
2076}
2077
2078static void ri_change(struct slgt_info *info, unsigned short status)
2079{
2080        if (status & BIT0) {
2081                info->signals |= SerialSignal_RI;
2082                info->input_signal_events.ri_up++;
2083        } else {
2084                info->signals &= ~SerialSignal_RI;
2085                info->input_signal_events.ri_down++;
2086        }
2087        DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2088        if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2089                slgt_irq_off(info, IRQ_RI);
2090                return;
2091        }
2092        info->icount.rng++;
2093        wake_up_interruptible(&info->status_event_wait_q);
2094        wake_up_interruptible(&info->event_wait_q);
2095        info->pending_bh |= BH_STATUS;
2096}
2097
2098static void isr_rxdata(struct slgt_info *info)
2099{
2100        unsigned int count = info->rbuf_fill_count;
2101        unsigned int i = info->rbuf_fill_index;
2102        unsigned short reg;
2103
2104        while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2105                reg = rd_reg16(info, RDR);
2106                DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2107                if (desc_complete(info->rbufs[i])) {
2108                        /* all buffers full */
2109                        rx_stop(info);
2110                        info->rx_restart = 1;
2111                        continue;
2112                }
2113                info->rbufs[i].buf[count++] = (unsigned char)reg;
2114                /* async mode saves status byte to buffer for each data byte */
2115                if (info->params.mode == MGSL_MODE_ASYNC)
2116                        info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2117                if (count == info->rbuf_fill_level || (reg & BIT10)) {
2118                        /* buffer full or end of frame */
2119                        set_desc_count(info->rbufs[i], count);
2120                        set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2121                        info->rbuf_fill_count = count = 0;
2122                        if (++i == info->rbuf_count)
2123                                i = 0;
2124                        info->pending_bh |= BH_RECEIVE;
2125                }
2126        }
2127
2128        info->rbuf_fill_index = i;
2129        info->rbuf_fill_count = count;
2130}
2131
2132static void isr_serial(struct slgt_info *info)
2133{
2134        unsigned short status = rd_reg16(info, SSR);
2135
2136        DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2137
2138        wr_reg16(info, SSR, status); /* clear pending */
2139
2140        info->irq_occurred = true;
2141
2142        if (info->params.mode == MGSL_MODE_ASYNC) {
2143                if (status & IRQ_TXIDLE) {
2144                        if (info->tx_active)
2145                                isr_txeom(info, status);
2146                }
2147                if (info->rx_pio && (status & IRQ_RXDATA))
2148                        isr_rxdata(info);
2149                if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2150                        info->icount.brk++;
2151                        /* process break detection if tty control allows */
2152                        if (info->port.tty) {
2153                                if (!(status & info->ignore_status_mask)) {
2154                                        if (info->read_status_mask & MASK_BREAK) {
2155                                                tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2156                                                if (info->port.flags & ASYNC_SAK)
2157                                                        do_SAK(info->port.tty);
2158                                        }
2159                                }
2160                        }
2161                }
2162        } else {
2163                if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2164                        isr_txeom(info, status);
2165                if (info->rx_pio && (status & IRQ_RXDATA))
2166                        isr_rxdata(info);
2167                if (status & IRQ_RXIDLE) {
2168                        if (status & RXIDLE)
2169                                info->icount.rxidle++;
2170                        else
2171                                info->icount.exithunt++;
2172                        wake_up_interruptible(&info->event_wait_q);
2173                }
2174
2175                if (status & IRQ_RXOVER)
2176                        rx_start(info);
2177        }
2178
2179        if (status & IRQ_DSR)
2180                dsr_change(info, status);
2181        if (status & IRQ_CTS)
2182                cts_change(info, status);
2183        if (status & IRQ_DCD)
2184                dcd_change(info, status);
2185        if (status & IRQ_RI)
2186                ri_change(info, status);
2187}
2188
2189static void isr_rdma(struct slgt_info *info)
2190{
2191        unsigned int status = rd_reg32(info, RDCSR);
2192
2193        DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2194
2195        /* RDCSR (rx DMA control/status)
2196         *
2197         * 31..07  reserved
2198         * 06      save status byte to DMA buffer
2199         * 05      error
2200         * 04      eol (end of list)
2201         * 03      eob (end of buffer)
2202         * 02      IRQ enable
2203         * 01      reset
2204         * 00      enable
2205         */
2206        wr_reg32(info, RDCSR, status);  /* clear pending */
2207
2208        if (status & (BIT5 + BIT4)) {
2209                DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2210                info->rx_restart = true;
2211        }
2212        info->pending_bh |= BH_RECEIVE;
2213}
2214
2215static void isr_tdma(struct slgt_info *info)
2216{
2217        unsigned int status = rd_reg32(info, TDCSR);
2218
2219        DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2220
2221        /* TDCSR (tx DMA control/status)
2222         *
2223         * 31..06  reserved
2224         * 05      error
2225         * 04      eol (end of list)
2226         * 03      eob (end of buffer)
2227         * 02      IRQ enable
2228         * 01      reset
2229         * 00      enable
2230         */
2231        wr_reg32(info, TDCSR, status);  /* clear pending */
2232
2233        if (status & (BIT5 + BIT4 + BIT3)) {
2234                // another transmit buffer has completed
2235                // run bottom half to get more send data from user
2236                info->pending_bh |= BH_TRANSMIT;
2237        }
2238}
2239
2240/*
2241 * return true if there are unsent tx DMA buffers, otherwise false
2242 *
2243 * if there are unsent buffers then info->tbuf_start
2244 * is set to index of first unsent buffer
2245 */
2246static bool unsent_tbufs(struct slgt_info *info)
2247{
2248        unsigned int i = info->tbuf_current;
2249        bool rc = false;
2250
2251        /*
2252         * search backwards from last loaded buffer (precedes tbuf_current)
2253         * for first unsent buffer (desc_count > 0)
2254         */
2255
2256        do {
2257                if (i)
2258                        i--;
2259                else
2260                        i = info->tbuf_count - 1;
2261                if (!desc_count(info->tbufs[i]))
2262                        break;
2263                info->tbuf_start = i;
2264                rc = true;
2265        } while (i != info->tbuf_current);
2266
2267        return rc;
2268}
2269
2270static void isr_txeom(struct slgt_info *info, unsigned short status)
2271{
2272        DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2273
2274        slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2275        tdma_reset(info);
2276        if (status & IRQ_TXUNDER) {
2277                unsigned short val = rd_reg16(info, TCR);
2278                wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2279                wr_reg16(info, TCR, val); /* clear reset bit */
2280        }
2281
2282        if (info->tx_active) {
2283                if (info->params.mode != MGSL_MODE_ASYNC) {
2284                        if (status & IRQ_TXUNDER)
2285                                info->icount.txunder++;
2286                        else if (status & IRQ_TXIDLE)
2287                                info->icount.txok++;
2288                }
2289
2290                if (unsent_tbufs(info)) {
2291                        tx_start(info);
2292                        update_tx_timer(info);
2293                        return;
2294                }
2295                info->tx_active = false;
2296
2297                del_timer(&info->tx_timer);
2298
2299                if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2300                        info->signals &= ~SerialSignal_RTS;
2301                        info->drop_rts_on_tx_done = false;
2302                        set_signals(info);
2303                }
2304
2305#if SYNCLINK_GENERIC_HDLC
2306                if (info->netcount)
2307                        hdlcdev_tx_done(info);
2308                else
2309#endif
2310                {
2311                        if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2312                                tx_stop(info);
2313                                return;
2314                        }
2315                        info->pending_bh |= BH_TRANSMIT;
2316                }
2317        }
2318}
2319
2320static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2321{
2322        struct cond_wait *w, *prev;
2323
2324        /* wake processes waiting for specific transitions */
2325        for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2326                if (w->data & changed) {
2327                        w->data = state;
2328                        wake_up_interruptible(&w->q);
2329                        if (prev != NULL)
2330                                prev->next = w->next;
2331                        else
2332                                info->gpio_wait_q = w->next;
2333                } else
2334                        prev = w;
2335        }
2336}
2337
2338/* interrupt service routine
2339 *
2340 *      irq     interrupt number
2341 *      dev_id  device ID supplied during interrupt registration
2342 */
2343static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2344{
2345        struct slgt_info *info = dev_id;
2346        unsigned int gsr;
2347        unsigned int i;
2348
2349        DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2350
2351        while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2352                DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2353                info->irq_occurred = true;
2354                for(i=0; i < info->port_count ; i++) {
2355                        if (info->port_array[i] == NULL)
2356                                continue;
2357                        spin_lock(&info->port_array[i]->lock);
2358                        if (gsr & (BIT8 << i))
2359                                isr_serial(info->port_array[i]);
2360                        if (gsr & (BIT16 << (i*2)))
2361                                isr_rdma(info->port_array[i]);
2362                        if (gsr & (BIT17 << (i*2)))
2363                                isr_tdma(info->port_array[i]);
2364                        spin_unlock(&info->port_array[i]->lock);
2365                }
2366        }
2367
2368        if (info->gpio_present) {
2369                unsigned int state;
2370                unsigned int changed;
2371                spin_lock(&info->lock);
2372                while ((changed = rd_reg32(info, IOSR)) != 0) {
2373                        DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2374                        /* read latched state of GPIO signals */
2375                        state = rd_reg32(info, IOVR);
2376                        /* clear pending GPIO interrupt bits */
2377                        wr_reg32(info, IOSR, changed);
2378                        for (i=0 ; i < info->port_count ; i++) {
2379                                if (info->port_array[i] != NULL)
2380                                        isr_gpio(info->port_array[i], changed, state);
2381                        }
2382                }
2383                spin_unlock(&info->lock);
2384        }
2385
2386        for(i=0; i < info->port_count ; i++) {
2387                struct slgt_info *port = info->port_array[i];
2388                if (port == NULL)
2389                        continue;
2390                spin_lock(&port->lock);
2391                if ((port->port.count || port->netcount) &&
2392                    port->pending_bh && !port->bh_running &&
2393                    !port->bh_requested) {
2394                        DBGISR(("%s bh queued\n", port->device_name));
2395                        schedule_work(&port->task);
2396                        port->bh_requested = true;
2397                }
2398                spin_unlock(&port->lock);
2399        }
2400
2401        DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2402        return IRQ_HANDLED;
2403}
2404
2405static int startup(struct slgt_info *info)
2406{
2407        DBGINFO(("%s startup\n", info->device_name));
2408
2409        if (tty_port_initialized(&info->port))
2410                return 0;
2411
2412        if (!info->tx_buf) {
2413                info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2414                if (!info->tx_buf) {
2415                        DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2416                        return -ENOMEM;
2417                }
2418        }
2419
2420        info->pending_bh = 0;
2421
2422        memset(&info->icount, 0, sizeof(info->icount));
2423
2424        /* program hardware for current parameters */
2425        change_params(info);
2426
2427        if (info->port.tty)
2428                clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2429
2430        tty_port_set_initialized(&info->port, 1);
2431
2432        return 0;
2433}
2434
2435/*
2436 *  called by close() and hangup() to shutdown hardware
2437 */
2438static void shutdown(struct slgt_info *info)
2439{
2440        unsigned long flags;
2441
2442        if (!tty_port_initialized(&info->port))
2443                return;
2444
2445        DBGINFO(("%s shutdown\n", info->device_name));
2446
2447        /* clear status wait queue because status changes */
2448        /* can't happen after shutting down the hardware */
2449        wake_up_interruptible(&info->status_event_wait_q);
2450        wake_up_interruptible(&info->event_wait_q);
2451
2452        del_timer_sync(&info->tx_timer);
2453        del_timer_sync(&info->rx_timer);
2454
2455        kfree(info->tx_buf);
2456        info->tx_buf = NULL;
2457
2458        spin_lock_irqsave(&info->lock,flags);
2459
2460        tx_stop(info);
2461        rx_stop(info);
2462
2463        slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2464
2465        if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2466                info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2467                set_signals(info);
2468        }
2469
2470        flush_cond_wait(&info->gpio_wait_q);
2471
2472        spin_unlock_irqrestore(&info->lock,flags);
2473
2474        if (info->port.tty)
2475                set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2476
2477        tty_port_set_initialized(&info->port, 0);
2478}
2479
2480static void program_hw(struct slgt_info *info)
2481{
2482        unsigned long flags;
2483
2484        spin_lock_irqsave(&info->lock,flags);
2485
2486        rx_stop(info);
2487        tx_stop(info);
2488
2489        if (info->params.mode != MGSL_MODE_ASYNC ||
2490            info->netcount)
2491                sync_mode(info);
2492        else
2493                async_mode(info);
2494
2495        set_signals(info);
2496
2497        info->dcd_chkcount = 0;
2498        info->cts_chkcount = 0;
2499        info->ri_chkcount = 0;
2500        info->dsr_chkcount = 0;
2501
2502        slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2503        get_signals(info);
2504
2505        if (info->netcount ||
2506            (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2507                rx_start(info);
2508
2509        spin_unlock_irqrestore(&info->lock,flags);
2510}
2511
2512/*
2513 * reconfigure adapter based on new parameters
2514 */
2515static void change_params(struct slgt_info *info)
2516{
2517        unsigned cflag;
2518        int bits_per_char;
2519
2520        if (!info->port.tty)
2521                return;
2522        DBGINFO(("%s change_params\n", info->device_name));
2523
2524        cflag = info->port.tty->termios.c_cflag;
2525
2526        /* if B0 rate (hangup) specified then negate RTS and DTR */
2527        /* otherwise assert RTS and DTR */
2528        if (cflag & CBAUD)
2529                info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2530        else
2531                info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2532
2533        /* byte size and parity */
2534
2535        switch (cflag & CSIZE) {
2536        case CS5: info->params.data_bits = 5; break;
2537        case CS6: info->params.data_bits = 6; break;
2538        case CS7: info->params.data_bits = 7; break;
2539        case CS8: info->params.data_bits = 8; break;
2540        default:  info->params.data_bits = 7; break;
2541        }
2542
2543        info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2544
2545        if (cflag & PARENB)
2546                info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2547        else
2548                info->params.parity = ASYNC_PARITY_NONE;
2549
2550        /* calculate number of jiffies to transmit a full
2551         * FIFO (32 bytes) at specified data rate
2552         */
2553        bits_per_char = info->params.data_bits +
2554                        info->params.stop_bits + 1;
2555
2556        info->params.data_rate = tty_get_baud_rate(info->port.tty);
2557
2558        if (info->params.data_rate) {
2559                info->timeout = (32*HZ*bits_per_char) /
2560                                info->params.data_rate;
2561        }
2562        info->timeout += HZ/50;         /* Add .02 seconds of slop */
2563
2564        tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2565        tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2566
2567        /* process tty input control flags */
2568
2569        info->read_status_mask = IRQ_RXOVER;
2570        if (I_INPCK(info->port.tty))
2571                info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2572        if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2573                info->read_status_mask |= MASK_BREAK;
2574        if (I_IGNPAR(info->port.tty))
2575                info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2576        if (I_IGNBRK(info->port.tty)) {
2577                info->ignore_status_mask |= MASK_BREAK;
2578                /* If ignoring parity and break indicators, ignore
2579                 * overruns too.  (For real raw support).
2580                 */
2581                if (I_IGNPAR(info->port.tty))
2582                        info->ignore_status_mask |= MASK_OVERRUN;
2583        }
2584
2585        program_hw(info);
2586}
2587
2588static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2589{
2590        DBGINFO(("%s get_stats\n",  info->device_name));
2591        if (!user_icount) {
2592                memset(&info->icount, 0, sizeof(info->icount));
2593        } else {
2594                if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2595                        return -EFAULT;
2596        }
2597        return 0;
2598}
2599
2600static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2601{
2602        DBGINFO(("%s get_params\n", info->device_name));
2603        if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2604                return -EFAULT;
2605        return 0;
2606}
2607
2608static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2609{
2610        unsigned long flags;
2611        MGSL_PARAMS tmp_params;
2612
2613        DBGINFO(("%s set_params\n", info->device_name));
2614        if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2615                return -EFAULT;
2616
2617        spin_lock_irqsave(&info->lock, flags);
2618        if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2619                info->base_clock = tmp_params.clock_speed;
2620        else
2621                memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2622        spin_unlock_irqrestore(&info->lock, flags);
2623
2624        program_hw(info);
2625
2626        return 0;
2627}
2628
2629static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2630{
2631        DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2632        if (put_user(info->idle_mode, idle_mode))
2633                return -EFAULT;
2634        return 0;
2635}
2636
2637static int set_txidle(struct slgt_info *info, int idle_mode)
2638{
2639        unsigned long flags;
2640        DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2641        spin_lock_irqsave(&info->lock,flags);
2642        info->idle_mode = idle_mode;
2643        if (info->params.mode != MGSL_MODE_ASYNC)
2644                tx_set_idle(info);
2645        spin_unlock_irqrestore(&info->lock,flags);
2646        return 0;
2647}
2648
2649static int tx_enable(struct slgt_info *info, int enable)
2650{
2651        unsigned long flags;
2652        DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2653        spin_lock_irqsave(&info->lock,flags);
2654        if (enable) {
2655                if (!info->tx_enabled)
2656                        tx_start(info);
2657        } else {
2658                if (info->tx_enabled)
2659                        tx_stop(info);
2660        }
2661        spin_unlock_irqrestore(&info->lock,flags);
2662        return 0;
2663}
2664
2665/*
2666 * abort transmit HDLC frame
2667 */
2668static int tx_abort(struct slgt_info *info)
2669{
2670        unsigned long flags;
2671        DBGINFO(("%s tx_abort\n", info->device_name));
2672        spin_lock_irqsave(&info->lock,flags);
2673        tdma_reset(info);
2674        spin_unlock_irqrestore(&info->lock,flags);
2675        return 0;
2676}
2677
2678static int rx_enable(struct slgt_info *info, int enable)
2679{
2680        unsigned long flags;
2681        unsigned int rbuf_fill_level;
2682        DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2683        spin_lock_irqsave(&info->lock,flags);
2684        /*
2685         * enable[31..16] = receive DMA buffer fill level
2686         * 0 = noop (leave fill level unchanged)
2687         * fill level must be multiple of 4 and <= buffer size
2688         */
2689        rbuf_fill_level = ((unsigned int)enable) >> 16;
2690        if (rbuf_fill_level) {
2691                if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2692                        spin_unlock_irqrestore(&info->lock, flags);
2693                        return -EINVAL;
2694                }
2695                info->rbuf_fill_level = rbuf_fill_level;
2696                if (rbuf_fill_level < 128)
2697                        info->rx_pio = 1; /* PIO mode */
2698                else
2699                        info->rx_pio = 0; /* DMA mode */
2700                rx_stop(info); /* restart receiver to use new fill level */
2701        }
2702
2703        /*
2704         * enable[1..0] = receiver enable command
2705         * 0 = disable
2706         * 1 = enable
2707         * 2 = enable or force hunt mode if already enabled
2708         */
2709        enable &= 3;
2710        if (enable) {
2711                if (!info->rx_enabled)
2712                        rx_start(info);
2713                else if (enable == 2) {
2714                        /* force hunt mode (write 1 to RCR[3]) */
2715                        wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2716                }
2717        } else {
2718                if (info->rx_enabled)
2719                        rx_stop(info);
2720        }
2721        spin_unlock_irqrestore(&info->lock,flags);
2722        return 0;
2723}
2724
2725/*
2726 *  wait for specified event to occur
2727 */
2728static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2729{
2730        unsigned long flags;
2731        int s;
2732        int rc=0;
2733        struct mgsl_icount cprev, cnow;
2734        int events;
2735        int mask;
2736        struct  _input_signal_events oldsigs, newsigs;
2737        DECLARE_WAITQUEUE(wait, current);
2738
2739        if (get_user(mask, mask_ptr))
2740                return -EFAULT;
2741
2742        DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2743
2744        spin_lock_irqsave(&info->lock,flags);
2745
2746        /* return immediately if state matches requested events */
2747        get_signals(info);
2748        s = info->signals;
2749
2750        events = mask &
2751                ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2752                  ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2753                  ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2754                  ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2755        if (events) {
2756                spin_unlock_irqrestore(&info->lock,flags);
2757                goto exit;
2758        }
2759
2760        /* save current irq counts */
2761        cprev = info->icount;
2762        oldsigs = info->input_signal_events;
2763
2764        /* enable hunt and idle irqs if needed */
2765        if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2766                unsigned short val = rd_reg16(info, SCR);
2767                if (!(val & IRQ_RXIDLE))
2768                        wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2769        }
2770
2771        set_current_state(TASK_INTERRUPTIBLE);
2772        add_wait_queue(&info->event_wait_q, &wait);
2773
2774        spin_unlock_irqrestore(&info->lock,flags);
2775
2776        for(;;) {
2777                schedule();
2778                if (signal_pending(current)) {
2779                        rc = -ERESTARTSYS;
2780                        break;
2781                }
2782
2783                /* get current irq counts */
2784                spin_lock_irqsave(&info->lock,flags);
2785                cnow = info->icount;
2786                newsigs = info->input_signal_events;
2787                set_current_state(TASK_INTERRUPTIBLE);
2788                spin_unlock_irqrestore(&info->lock,flags);
2789
2790                /* if no change, wait aborted for some reason */
2791                if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2792                    newsigs.dsr_down == oldsigs.dsr_down &&
2793                    newsigs.dcd_up   == oldsigs.dcd_up   &&
2794                    newsigs.dcd_down == oldsigs.dcd_down &&
2795                    newsigs.cts_up   == oldsigs.cts_up   &&
2796                    newsigs.cts_down == oldsigs.cts_down &&
2797                    newsigs.ri_up    == oldsigs.ri_up    &&
2798                    newsigs.ri_down  == oldsigs.ri_down  &&
2799                    cnow.exithunt    == cprev.exithunt   &&
2800                    cnow.rxidle      == cprev.rxidle) {
2801                        rc = -EIO;
2802                        break;
2803                }
2804
2805                events = mask &
2806                        ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2807                          (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2808                          (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2809                          (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2810                          (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2811                          (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2812                          (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2813                          (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2814                          (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2815                          (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2816                if (events)
2817                        break;
2818
2819                cprev = cnow;
2820                oldsigs = newsigs;
2821        }
2822
2823        remove_wait_queue(&info->event_wait_q, &wait);
2824        set_current_state(TASK_RUNNING);
2825
2826
2827        if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2828                spin_lock_irqsave(&info->lock,flags);
2829                if (!waitqueue_active(&info->event_wait_q)) {
2830                        /* disable enable exit hunt mode/idle rcvd IRQs */
2831                        wr_reg16(info, SCR,
2832                                (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2833                }
2834                spin_unlock_irqrestore(&info->lock,flags);
2835        }
2836exit:
2837        if (rc == 0)
2838                rc = put_user(events, mask_ptr);
2839        return rc;
2840}
2841
2842static int get_interface(struct slgt_info *info, int __user *if_mode)
2843{
2844        DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2845        if (put_user(info->if_mode, if_mode))
2846                return -EFAULT;
2847        return 0;
2848}
2849
2850static int set_interface(struct slgt_info *info, int if_mode)
2851{
2852        unsigned long flags;
2853        unsigned short val;
2854
2855        DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2856        spin_lock_irqsave(&info->lock,flags);
2857        info->if_mode = if_mode;
2858
2859        msc_set_vcr(info);
2860
2861        /* TCR (tx control) 07  1=RTS driver control */
2862        val = rd_reg16(info, TCR);
2863        if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2864                val |= BIT7;
2865        else
2866                val &= ~BIT7;
2867        wr_reg16(info, TCR, val);
2868
2869        spin_unlock_irqrestore(&info->lock,flags);
2870        return 0;
2871}
2872
2873static int get_xsync(struct slgt_info *info, int __user *xsync)
2874{
2875        DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2876        if (put_user(info->xsync, xsync))
2877                return -EFAULT;
2878        return 0;
2879}
2880
2881/*
2882 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2883 *
2884 * sync pattern is contained in least significant bytes of value
2885 * most significant byte of sync pattern is oldest (1st sent/detected)
2886 */
2887static int set_xsync(struct slgt_info *info, int xsync)
2888{
2889        unsigned long flags;
2890
2891        DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2892        spin_lock_irqsave(&info->lock, flags);
2893        info->xsync = xsync;
2894        wr_reg32(info, XSR, xsync);
2895        spin_unlock_irqrestore(&info->lock, flags);
2896        return 0;
2897}
2898
2899static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2900{
2901        DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2902        if (put_user(info->xctrl, xctrl))
2903                return -EFAULT;
2904        return 0;
2905}
2906
2907/*
2908 * set extended control options
2909 *
2910 * xctrl[31:19] reserved, must be zero
2911 * xctrl[18:17] extended sync pattern length in bytes
2912 *              00 = 1 byte  in xsr[7:0]
2913 *              01 = 2 bytes in xsr[15:0]
2914 *              10 = 3 bytes in xsr[23:0]
2915 *              11 = 4 bytes in xsr[31:0]
2916 * xctrl[16]    1 = enable terminal count, 0=disabled
2917 * xctrl[15:0]  receive terminal count for fixed length packets
2918 *              value is count minus one (0 = 1 byte packet)
2919 *              when terminal count is reached, receiver
2920 *              automatically returns to hunt mode and receive
2921 *              FIFO contents are flushed to DMA buffers with
2922 *              end of frame (EOF) status
2923 */
2924static int set_xctrl(struct slgt_info *info, int xctrl)
2925{
2926        unsigned long flags;
2927
2928        DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2929        spin_lock_irqsave(&info->lock, flags);
2930        info->xctrl = xctrl;
2931        wr_reg32(info, XCR, xctrl);
2932        spin_unlock_irqrestore(&info->lock, flags);
2933        return 0;
2934}
2935
2936/*
2937 * set general purpose IO pin state and direction
2938 *
2939 * user_gpio fields:
2940 * state   each bit indicates a pin state
2941 * smask   set bit indicates pin state to set
2942 * dir     each bit indicates a pin direction (0=input, 1=output)
2943 * dmask   set bit indicates pin direction to set
2944 */
2945static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2946{
2947        unsigned long flags;
2948        struct gpio_desc gpio;
2949        __u32 data;
2950
2951        if (!info->gpio_present)
2952                return -EINVAL;
2953        if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2954                return -EFAULT;
2955        DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2956                 info->device_name, gpio.state, gpio.smask,
2957                 gpio.dir, gpio.dmask));
2958
2959        spin_lock_irqsave(&info->port_array[0]->lock, flags);
2960        if (gpio.dmask) {
2961                data = rd_reg32(info, IODR);
2962                data |= gpio.dmask & gpio.dir;
2963                data &= ~(gpio.dmask & ~gpio.dir);
2964                wr_reg32(info, IODR, data);
2965        }
2966        if (gpio.smask) {
2967                data = rd_reg32(info, IOVR);
2968                data |= gpio.smask & gpio.state;
2969                data &= ~(gpio.smask & ~gpio.state);
2970                wr_reg32(info, IOVR, data);
2971        }
2972        spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2973
2974        return 0;
2975}
2976
2977/*
2978 * get general purpose IO pin state and direction
2979 */
2980static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2981{
2982        struct gpio_desc gpio;
2983        if (!info->gpio_present)
2984                return -EINVAL;
2985        gpio.state = rd_reg32(info, IOVR);
2986        gpio.smask = 0xffffffff;
2987        gpio.dir   = rd_reg32(info, IODR);
2988        gpio.dmask = 0xffffffff;
2989        if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2990                return -EFAULT;
2991        DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2992                 info->device_name, gpio.state, gpio.dir));
2993        return 0;
2994}
2995
2996/*
2997 * conditional wait facility
2998 */
2999static void init_cond_wait(struct cond_wait *w, unsigned int data)
3000{
3001        init_waitqueue_head(&w->q);
3002        init_waitqueue_entry(&w->wait, current);
3003        w->data = data;
3004}
3005
3006static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3007{
3008        set_current_state(TASK_INTERRUPTIBLE);
3009        add_wait_queue(&w->q, &w->wait);
3010        w->next = *head;
3011        *head = w;
3012}
3013
3014static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3015{
3016        struct cond_wait *w, *prev;
3017        remove_wait_queue(&cw->q, &cw->wait);
3018        set_current_state(TASK_RUNNING);
3019        for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3020                if (w == cw) {
3021                        if (prev != NULL)
3022                                prev->next = w->next;
3023                        else
3024                                *head = w->next;
3025                        break;
3026                }
3027        }
3028}
3029
3030static void flush_cond_wait(struct cond_wait **head)
3031{
3032        while (*head != NULL) {
3033                wake_up_interruptible(&(*head)->q);
3034                *head = (*head)->next;
3035        }
3036}
3037
3038/*
3039 * wait for general purpose I/O pin(s) to enter specified state
3040 *
3041 * user_gpio fields:
3042 * state - bit indicates target pin state
3043 * smask - set bit indicates watched pin
3044 *
3045 * The wait ends when at least one watched pin enters the specified
3046 * state. When 0 (no error) is returned, user_gpio->state is set to the
3047 * state of all GPIO pins when the wait ends.
3048 *
3049 * Note: Each pin may be a dedicated input, dedicated output, or
3050 * configurable input/output. The number and configuration of pins
3051 * varies with the specific adapter model. Only input pins (dedicated
3052 * or configured) can be monitored with this function.
3053 */
3054static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3055{
3056        unsigned long flags;
3057        int rc = 0;
3058        struct gpio_desc gpio;
3059        struct cond_wait wait;
3060        u32 state;
3061
3062        if (!info->gpio_present)
3063                return -EINVAL;
3064        if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3065                return -EFAULT;
3066        DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3067                 info->device_name, gpio.state, gpio.smask));
3068        /* ignore output pins identified by set IODR bit */
3069        if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3070                return -EINVAL;
3071        init_cond_wait(&wait, gpio.smask);
3072
3073        spin_lock_irqsave(&info->port_array[0]->lock, flags);
3074        /* enable interrupts for watched pins */
3075        wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3076        /* get current pin states */
3077        state = rd_reg32(info, IOVR);
3078
3079        if (gpio.smask & ~(state ^ gpio.state)) {
3080                /* already in target state */
3081                gpio.state = state;
3082        } else {
3083                /* wait for target state */
3084                add_cond_wait(&info->gpio_wait_q, &wait);
3085                spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3086                schedule();
3087                if (signal_pending(current))
3088                        rc = -ERESTARTSYS;
3089                else
3090                        gpio.state = wait.data;
3091                spin_lock_irqsave(&info->port_array[0]->lock, flags);
3092                remove_cond_wait(&info->gpio_wait_q, &wait);
3093        }
3094
3095        /* disable all GPIO interrupts if no waiting processes */
3096        if (info->gpio_wait_q == NULL)
3097                wr_reg32(info, IOER, 0);
3098        spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3099
3100        if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3101                rc = -EFAULT;
3102        return rc;
3103}
3104
3105static int modem_input_wait(struct slgt_info *info,int arg)
3106{
3107        unsigned long flags;
3108        int rc;
3109        struct mgsl_icount cprev, cnow;
3110        DECLARE_WAITQUEUE(wait, current);
3111
3112        /* save current irq counts */
3113        spin_lock_irqsave(&info->lock,flags);
3114        cprev = info->icount;
3115        add_wait_queue(&info->status_event_wait_q, &wait);
3116        set_current_state(TASK_INTERRUPTIBLE);
3117        spin_unlock_irqrestore(&info->lock,flags);
3118
3119        for(;;) {
3120                schedule();
3121                if (signal_pending(current)) {
3122                        rc = -ERESTARTSYS;
3123                        break;
3124                }
3125
3126                /* get new irq counts */
3127                spin_lock_irqsave(&info->lock,flags);
3128                cnow = info->icount;
3129                set_current_state(TASK_INTERRUPTIBLE);
3130                spin_unlock_irqrestore(&info->lock,flags);
3131
3132                /* if no change, wait aborted for some reason */
3133                if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3134                    cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3135                        rc = -EIO;
3136                        break;
3137                }
3138
3139                /* check for change in caller specified modem input */
3140                if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3141                    (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3142                    (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3143                    (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3144                        rc = 0;
3145                        break;
3146                }
3147
3148                cprev = cnow;
3149        }
3150        remove_wait_queue(&info->status_event_wait_q, &wait);
3151        set_current_state(TASK_RUNNING);
3152        return rc;
3153}
3154
3155/*
3156 *  return state of serial control and status signals
3157 */
3158static int tiocmget(struct tty_struct *tty)
3159{
3160        struct slgt_info *info = tty->driver_data;
3161        unsigned int result;
3162        unsigned long flags;
3163
3164        spin_lock_irqsave(&info->lock,flags);
3165        get_signals(info);
3166        spin_unlock_irqrestore(&info->lock,flags);
3167
3168        result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3169                ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3170                ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3171                ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3172                ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3173                ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3174
3175        DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3176        return result;
3177}
3178
3179/*
3180 * set modem control signals (DTR/RTS)
3181 *
3182 *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3183 *              TIOCMSET = set/clear signal values
3184 *      value   bit mask for command
3185 */
3186static int tiocmset(struct tty_struct *tty,
3187                    unsigned int set, unsigned int clear)
3188{
3189        struct slgt_info *info = tty->driver_data;
3190        unsigned long flags;
3191
3192        DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3193
3194        if (set & TIOCM_RTS)
3195                info->signals |= SerialSignal_RTS;
3196        if (set & TIOCM_DTR)
3197                info->signals |= SerialSignal_DTR;
3198        if (clear & TIOCM_RTS)
3199                info->signals &= ~SerialSignal_RTS;
3200        if (clear & TIOCM_DTR)
3201                info->signals &= ~SerialSignal_DTR;
3202
3203        spin_lock_irqsave(&info->lock,flags);
3204        set_signals(info);
3205        spin_unlock_irqrestore(&info->lock,flags);
3206        return 0;
3207}
3208
3209static int carrier_raised(struct tty_port *port)
3210{
3211        unsigned long flags;
3212        struct slgt_info *info = container_of(port, struct slgt_info, port);
3213
3214        spin_lock_irqsave(&info->lock,flags);
3215        get_signals(info);
3216        spin_unlock_irqrestore(&info->lock,flags);
3217        return (info->signals & SerialSignal_DCD) ? 1 : 0;
3218}
3219
3220static void dtr_rts(struct tty_port *port, int on)
3221{
3222        unsigned long flags;
3223        struct slgt_info *info = container_of(port, struct slgt_info, port);
3224
3225        spin_lock_irqsave(&info->lock,flags);
3226        if (on)
3227                info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3228        else
3229                info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3230        set_signals(info);
3231        spin_unlock_irqrestore(&info->lock,flags);
3232}
3233
3234
3235/*
3236 *  block current process until the device is ready to open
3237 */
3238static int block_til_ready(struct tty_struct *tty, struct file *filp,
3239                           struct slgt_info *info)
3240{
3241        DECLARE_WAITQUEUE(wait, current);
3242        int             retval;
3243        bool            do_clocal = false;
3244        unsigned long   flags;
3245        int             cd;
3246        struct tty_port *port = &info->port;
3247
3248        DBGINFO(("%s block_til_ready\n", tty->driver->name));
3249
3250        if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3251                /* nonblock mode is set or port is not enabled */
3252                tty_port_set_active(port, 1);
3253                return 0;
3254        }
3255
3256        if (C_CLOCAL(tty))
3257                do_clocal = true;
3258
3259        /* Wait for carrier detect and the line to become
3260         * free (i.e., not in use by the callout).  While we are in
3261         * this loop, port->count is dropped by one, so that
3262         * close() knows when to free things.  We restore it upon
3263         * exit, either normal or abnormal.
3264         */
3265
3266        retval = 0;
3267        add_wait_queue(&port->open_wait, &wait);
3268
3269        spin_lock_irqsave(&info->lock, flags);
3270        port->count--;
3271        spin_unlock_irqrestore(&info->lock, flags);
3272        port->blocked_open++;
3273
3274        while (1) {
3275                if (C_BAUD(tty) && tty_port_initialized(port))
3276                        tty_port_raise_dtr_rts(port);
3277
3278                set_current_state(TASK_INTERRUPTIBLE);
3279
3280                if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3281                        retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3282                                        -EAGAIN : -ERESTARTSYS;
3283                        break;
3284                }
3285
3286                cd = tty_port_carrier_raised(port);
3287                if (do_clocal || cd)
3288                        break;
3289
3290                if (signal_pending(current)) {
3291                        retval = -ERESTARTSYS;
3292                        break;
3293                }
3294
3295                DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3296                tty_unlock(tty);
3297                schedule();
3298                tty_lock(tty);
3299        }
3300
3301        set_current_state(TASK_RUNNING);
3302        remove_wait_queue(&port->open_wait, &wait);
3303
3304        if (!tty_hung_up_p(filp))
3305                port->count++;
3306        port->blocked_open--;
3307
3308        if (!retval)
3309                tty_port_set_active(port, 1);
3310
3311        DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3312        return retval;
3313}
3314
3315/*
3316 * allocate buffers used for calling line discipline receive_buf
3317 * directly in synchronous mode
3318 * note: add 5 bytes to max frame size to allow appending
3319 * 32-bit CRC and status byte when configured to do so
3320 */
3321static int alloc_tmp_rbuf(struct slgt_info *info)
3322{
3323        info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3324        if (info->tmp_rbuf == NULL)
3325                return -ENOMEM;
3326        /* unused flag buffer to satisfy receive_buf calling interface */
3327        info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3328        if (!info->flag_buf) {
3329                kfree(info->tmp_rbuf);
3330                info->tmp_rbuf = NULL;
3331                return -ENOMEM;
3332        }
3333        return 0;
3334}
3335
3336static void free_tmp_rbuf(struct slgt_info *info)
3337{
3338        kfree(info->tmp_rbuf);
3339        info->tmp_rbuf = NULL;
3340        kfree(info->flag_buf);
3341        info->flag_buf = NULL;
3342}
3343
3344/*
3345 * allocate DMA descriptor lists.
3346 */
3347static int alloc_desc(struct slgt_info *info)
3348{
3349        unsigned int i;
3350        unsigned int pbufs;
3351
3352        /* allocate memory to hold descriptor lists */
3353        info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3354                                           &info->bufs_dma_addr);
3355        if (info->bufs == NULL)
3356                return -ENOMEM;
3357
3358        info->rbufs = (struct slgt_desc*)info->bufs;
3359        info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3360
3361        pbufs = (unsigned int)info->bufs_dma_addr;
3362
3363        /*
3364         * Build circular lists of descriptors
3365         */
3366
3367        for (i=0; i < info->rbuf_count; i++) {
3368                /* physical address of this descriptor */
3369                info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3370
3371                /* physical address of next descriptor */
3372                if (i == info->rbuf_count - 1)
3373                        info->rbufs[i].next = cpu_to_le32(pbufs);
3374                else
3375                        info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3376                set_desc_count(info->rbufs[i], DMABUFSIZE);
3377        }
3378
3379        for (i=0; i < info->tbuf_count; i++) {
3380                /* physical address of this descriptor */
3381                info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3382
3383                /* physical address of next descriptor */
3384                if (i == info->tbuf_count - 1)
3385                        info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3386                else
3387                        info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3388        }
3389
3390        return 0;
3391}
3392
3393static void free_desc(struct slgt_info *info)
3394{
3395        if (info->bufs != NULL) {
3396                pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3397                info->bufs  = NULL;
3398                info->rbufs = NULL;
3399                info->tbufs = NULL;
3400        }
3401}
3402
3403static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3404{
3405        int i;
3406        for (i=0; i < count; i++) {
3407                if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3408                        return -ENOMEM;
3409                bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3410        }
3411        return 0;
3412}
3413
3414static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3415{
3416        int i;
3417        for (i=0; i < count; i++) {
3418                if (bufs[i].buf == NULL)
3419                        continue;
3420                pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3421                bufs[i].buf = NULL;
3422        }
3423}
3424
3425static int alloc_dma_bufs(struct slgt_info *info)
3426{
3427        info->rbuf_count = 32;
3428        info->tbuf_count = 32;
3429
3430        if (alloc_desc(info) < 0 ||
3431            alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3432            alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3433            alloc_tmp_rbuf(info) < 0) {
3434                DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3435                return -ENOMEM;
3436        }
3437        reset_rbufs(info);
3438        return 0;
3439}
3440
3441static void free_dma_bufs(struct slgt_info *info)
3442{
3443        if (info->bufs) {
3444                free_bufs(info, info->rbufs, info->rbuf_count);
3445                free_bufs(info, info->tbufs, info->tbuf_count);
3446                free_desc(info);
3447        }
3448        free_tmp_rbuf(info);
3449}
3450
3451static int claim_resources(struct slgt_info *info)
3452{
3453        if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3454                DBGERR(("%s reg addr conflict, addr=%08X\n",
3455                        info->device_name, info->phys_reg_addr));
3456                info->init_error = DiagStatus_AddressConflict;
3457                goto errout;
3458        }
3459        else
3460                info->reg_addr_requested = true;
3461
3462        info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3463        if (!info->reg_addr) {
3464                DBGERR(("%s can't map device registers, addr=%08X\n",
3465                        info->device_name, info->phys_reg_addr));
3466                info->init_error = DiagStatus_CantAssignPciResources;
3467                goto errout;
3468        }
3469        return 0;
3470
3471errout:
3472        release_resources(info);
3473        return -ENODEV;
3474}
3475
3476static void release_resources(struct slgt_info *info)
3477{
3478        if (info->irq_requested) {
3479                free_irq(info->irq_level, info);
3480                info->irq_requested = false;
3481        }
3482
3483        if (info->reg_addr_requested) {
3484                release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3485                info->reg_addr_requested = false;
3486        }
3487
3488        if (info->reg_addr) {
3489                iounmap(info->reg_addr);
3490                info->reg_addr = NULL;
3491        }
3492}
3493
3494/* Add the specified device instance data structure to the
3495 * global linked list of devices and increment the device count.
3496 */
3497static void add_device(struct slgt_info *info)
3498{
3499        char *devstr;
3500
3501        info->next_device = NULL;
3502        info->line = slgt_device_count;
3503        sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3504
3505        if (info->line < MAX_DEVICES) {
3506                if (maxframe[info->line])
3507                        info->max_frame_size = maxframe[info->line];
3508        }
3509
3510        slgt_device_count++;
3511
3512        if (!slgt_device_list)
3513                slgt_device_list = info;
3514        else {
3515                struct slgt_info *current_dev = slgt_device_list;
3516                while(current_dev->next_device)
3517                        current_dev = current_dev->next_device;
3518                current_dev->next_device = info;
3519        }
3520
3521        if (info->max_frame_size < 4096)
3522                info->max_frame_size = 4096;
3523        else if (info->max_frame_size > 65535)
3524                info->max_frame_size = 65535;
3525
3526        switch(info->pdev->device) {
3527        case SYNCLINK_GT_DEVICE_ID:
3528                devstr = "GT";
3529                break;
3530        case SYNCLINK_GT2_DEVICE_ID:
3531                devstr = "GT2";
3532                break;
3533        case SYNCLINK_GT4_DEVICE_ID:
3534                devstr = "GT4";
3535                break;
3536        case SYNCLINK_AC_DEVICE_ID:
3537                devstr = "AC";
3538                info->params.mode = MGSL_MODE_ASYNC;
3539                break;
3540        default:
3541                devstr = "(unknown model)";
3542        }
3543        printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3544                devstr, info->device_name, info->phys_reg_addr,
3545                info->irq_level, info->max_frame_size);
3546
3547#if SYNCLINK_GENERIC_HDLC
3548        hdlcdev_init(info);
3549#endif
3550}
3551
3552static const struct tty_port_operations slgt_port_ops = {
3553        .carrier_raised = carrier_raised,
3554        .dtr_rts = dtr_rts,
3555};
3556
3557/*
3558 *  allocate device instance structure, return NULL on failure
3559 */
3560static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3561{
3562        struct slgt_info *info;
3563
3564        info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3565
3566        if (!info) {
3567                DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3568                        driver_name, adapter_num, port_num));
3569        } else {
3570                tty_port_init(&info->port);
3571                info->port.ops = &slgt_port_ops;
3572                info->magic = MGSL_MAGIC;
3573                INIT_WORK(&info->task, bh_handler);
3574                info->max_frame_size = 4096;
3575                info->base_clock = 14745600;
3576                info->rbuf_fill_level = DMABUFSIZE;
3577                info->port.close_delay = 5*HZ/10;
3578                info->port.closing_wait = 30*HZ;
3579                init_waitqueue_head(&info->status_event_wait_q);
3580                init_waitqueue_head(&info->event_wait_q);
3581                spin_lock_init(&info->netlock);
3582                memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3583                info->idle_mode = HDLC_TXIDLE_FLAGS;
3584                info->adapter_num = adapter_num;
3585                info->port_num = port_num;
3586
3587                timer_setup(&info->tx_timer, tx_timeout, 0);
3588                timer_setup(&info->rx_timer, rx_timeout, 0);
3589
3590                /* Copy configuration info to device instance data */
3591                info->pdev = pdev;
3592                info->irq_level = pdev->irq;
3593                info->phys_reg_addr = pci_resource_start(pdev,0);
3594
3595                info->bus_type = MGSL_BUS_TYPE_PCI;
3596                info->irq_flags = IRQF_SHARED;
3597
3598                info->init_error = -1; /* assume error, set to 0 on successful init */
3599        }
3600
3601        return info;
3602}
3603
3604static void device_init(int adapter_num, struct pci_dev *pdev)
3605{
3606        struct slgt_info *port_array[SLGT_MAX_PORTS];
3607        int i;
3608        int port_count = 1;
3609
3610        if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3611                port_count = 2;
3612        else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3613                port_count = 4;
3614
3615        /* allocate device instances for all ports */
3616        for (i=0; i < port_count; ++i) {
3617                port_array[i] = alloc_dev(adapter_num, i, pdev);
3618                if (port_array[i] == NULL) {
3619                        for (--i; i >= 0; --i) {
3620                                tty_port_destroy(&port_array[i]->port);
3621                                kfree(port_array[i]);
3622                        }
3623                        return;
3624                }
3625        }
3626
3627        /* give copy of port_array to all ports and add to device list  */
3628        for (i=0; i < port_count; ++i) {
3629                memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3630                add_device(port_array[i]);
3631                port_array[i]->port_count = port_count;
3632                spin_lock_init(&port_array[i]->lock);
3633        }
3634
3635        /* Allocate and claim adapter resources */
3636        if (!claim_resources(port_array[0])) {
3637
3638                alloc_dma_bufs(port_array[0]);
3639
3640                /* copy resource information from first port to others */
3641                for (i = 1; i < port_count; ++i) {
3642                        port_array[i]->irq_level = port_array[0]->irq_level;
3643                        port_array[i]->reg_addr  = port_array[0]->reg_addr;
3644                        alloc_dma_bufs(port_array[i]);
3645                }
3646
3647                if (request_irq(port_array[0]->irq_level,
3648                                        slgt_interrupt,
3649                                        port_array[0]->irq_flags,
3650                                        port_array[0]->device_name,
3651                                        port_array[0]) < 0) {
3652                        DBGERR(("%s request_irq failed IRQ=%d\n",
3653                                port_array[0]->device_name,
3654                                port_array[0]->irq_level));
3655                } else {
3656                        port_array[0]->irq_requested = true;
3657                        adapter_test(port_array[0]);
3658                        for (i=1 ; i < port_count ; i++) {
3659                                port_array[i]->init_error = port_array[0]->init_error;
3660                                port_array[i]->gpio_present = port_array[0]->gpio_present;
3661                        }
3662                }
3663        }
3664
3665        for (i = 0; i < port_count; ++i) {
3666                struct slgt_info *info = port_array[i];
3667                tty_port_register_device(&info->port, serial_driver, info->line,
3668                                &info->pdev->dev);
3669        }
3670}
3671
3672static int init_one(struct pci_dev *dev,
3673                              const struct pci_device_id *ent)
3674{
3675        if (pci_enable_device(dev)) {
3676                printk("error enabling pci device %p\n", dev);
3677                return -EIO;
3678        }
3679        pci_set_master(dev);
3680        device_init(slgt_device_count, dev);
3681        return 0;
3682}
3683
3684static void remove_one(struct pci_dev *dev)
3685{
3686}
3687
3688static const struct tty_operations ops = {
3689        .open = open,
3690        .close = close,
3691        .write = write,
3692        .put_char = put_char,
3693        .flush_chars = flush_chars,
3694        .write_room = write_room,
3695        .chars_in_buffer = chars_in_buffer,
3696        .flush_buffer = flush_buffer,
3697        .ioctl = ioctl,
3698        .compat_ioctl = slgt_compat_ioctl,
3699        .throttle = throttle,
3700        .unthrottle = unthrottle,
3701        .send_xchar = send_xchar,
3702        .break_ctl = set_break,
3703        .wait_until_sent = wait_until_sent,
3704        .set_termios = set_termios,
3705        .stop = tx_hold,
3706        .start = tx_release,
3707        .hangup = hangup,
3708        .tiocmget = tiocmget,
3709        .tiocmset = tiocmset,
3710        .get_icount = get_icount,
3711        .proc_show = synclink_gt_proc_show,
3712};
3713
3714static void slgt_cleanup(void)
3715{
3716        int rc;
3717        struct slgt_info *info;
3718        struct slgt_info *tmp;
3719
3720        printk(KERN_INFO "unload %s\n", driver_name);
3721
3722        if (serial_driver) {
3723                for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3724                        tty_unregister_device(serial_driver, info->line);
3725                rc = tty_unregister_driver(serial_driver);
3726                if (rc)
3727                        DBGERR(("tty_unregister_driver error=%d\n", rc));
3728                put_tty_driver(serial_driver);
3729        }
3730
3731        /* reset devices */
3732        info = slgt_device_list;
3733        while(info) {
3734                reset_port(info);
3735                info = info->next_device;
3736        }
3737
3738        /* release devices */
3739        info = slgt_device_list;
3740        while(info) {
3741#if SYNCLINK_GENERIC_HDLC
3742                hdlcdev_exit(info);
3743#endif
3744                free_dma_bufs(info);
3745                free_tmp_rbuf(info);
3746                if (info->port_num == 0)
3747                        release_resources(info);
3748                tmp = info;
3749                info = info->next_device;
3750                tty_port_destroy(&tmp->port);
3751                kfree(tmp);
3752        }
3753
3754        if (pci_registered)
3755                pci_unregister_driver(&pci_driver);
3756}
3757
3758/*
3759 *  Driver initialization entry point.
3760 */
3761static int __init slgt_init(void)
3762{
3763        int rc;
3764
3765        printk(KERN_INFO "%s\n", driver_name);
3766
3767        serial_driver = alloc_tty_driver(MAX_DEVICES);
3768        if (!serial_driver) {
3769                printk("%s can't allocate tty driver\n", driver_name);
3770                return -ENOMEM;
3771        }
3772
3773        /* Initialize the tty_driver structure */
3774
3775        serial_driver->driver_name = slgt_driver_name;
3776        serial_driver->name = tty_dev_prefix;
3777        serial_driver->major = ttymajor;
3778        serial_driver->minor_start = 64;
3779        serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3780        serial_driver->subtype = SERIAL_TYPE_NORMAL;
3781        serial_driver->init_termios = tty_std_termios;
3782        serial_driver->init_termios.c_cflag =
3783                B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3784        serial_driver->init_termios.c_ispeed = 9600;
3785        serial_driver->init_termios.c_ospeed = 9600;
3786        serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3787        tty_set_operations(serial_driver, &ops);
3788        if ((rc = tty_register_driver(serial_driver)) < 0) {
3789                DBGERR(("%s can't register serial driver\n", driver_name));
3790                put_tty_driver(serial_driver);
3791                serial_driver = NULL;
3792                goto error;
3793        }
3794
3795        printk(KERN_INFO "%s, tty major#%d\n",
3796               driver_name, serial_driver->major);
3797
3798        slgt_device_count = 0;
3799        if ((rc = pci_register_driver(&pci_driver)) < 0) {
3800                printk("%s pci_register_driver error=%d\n", driver_name, rc);
3801                goto error;
3802        }
3803        pci_registered = true;
3804
3805        if (!slgt_device_list)
3806                printk("%s no devices found\n",driver_name);
3807
3808        return 0;
3809
3810error:
3811        slgt_cleanup();
3812        return rc;
3813}
3814
3815static void __exit slgt_exit(void)
3816{
3817        slgt_cleanup();
3818}
3819
3820module_init(slgt_init);
3821module_exit(slgt_exit);
3822
3823/*
3824 * register access routines
3825 */
3826
3827#define CALC_REGADDR() \
3828        unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3829        if (addr >= 0x80) \
3830                reg_addr += (info->port_num) * 32; \
3831        else if (addr >= 0x40)  \
3832                reg_addr += (info->port_num) * 16;
3833
3834static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3835{
3836        CALC_REGADDR();
3837        return readb((void __iomem *)reg_addr);
3838}
3839
3840static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3841{
3842        CALC_REGADDR();
3843        writeb(value, (void __iomem *)reg_addr);
3844}
3845
3846static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3847{
3848        CALC_REGADDR();
3849        return readw((void __iomem *)reg_addr);
3850}
3851
3852static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3853{
3854        CALC_REGADDR();
3855        writew(value, (void __iomem *)reg_addr);
3856}
3857
3858static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3859{
3860        CALC_REGADDR();
3861        return readl((void __iomem *)reg_addr);
3862}
3863
3864static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3865{
3866        CALC_REGADDR();
3867        writel(value, (void __iomem *)reg_addr);
3868}
3869
3870static void rdma_reset(struct slgt_info *info)
3871{
3872        unsigned int i;
3873
3874        /* set reset bit */
3875        wr_reg32(info, RDCSR, BIT1);
3876
3877        /* wait for enable bit cleared */
3878        for(i=0 ; i < 1000 ; i++)
3879                if (!(rd_reg32(info, RDCSR) & BIT0))
3880                        break;
3881}
3882
3883static void tdma_reset(struct slgt_info *info)
3884{
3885        unsigned int i;
3886
3887        /* set reset bit */
3888        wr_reg32(info, TDCSR, BIT1);
3889
3890        /* wait for enable bit cleared */
3891        for(i=0 ; i < 1000 ; i++)
3892                if (!(rd_reg32(info, TDCSR) & BIT0))
3893                        break;
3894}
3895
3896/*
3897 * enable internal loopback
3898 * TxCLK and RxCLK are generated from BRG
3899 * and TxD is looped back to RxD internally.
3900 */
3901static void enable_loopback(struct slgt_info *info)
3902{
3903        /* SCR (serial control) BIT2=loopback enable */
3904        wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3905
3906        if (info->params.mode != MGSL_MODE_ASYNC) {
3907                /* CCR (clock control)
3908                 * 07..05  tx clock source (010 = BRG)
3909                 * 04..02  rx clock source (010 = BRG)
3910                 * 01      auxclk enable   (0 = disable)
3911                 * 00      BRG enable      (1 = enable)
3912                 *
3913                 * 0100 1001
3914                 */
3915                wr_reg8(info, CCR, 0x49);
3916
3917                /* set speed if available, otherwise use default */
3918                if (info->params.clock_speed)
3919                        set_rate(info, info->params.clock_speed);
3920                else
3921                        set_rate(info, 3686400);
3922        }
3923}
3924
3925/*
3926 *  set baud rate generator to specified rate
3927 */
3928static void set_rate(struct slgt_info *info, u32 rate)
3929{
3930        unsigned int div;
3931        unsigned int osc = info->base_clock;
3932
3933        /* div = osc/rate - 1
3934         *
3935         * Round div up if osc/rate is not integer to
3936         * force to next slowest rate.
3937         */
3938
3939        if (rate) {
3940                div = osc/rate;
3941                if (!(osc % rate) && div)
3942                        div--;
3943                wr_reg16(info, BDR, (unsigned short)div);
3944        }
3945}
3946
3947static void rx_stop(struct slgt_info *info)
3948{
3949        unsigned short val;
3950
3951        /* disable and reset receiver */
3952        val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3953        wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3954        wr_reg16(info, RCR, val);                  /* clear reset bit */
3955
3956        slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3957
3958        /* clear pending rx interrupts */
3959        wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3960
3961        rdma_reset(info);
3962
3963        info->rx_enabled = false;
3964        info->rx_restart = false;
3965}
3966
3967static void rx_start(struct slgt_info *info)
3968{
3969        unsigned short val;
3970
3971        slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3972
3973        /* clear pending rx overrun IRQ */
3974        wr_reg16(info, SSR, IRQ_RXOVER);
3975
3976        /* reset and disable receiver */
3977        val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3978        wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3979        wr_reg16(info, RCR, val);                  /* clear reset bit */
3980
3981        rdma_reset(info);
3982        reset_rbufs(info);
3983
3984        if (info->rx_pio) {
3985                /* rx request when rx FIFO not empty */
3986                wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3987                slgt_irq_on(info, IRQ_RXDATA);
3988                if (info->params.mode == MGSL_MODE_ASYNC) {
3989                        /* enable saving of rx status */
3990                        wr_reg32(info, RDCSR, BIT6);
3991                }
3992        } else {
3993                /* rx request when rx FIFO half full */
3994                wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3995                /* set 1st descriptor address */
3996                wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3997
3998                if (info->params.mode != MGSL_MODE_ASYNC) {
3999                        /* enable rx DMA and DMA interrupt */
4000                        wr_reg32(info, RDCSR, (BIT2 + BIT0));
4001                } else {
4002                        /* enable saving of rx status, rx DMA and DMA interrupt */
4003                        wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4004                }
4005        }
4006
4007        slgt_irq_on(info, IRQ_RXOVER);
4008
4009        /* enable receiver */
4010        wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4011
4012        info->rx_restart = false;
4013        info->rx_enabled = true;
4014}
4015
4016static void tx_start(struct slgt_info *info)
4017{
4018        if (!info->tx_enabled) {
4019                wr_reg16(info, TCR,
4020                         (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4021                info->tx_enabled = true;
4022        }
4023
4024        if (desc_count(info->tbufs[info->tbuf_start])) {
4025                info->drop_rts_on_tx_done = false;
4026
4027                if (info->params.mode != MGSL_MODE_ASYNC) {
4028                        if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4029                                get_signals(info);
4030                                if (!(info->signals & SerialSignal_RTS)) {
4031                                        info->signals |= SerialSignal_RTS;
4032                                        set_signals(info);
4033                                        info->drop_rts_on_tx_done = true;
4034                                }
4035                        }
4036
4037                        slgt_irq_off(info, IRQ_TXDATA);
4038                        slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4039                        /* clear tx idle and underrun status bits */
4040                        wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4041                } else {
4042                        slgt_irq_off(info, IRQ_TXDATA);
4043                        slgt_irq_on(info, IRQ_TXIDLE);
4044                        /* clear tx idle status bit */
4045                        wr_reg16(info, SSR, IRQ_TXIDLE);
4046                }
4047                /* set 1st descriptor address and start DMA */
4048                wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4049                wr_reg32(info, TDCSR, BIT2 + BIT0);
4050                info->tx_active = true;
4051        }
4052}
4053
4054static void tx_stop(struct slgt_info *info)
4055{
4056        unsigned short val;
4057
4058        del_timer(&info->tx_timer);
4059
4060        tdma_reset(info);
4061
4062        /* reset and disable transmitter */
4063        val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
4064        wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4065
4066        slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4067
4068        /* clear tx idle and underrun status bit */
4069        wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4070
4071        reset_tbufs(info);
4072
4073        info->tx_enabled = false;
4074        info->tx_active = false;
4075}
4076
4077static void reset_port(struct slgt_info *info)
4078{
4079        if (!info->reg_addr)
4080                return;
4081
4082        tx_stop(info);
4083        rx_stop(info);
4084
4085        info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4086        set_signals(info);
4087
4088        slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4089}
4090
4091static void reset_adapter(struct slgt_info *info)
4092{
4093        int i;
4094        for (i=0; i < info->port_count; ++i) {
4095                if (info->port_array[i])
4096                        reset_port(info->port_array[i]);
4097        }
4098}
4099
4100static void async_mode(struct slgt_info *info)
4101{
4102        unsigned short val;
4103
4104        slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4105        tx_stop(info);
4106        rx_stop(info);
4107
4108        /* TCR (tx control)
4109         *
4110         * 15..13  mode, 010=async
4111         * 12..10  encoding, 000=NRZ
4112         * 09      parity enable
4113         * 08      1=odd parity, 0=even parity
4114         * 07      1=RTS driver control
4115         * 06      1=break enable
4116         * 05..04  character length
4117         *         00=5 bits
4118         *         01=6 bits
4119         *         10=7 bits
4120         *         11=8 bits
4121         * 03      0=1 stop bit, 1=2 stop bits
4122         * 02      reset
4123         * 01      enable
4124         * 00      auto-CTS enable
4125         */
4126        val = 0x4000;
4127
4128        if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4129                val |= BIT7;
4130
4131        if (info->params.parity != ASYNC_PARITY_NONE) {
4132                val |= BIT9;
4133                if (info->params.parity == ASYNC_PARITY_ODD)
4134                        val |= BIT8;
4135        }
4136
4137        switch (info->params.data_bits)
4138        {
4139        case 6: val |= BIT4; break;
4140        case 7: val |= BIT5; break;
4141        case 8: val |= BIT5 + BIT4; break;
4142        }
4143
4144        if (info->params.stop_bits != 1)
4145                val |= BIT3;
4146
4147        if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4148                val |= BIT0;
4149
4150        wr_reg16(info, TCR, val);
4151
4152        /* RCR (rx control)
4153         *
4154         * 15..13  mode, 010=async
4155         * 12..10  encoding, 000=NRZ
4156         * 09      parity enable
4157         * 08      1=odd parity, 0=even parity
4158         * 07..06  reserved, must be 0
4159         * 05..04  character length
4160         *         00=5 bits
4161         *         01=6 bits
4162         *         10=7 bits
4163         *         11=8 bits
4164         * 03      reserved, must be zero
4165         * 02      reset
4166         * 01      enable
4167         * 00      auto-DCD enable
4168         */
4169        val = 0x4000;
4170
4171        if (info->params.parity != ASYNC_PARITY_NONE) {
4172                val |= BIT9;
4173                if (info->params.parity == ASYNC_PARITY_ODD)
4174                        val |= BIT8;
4175        }
4176
4177        switch (info->params.data_bits)
4178        {
4179        case 6: val |= BIT4; break;
4180        case 7: val |= BIT5; break;
4181        case 8: val |= BIT5 + BIT4; break;
4182        }
4183
4184        if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4185                val |= BIT0;
4186
4187        wr_reg16(info, RCR, val);
4188
4189        /* CCR (clock control)
4190         *
4191         * 07..05  011 = tx clock source is BRG/16
4192         * 04..02  010 = rx clock source is BRG
4193         * 01      0 = auxclk disabled
4194         * 00      1 = BRG enabled
4195         *
4196         * 0110 1001
4197         */
4198        wr_reg8(info, CCR, 0x69);
4199
4200        msc_set_vcr(info);
4201
4202        /* SCR (serial control)
4203         *
4204         * 15  1=tx req on FIFO half empty
4205         * 14  1=rx req on FIFO half full
4206         * 13  tx data  IRQ enable
4207         * 12  tx idle  IRQ enable
4208         * 11  rx break on IRQ enable
4209         * 10  rx data  IRQ enable
4210         * 09  rx break off IRQ enable
4211         * 08  overrun  IRQ enable
4212         * 07  DSR      IRQ enable
4213         * 06  CTS      IRQ enable
4214         * 05  DCD      IRQ enable
4215         * 04  RI       IRQ enable
4216         * 03  0=16x sampling, 1=8x sampling
4217         * 02  1=txd->rxd internal loopback enable
4218         * 01  reserved, must be zero
4219         * 00  1=master IRQ enable
4220         */
4221        val = BIT15 + BIT14 + BIT0;
4222        /* JCR[8] : 1 = x8 async mode feature available */
4223        if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4224            ((info->base_clock < (info->params.data_rate * 16)) ||
4225             (info->base_clock % (info->params.data_rate * 16)))) {
4226                /* use 8x sampling */
4227                val |= BIT3;
4228                set_rate(info, info->params.data_rate * 8);
4229        } else {
4230                /* use 16x sampling */
4231                set_rate(info, info->params.data_rate * 16);
4232        }
4233        wr_reg16(info, SCR, val);
4234
4235        slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4236
4237        if (info->params.loopback)
4238                enable_loopback(info);
4239}
4240
4241static void sync_mode(struct slgt_info *info)
4242{
4243        unsigned short val;
4244
4245        slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4246        tx_stop(info);
4247        rx_stop(info);
4248
4249        /* TCR (tx control)
4250         *
4251         * 15..13  mode
4252         *         000=HDLC/SDLC
4253         *         001=raw bit synchronous
4254         *         010=asynchronous/isochronous
4255         *         011=monosync byte synchronous
4256         *         100=bisync byte synchronous
4257         *         101=xsync byte synchronous
4258         * 12..10  encoding
4259         * 09      CRC enable
4260         * 08      CRC32
4261         * 07      1=RTS driver control
4262         * 06      preamble enable
4263         * 05..04  preamble length
4264         * 03      share open/close flag
4265         * 02      reset
4266         * 01      enable
4267         * 00      auto-CTS enable
4268         */
4269        val = BIT2;
4270
4271        switch(info->params.mode) {
4272        case MGSL_MODE_XSYNC:
4273                val |= BIT15 + BIT13;
4274                break;
4275        case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4276        case MGSL_MODE_BISYNC:   val |= BIT15; break;
4277        case MGSL_MODE_RAW:      val |= BIT13; break;
4278        }
4279        if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4280                val |= BIT7;
4281
4282        switch(info->params.encoding)
4283        {
4284        case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4285        case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4286        case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4287        case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4288        case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4289        case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4290        case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4291        }
4292
4293        switch (info->params.crc_type & HDLC_CRC_MASK)
4294        {
4295        case HDLC_CRC_16_CCITT: val |= BIT9; break;
4296        case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4297        }
4298
4299        if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4300                val |= BIT6;
4301
4302        switch (info->params.preamble_length)
4303        {
4304        case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4305        case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4306        case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4307        }
4308
4309        if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4310                val |= BIT0;
4311
4312        wr_reg16(info, TCR, val);
4313
4314        /* TPR (transmit preamble) */
4315
4316        switch (info->params.preamble)
4317        {
4318        case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4319        case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4320        case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4321        case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4322        case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4323        default:                          val = 0x7e; break;
4324        }
4325        wr_reg8(info, TPR, (unsigned char)val);
4326
4327        /* RCR (rx control)
4328         *
4329         * 15..13  mode
4330         *         000=HDLC/SDLC
4331         *         001=raw bit synchronous
4332         *         010=asynchronous/isochronous
4333         *         011=monosync byte synchronous
4334         *         100=bisync byte synchronous
4335         *         101=xsync byte synchronous
4336         * 12..10  encoding
4337         * 09      CRC enable
4338         * 08      CRC32
4339         * 07..03  reserved, must be 0
4340         * 02      reset
4341         * 01      enable
4342         * 00      auto-DCD enable
4343         */
4344        val = 0;
4345
4346        switch(info->params.mode) {
4347        case MGSL_MODE_XSYNC:
4348                val |= BIT15 + BIT13;
4349                break;
4350        case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4351        case MGSL_MODE_BISYNC:   val |= BIT15; break;
4352        case MGSL_MODE_RAW:      val |= BIT13; break;
4353        }
4354
4355        switch(info->params.encoding)
4356        {
4357        case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4358        case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4359        case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4360        case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4361        case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4362        case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4363        case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4364        }
4365
4366        switch (info->params.crc_type & HDLC_CRC_MASK)
4367        {
4368        case HDLC_CRC_16_CCITT: val |= BIT9; break;
4369        case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4370        }
4371
4372        if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4373                val |= BIT0;
4374
4375        wr_reg16(info, RCR, val);
4376
4377        /* CCR (clock control)
4378         *
4379         * 07..05  tx clock source
4380         * 04..02  rx clock source
4381         * 01      auxclk enable
4382         * 00      BRG enable
4383         */
4384        val = 0;
4385
4386        if (info->params.flags & HDLC_FLAG_TXC_BRG)
4387        {
4388                // when RxC source is DPLL, BRG generates 16X DPLL
4389                // reference clock, so take TxC from BRG/16 to get
4390                // transmit clock at actual data rate
4391                if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4392                        val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4393                else
4394                        val |= BIT6;    /* 010, txclk = BRG */
4395        }
4396        else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4397                val |= BIT7;    /* 100, txclk = DPLL Input */
4398        else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4399                val |= BIT5;    /* 001, txclk = RXC Input */
4400
4401        if (info->params.flags & HDLC_FLAG_RXC_BRG)
4402                val |= BIT3;    /* 010, rxclk = BRG */
4403        else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4404                val |= BIT4;    /* 100, rxclk = DPLL */
4405        else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4406                val |= BIT2;    /* 001, rxclk = TXC Input */
4407
4408        if (info->params.clock_speed)
4409                val |= BIT1 + BIT0;
4410
4411        wr_reg8(info, CCR, (unsigned char)val);
4412
4413        if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4414        {
4415                // program DPLL mode
4416                switch(info->params.encoding)
4417                {
4418                case HDLC_ENCODING_BIPHASE_MARK:
4419                case HDLC_ENCODING_BIPHASE_SPACE:
4420                        val = BIT7; break;
4421                case HDLC_ENCODING_BIPHASE_LEVEL:
4422                case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4423                        val = BIT7 + BIT6; break;
4424                default: val = BIT6;    // NRZ encodings
4425                }
4426                wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4427
4428                // DPLL requires a 16X reference clock from BRG
4429                set_rate(info, info->params.clock_speed * 16);
4430        }
4431        else
4432                set_rate(info, info->params.clock_speed);
4433
4434        tx_set_idle(info);
4435
4436        msc_set_vcr(info);
4437
4438        /* SCR (serial control)
4439         *
4440         * 15  1=tx req on FIFO half empty
4441         * 14  1=rx req on FIFO half full
4442         * 13  tx data  IRQ enable
4443         * 12  tx idle  IRQ enable
4444         * 11  underrun IRQ enable
4445         * 10  rx data  IRQ enable
4446         * 09  rx idle  IRQ enable
4447         * 08  overrun  IRQ enable
4448         * 07  DSR      IRQ enable
4449         * 06  CTS      IRQ enable
4450         * 05  DCD      IRQ enable
4451         * 04  RI       IRQ enable
4452         * 03  reserved, must be zero
4453         * 02  1=txd->rxd internal loopback enable
4454         * 01  reserved, must be zero
4455         * 00  1=master IRQ enable
4456         */
4457        wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4458
4459        if (info->params.loopback)
4460                enable_loopback(info);
4461}
4462
4463/*
4464 *  set transmit idle mode
4465 */
4466static void tx_set_idle(struct slgt_info *info)
4467{
4468        unsigned char val;
4469        unsigned short tcr;
4470
4471        /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4472         * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4473         */
4474        tcr = rd_reg16(info, TCR);
4475        if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4476                /* disable preamble, set idle size to 16 bits */
4477                tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4478                /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4479                wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4480        } else if (!(tcr & BIT6)) {
4481                /* preamble is disabled, set idle size to 8 bits */
4482                tcr &= ~(BIT5 + BIT4);
4483        }
4484        wr_reg16(info, TCR, tcr);
4485
4486        if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4487                /* LSB of custom tx idle specified in tx idle register */
4488                val = (unsigned char)(info->idle_mode & 0xff);
4489        } else {
4490                /* standard 8 bit idle patterns */
4491                switch(info->idle_mode)
4492                {
4493                case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4494                case HDLC_TXIDLE_ALT_ZEROS_ONES:
4495                case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4496                case HDLC_TXIDLE_ZEROS:
4497                case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4498                default:                         val = 0xff;
4499                }
4500        }
4501
4502        wr_reg8(info, TIR, val);
4503}
4504
4505/*
4506 * get state of V24 status (input) signals
4507 */
4508static void get_signals(struct slgt_info *info)
4509{
4510        unsigned short status = rd_reg16(info, SSR);
4511
4512        /* clear all serial signals except RTS and DTR */
4513        info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4514
4515        if (status & BIT3)
4516                info->signals |= SerialSignal_DSR;
4517        if (status & BIT2)
4518                info->signals |= SerialSignal_CTS;
4519        if (status & BIT1)
4520                info->signals |= SerialSignal_DCD;
4521        if (status & BIT0)
4522                info->signals |= SerialSignal_RI;
4523}
4524
4525/*
4526 * set V.24 Control Register based on current configuration
4527 */
4528static void msc_set_vcr(struct slgt_info *info)
4529{
4530        unsigned char val = 0;
4531
4532        /* VCR (V.24 control)
4533         *
4534         * 07..04  serial IF select
4535         * 03      DTR
4536         * 02      RTS
4537         * 01      LL
4538         * 00      RL
4539         */
4540
4541        switch(info->if_mode & MGSL_INTERFACE_MASK)
4542        {
4543        case MGSL_INTERFACE_RS232:
4544                val |= BIT5; /* 0010 */
4545                break;
4546        case MGSL_INTERFACE_V35:
4547                val |= BIT7 + BIT6 + BIT5; /* 1110 */
4548                break;
4549        case MGSL_INTERFACE_RS422:
4550                val |= BIT6; /* 0100 */
4551                break;
4552        }
4553
4554        if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4555                val |= BIT4;
4556        if (info->signals & SerialSignal_DTR)
4557                val |= BIT3;
4558        if (info->signals & SerialSignal_RTS)
4559                val |= BIT2;
4560        if (info->if_mode & MGSL_INTERFACE_LL)
4561                val |= BIT1;
4562        if (info->if_mode & MGSL_INTERFACE_RL)
4563                val |= BIT0;
4564        wr_reg8(info, VCR, val);
4565}
4566
4567/*
4568 * set state of V24 control (output) signals
4569 */
4570static void set_signals(struct slgt_info *info)
4571{
4572        unsigned char val = rd_reg8(info, VCR);
4573        if (info->signals & SerialSignal_DTR)
4574                val |= BIT3;
4575        else
4576                val &= ~BIT3;
4577        if (info->signals & SerialSignal_RTS)
4578                val |= BIT2;
4579        else
4580                val &= ~BIT2;
4581        wr_reg8(info, VCR, val);
4582}
4583
4584/*
4585 * free range of receive DMA buffers (i to last)
4586 */
4587static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4588{
4589        int done = 0;
4590
4591        while(!done) {
4592                /* reset current buffer for reuse */
4593                info->rbufs[i].status = 0;
4594                set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4595                if (i == last)
4596                        done = 1;
4597                if (++i == info->rbuf_count)
4598                        i = 0;
4599        }
4600        info->rbuf_current = i;
4601}
4602
4603/*
4604 * mark all receive DMA buffers as free
4605 */
4606static void reset_rbufs(struct slgt_info *info)
4607{
4608        free_rbufs(info, 0, info->rbuf_count - 1);
4609        info->rbuf_fill_index = 0;
4610        info->rbuf_fill_count = 0;
4611}
4612
4613/*
4614 * pass receive HDLC frame to upper layer
4615 *
4616 * return true if frame available, otherwise false
4617 */
4618static bool rx_get_frame(struct slgt_info *info)
4619{
4620        unsigned int start, end;
4621        unsigned short status;
4622        unsigned int framesize = 0;
4623        unsigned long flags;
4624        struct tty_struct *tty = info->port.tty;
4625        unsigned char addr_field = 0xff;
4626        unsigned int crc_size = 0;
4627
4628        switch (info->params.crc_type & HDLC_CRC_MASK) {
4629        case HDLC_CRC_16_CCITT: crc_size = 2; break;
4630        case HDLC_CRC_32_CCITT: crc_size = 4; break;
4631        }
4632
4633check_again:
4634
4635        framesize = 0;
4636        addr_field = 0xff;
4637        start = end = info->rbuf_current;
4638
4639        for (;;) {
4640                if (!desc_complete(info->rbufs[end]))
4641                        goto cleanup;
4642
4643                if (framesize == 0 && info->params.addr_filter != 0xff)
4644                        addr_field = info->rbufs[end].buf[0];
4645
4646                framesize += desc_count(info->rbufs[end]);
4647
4648                if (desc_eof(info->rbufs[end]))
4649                        break;
4650
4651                if (++end == info->rbuf_count)
4652                        end = 0;
4653
4654                if (end == info->rbuf_current) {
4655                        if (info->rx_enabled){
4656                                spin_lock_irqsave(&info->lock,flags);
4657                                rx_start(info);
4658                                spin_unlock_irqrestore(&info->lock,flags);
4659                        }
4660                        goto cleanup;
4661                }
4662        }
4663
4664        /* status
4665         *
4666         * 15      buffer complete
4667         * 14..06  reserved
4668         * 05..04  residue
4669         * 02      eof (end of frame)
4670         * 01      CRC error
4671         * 00      abort
4672         */
4673        status = desc_status(info->rbufs[end]);
4674
4675        /* ignore CRC bit if not using CRC (bit is undefined) */
4676        if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4677                status &= ~BIT1;
4678
4679        if (framesize == 0 ||
4680                 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4681                free_rbufs(info, start, end);
4682                goto check_again;
4683        }
4684
4685        if (framesize < (2 + crc_size) || status & BIT0) {
4686                info->icount.rxshort++;
4687                framesize = 0;
4688        } else if (status & BIT1) {
4689                info->icount.rxcrc++;
4690                if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4691                        framesize = 0;
4692        }
4693
4694#if SYNCLINK_GENERIC_HDLC
4695        if (framesize == 0) {
4696                info->netdev->stats.rx_errors++;
4697                info->netdev->stats.rx_frame_errors++;
4698        }
4699#endif
4700
4701        DBGBH(("%s rx frame status=%04X size=%d\n",
4702                info->device_name, status, framesize));
4703        DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4704
4705        if (framesize) {
4706                if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4707                        framesize -= crc_size;
4708                        crc_size = 0;
4709                }
4710
4711                if (framesize > info->max_frame_size + crc_size)
4712                        info->icount.rxlong++;
4713                else {
4714                        /* copy dma buffer(s) to contiguous temp buffer */
4715                        int copy_count = framesize;
4716                        int i = start;
4717                        unsigned char *p = info->tmp_rbuf;
4718                        info->tmp_rbuf_count = framesize;
4719
4720                        info->icount.rxok++;
4721
4722                        while(copy_count) {
4723                                int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4724                                memcpy(p, info->rbufs[i].buf, partial_count);
4725                                p += partial_count;
4726                                copy_count -= partial_count;
4727                                if (++i == info->rbuf_count)
4728                                        i = 0;
4729                        }
4730
4731                        if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4732                                *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4733                                framesize++;
4734                        }
4735
4736#if SYNCLINK_GENERIC_HDLC
4737                        if (info->netcount)
4738                                hdlcdev_rx(info,info->tmp_rbuf, framesize);
4739                        else
4740#endif
4741                                ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4742                }
4743        }
4744        free_rbufs(info, start, end);
4745        return true;
4746
4747cleanup:
4748        return false;
4749}
4750
4751/*
4752 * pass receive buffer (RAW synchronous mode) to tty layer
4753 * return true if buffer available, otherwise false
4754 */
4755static bool rx_get_buf(struct slgt_info *info)
4756{
4757        unsigned int i = info->rbuf_current;
4758        unsigned int count;
4759
4760        if (!desc_complete(info->rbufs[i]))
4761                return false;
4762        count = desc_count(info->rbufs[i]);
4763        switch(info->params.mode) {
4764        case MGSL_MODE_MONOSYNC:
4765        case MGSL_MODE_BISYNC:
4766        case MGSL_MODE_XSYNC:
4767                /* ignore residue in byte synchronous modes */
4768                if (desc_residue(info->rbufs[i]))
4769                        count--;
4770                break;
4771        }
4772        DBGDATA(info, info->rbufs[i].buf, count, "rx");
4773        DBGINFO(("rx_get_buf size=%d\n", count));
4774        if (count)
4775                ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4776                                  info->flag_buf, count);
4777        free_rbufs(info, i, i);
4778        return true;
4779}
4780
4781static void reset_tbufs(struct slgt_info *info)
4782{
4783        unsigned int i;
4784        info->tbuf_current = 0;
4785        for (i=0 ; i < info->tbuf_count ; i++) {
4786                info->tbufs[i].status = 0;
4787                info->tbufs[i].count  = 0;
4788        }
4789}
4790
4791/*
4792 * return number of free transmit DMA buffers
4793 */
4794static unsigned int free_tbuf_count(struct slgt_info *info)
4795{
4796        unsigned int count = 0;
4797        unsigned int i = info->tbuf_current;
4798
4799        do
4800        {
4801                if (desc_count(info->tbufs[i]))
4802                        break; /* buffer in use */
4803                ++count;
4804                if (++i == info->tbuf_count)
4805                        i=0;
4806        } while (i != info->tbuf_current);
4807
4808        /* if tx DMA active, last zero count buffer is in use */
4809        if (count && (rd_reg32(info, TDCSR) & BIT0))
4810                --count;
4811
4812        return count;
4813}
4814
4815/*
4816 * return number of bytes in unsent transmit DMA buffers
4817 * and the serial controller tx FIFO
4818 */
4819static unsigned int tbuf_bytes(struct slgt_info *info)
4820{
4821        unsigned int total_count = 0;
4822        unsigned int i = info->tbuf_current;
4823        unsigned int reg_value;
4824        unsigned int count;
4825        unsigned int active_buf_count = 0;
4826
4827        /*
4828         * Add descriptor counts for all tx DMA buffers.
4829         * If count is zero (cleared by DMA controller after read),
4830         * the buffer is complete or is actively being read from.
4831         *
4832         * Record buf_count of last buffer with zero count starting
4833         * from current ring position. buf_count is mirror
4834         * copy of count and is not cleared by serial controller.
4835         * If DMA controller is active, that buffer is actively
4836         * being read so add to total.
4837         */
4838        do {
4839                count = desc_count(info->tbufs[i]);
4840                if (count)
4841                        total_count += count;
4842                else if (!total_count)
4843                        active_buf_count = info->tbufs[i].buf_count;
4844                if (++i == info->tbuf_count)
4845                        i = 0;
4846        } while (i != info->tbuf_current);
4847
4848        /* read tx DMA status register */
4849        reg_value = rd_reg32(info, TDCSR);
4850
4851        /* if tx DMA active, last zero count buffer is in use */
4852        if (reg_value & BIT0)
4853                total_count += active_buf_count;
4854
4855        /* add tx FIFO count = reg_value[15..8] */
4856        total_count += (reg_value >> 8) & 0xff;
4857
4858        /* if transmitter active add one byte for shift register */
4859        if (info->tx_active)
4860                total_count++;
4861
4862        return total_count;
4863}
4864
4865/*
4866 * load data into transmit DMA buffer ring and start transmitter if needed
4867 * return true if data accepted, otherwise false (buffers full)
4868 */
4869static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4870{
4871        unsigned short count;
4872        unsigned int i;
4873        struct slgt_desc *d;
4874
4875        /* check required buffer space */
4876        if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4877                return false;
4878
4879        DBGDATA(info, buf, size, "tx");
4880
4881        /*
4882         * copy data to one or more DMA buffers in circular ring
4883         * tbuf_start   = first buffer for this data
4884         * tbuf_current = next free buffer
4885         *
4886         * Copy all data before making data visible to DMA controller by
4887         * setting descriptor count of the first buffer.
4888         * This prevents an active DMA controller from reading the first DMA
4889         * buffers of a frame and stopping before the final buffers are filled.
4890         */
4891
4892        info->tbuf_start = i = info->tbuf_current;
4893
4894        while (size) {
4895                d = &info->tbufs[i];
4896
4897                count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4898                memcpy(d->buf, buf, count);
4899
4900                size -= count;
4901                buf  += count;
4902
4903                /*
4904                 * set EOF bit for last buffer of HDLC frame or
4905                 * for every buffer in raw mode
4906                 */
4907                if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4908                    info->params.mode == MGSL_MODE_RAW)
4909                        set_desc_eof(*d, 1);
4910                else
4911                        set_desc_eof(*d, 0);
4912
4913                /* set descriptor count for all but first buffer */
4914                if (i != info->tbuf_start)
4915                        set_desc_count(*d, count);
4916                d->buf_count = count;
4917
4918                if (++i == info->tbuf_count)
4919                        i = 0;
4920        }
4921
4922        info->tbuf_current = i;
4923
4924        /* set first buffer count to make new data visible to DMA controller */
4925        d = &info->tbufs[info->tbuf_start];
4926        set_desc_count(*d, d->buf_count);
4927
4928        /* start transmitter if needed and update transmit timeout */
4929        if (!info->tx_active)
4930                tx_start(info);
4931        update_tx_timer(info);
4932
4933        return true;
4934}
4935
4936static int register_test(struct slgt_info *info)
4937{
4938        static unsigned short patterns[] =
4939                {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4940        static unsigned int count = ARRAY_SIZE(patterns);
4941        unsigned int i;
4942        int rc = 0;
4943
4944        for (i=0 ; i < count ; i++) {
4945                wr_reg16(info, TIR, patterns[i]);
4946                wr_reg16(info, BDR, patterns[(i+1)%count]);
4947                if ((rd_reg16(info, TIR) != patterns[i]) ||
4948                    (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4949                        rc = -ENODEV;
4950                        break;
4951                }
4952        }
4953        info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4954        info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4955        return rc;
4956}
4957
4958static int irq_test(struct slgt_info *info)
4959{
4960        unsigned long timeout;
4961        unsigned long flags;
4962        struct tty_struct *oldtty = info->port.tty;
4963        u32 speed = info->params.data_rate;
4964
4965        info->params.data_rate = 921600;
4966        info->port.tty = NULL;
4967
4968        spin_lock_irqsave(&info->lock, flags);
4969        async_mode(info);
4970        slgt_irq_on(info, IRQ_TXIDLE);
4971
4972        /* enable transmitter */
4973        wr_reg16(info, TCR,
4974                (unsigned short)(rd_reg16(info, TCR) | BIT1));
4975
4976        /* write one byte and wait for tx idle */
4977        wr_reg16(info, TDR, 0);
4978
4979        /* assume failure */
4980        info->init_error = DiagStatus_IrqFailure;
4981        info->irq_occurred = false;
4982
4983        spin_unlock_irqrestore(&info->lock, flags);
4984
4985        timeout=100;
4986        while(timeout-- && !info->irq_occurred)
4987                msleep_interruptible(10);
4988
4989        spin_lock_irqsave(&info->lock,flags);
4990        reset_port(info);
4991        spin_unlock_irqrestore(&info->lock,flags);
4992
4993        info->params.data_rate = speed;
4994        info->port.tty = oldtty;
4995
4996        info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4997        return info->irq_occurred ? 0 : -ENODEV;
4998}
4999
5000static int loopback_test_rx(struct slgt_info *info)
5001{
5002        unsigned char *src, *dest;
5003        int count;
5004
5005        if (desc_complete(info->rbufs[0])) {
5006                count = desc_count(info->rbufs[0]);
5007                src   = info->rbufs[0].buf;
5008                dest  = info->tmp_rbuf;
5009
5010                for( ; count ; count-=2, src+=2) {
5011                        /* src=data byte (src+1)=status byte */
5012                        if (!(*(src+1) & (BIT9 + BIT8))) {
5013                                *dest = *src;
5014                                dest++;
5015                                info->tmp_rbuf_count++;
5016                        }
5017                }
5018                DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5019                return 1;
5020        }
5021        return 0;
5022}
5023
5024static int loopback_test(struct slgt_info *info)
5025{
5026#define TESTFRAMESIZE 20
5027
5028        unsigned long timeout;
5029        u16 count = TESTFRAMESIZE;
5030        unsigned char buf[TESTFRAMESIZE];
5031        int rc = -ENODEV;
5032        unsigned long flags;
5033
5034        struct tty_struct *oldtty = info->port.tty;
5035        MGSL_PARAMS params;
5036
5037        memcpy(&params, &info->params, sizeof(params));
5038
5039        info->params.mode = MGSL_MODE_ASYNC;
5040        info->params.data_rate = 921600;
5041        info->params.loopback = 1;
5042        info->port.tty = NULL;
5043
5044        /* build and send transmit frame */
5045        for (count = 0; count < TESTFRAMESIZE; ++count)
5046                buf[count] = (unsigned char)count;
5047
5048        info->tmp_rbuf_count = 0;
5049        memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5050
5051        /* program hardware for HDLC and enabled receiver */
5052        spin_lock_irqsave(&info->lock,flags);
5053        async_mode(info);
5054        rx_start(info);
5055        tx_load(info, buf, count);
5056        spin_unlock_irqrestore(&info->lock, flags);
5057
5058        /* wait for receive complete */
5059        for (timeout = 100; timeout; --timeout) {
5060                msleep_interruptible(10);
5061                if (loopback_test_rx(info)) {
5062                        rc = 0;
5063                        break;
5064                }
5065        }
5066
5067        /* verify received frame length and contents */
5068        if (!rc && (info->tmp_rbuf_count != count ||
5069                  memcmp(buf, info->tmp_rbuf, count))) {
5070                rc = -ENODEV;
5071        }
5072
5073        spin_lock_irqsave(&info->lock,flags);
5074        reset_adapter(info);
5075        spin_unlock_irqrestore(&info->lock,flags);
5076
5077        memcpy(&info->params, &params, sizeof(info->params));
5078        info->port.tty = oldtty;
5079
5080        info->init_error = rc ? DiagStatus_DmaFailure : 0;
5081        return rc;
5082}
5083
5084static int adapter_test(struct slgt_info *info)
5085{
5086        DBGINFO(("testing %s\n", info->device_name));
5087        if (register_test(info) < 0) {
5088                printk("register test failure %s addr=%08X\n",
5089                        info->device_name, info->phys_reg_addr);
5090        } else if (irq_test(info) < 0) {
5091                printk("IRQ test failure %s IRQ=%d\n",
5092                        info->device_name, info->irq_level);
5093        } else if (loopback_test(info) < 0) {
5094                printk("loopback test failure %s\n", info->device_name);
5095        }
5096        return info->init_error;
5097}
5098
5099/*
5100 * transmit timeout handler
5101 */
5102static void tx_timeout(struct timer_list *t)
5103{
5104        struct slgt_info *info = from_timer(info, t, tx_timer);
5105        unsigned long flags;
5106
5107        DBGINFO(("%s tx_timeout\n", info->device_name));
5108        if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5109                info->icount.txtimeout++;
5110        }
5111        spin_lock_irqsave(&info->lock,flags);
5112        tx_stop(info);
5113        spin_unlock_irqrestore(&info->lock,flags);
5114
5115#if SYNCLINK_GENERIC_HDLC
5116        if (info->netcount)
5117                hdlcdev_tx_done(info);
5118        else
5119#endif
5120                bh_transmit(info);
5121}
5122
5123/*
5124 * receive buffer polling timer
5125 */
5126static void rx_timeout(struct timer_list *t)
5127{
5128        struct slgt_info *info = from_timer(info, t, rx_timer);
5129        unsigned long flags;
5130
5131        DBGINFO(("%s rx_timeout\n", info->device_name));
5132        spin_lock_irqsave(&info->lock, flags);
5133        info->pending_bh |= BH_RECEIVE;
5134        spin_unlock_irqrestore(&info->lock, flags);
5135        bh_handler(&info->task);
5136}
5137
5138