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10#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
11#define __DRIVERS_USB_CHIPIDEA_CI_H
12
13#include <linux/list.h>
14#include <linux/irqreturn.h>
15#include <linux/usb.h>
16#include <linux/usb/gadget.h>
17#include <linux/usb/otg-fsm.h>
18#include <linux/usb/otg.h>
19#include <linux/ulpi/interface.h>
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23
24#define TD_PAGE_COUNT 5
25#define CI_HDRC_PAGE_SIZE 4096ul
26#define ENDPT_MAX 32
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31
32#define ID_ID 0x0
33#define ID_HWGENERAL 0x4
34#define ID_HWHOST 0x8
35#define ID_HWDEVICE 0xc
36#define ID_HWTXBUF 0x10
37#define ID_HWRXBUF 0x14
38#define ID_SBUSCFG 0x90
39
40
41enum ci_hw_regs {
42 CAP_CAPLENGTH,
43 CAP_HCCPARAMS,
44 CAP_DCCPARAMS,
45 CAP_TESTMODE,
46 CAP_LAST = CAP_TESTMODE,
47 OP_USBCMD,
48 OP_USBSTS,
49 OP_USBINTR,
50 OP_DEVICEADDR,
51 OP_ENDPTLISTADDR,
52 OP_TTCTRL,
53 OP_BURSTSIZE,
54 OP_ULPI_VIEWPORT,
55 OP_PORTSC,
56 OP_DEVLC,
57 OP_OTGSC,
58 OP_USBMODE,
59 OP_ENDPTSETUPSTAT,
60 OP_ENDPTPRIME,
61 OP_ENDPTFLUSH,
62 OP_ENDPTSTAT,
63 OP_ENDPTCOMPLETE,
64 OP_ENDPTCTRL,
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66 OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
67};
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85struct ci_hw_ep {
86 struct usb_ep ep;
87 u8 dir;
88 u8 num;
89 u8 type;
90 char name[16];
91 struct {
92 struct list_head queue;
93 struct ci_hw_qh *ptr;
94 dma_addr_t dma;
95 } qh;
96 int wedge;
97
98
99 struct ci_hdrc *ci;
100 spinlock_t *lock;
101 struct dma_pool *td_pool;
102 struct td_node *pending_td;
103};
104
105enum ci_role {
106 CI_ROLE_HOST = 0,
107 CI_ROLE_GADGET,
108 CI_ROLE_END,
109};
110
111enum ci_revision {
112 CI_REVISION_1X = 10,
113 CI_REVISION_20 = 20,
114 CI_REVISION_21,
115 CI_REVISION_22,
116 CI_REVISION_23,
117 CI_REVISION_24,
118 CI_REVISION_25,
119 CI_REVISION_25_PLUS,
120 CI_REVISION_UNKNOWN = 99,
121};
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130struct ci_role_driver {
131 int (*start)(struct ci_hdrc *);
132 void (*stop)(struct ci_hdrc *);
133 irqreturn_t (*irq)(struct ci_hdrc *);
134 const char *name;
135};
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147struct hw_bank {
148 unsigned lpm;
149 resource_size_t phys;
150 void __iomem *abs;
151 void __iomem *cap;
152 void __iomem *op;
153 size_t size;
154 void __iomem *regmap[OP_LAST + 1];
155};
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206struct ci_hdrc {
207 struct device *dev;
208 spinlock_t lock;
209 struct hw_bank hw_bank;
210 int irq;
211 struct ci_role_driver *roles[CI_ROLE_END];
212 enum ci_role role;
213 bool is_otg;
214 struct usb_otg otg;
215 struct otg_fsm fsm;
216 struct hrtimer otg_fsm_hrtimer;
217 ktime_t hr_timeouts[NUM_OTG_FSM_TIMERS];
218 unsigned enabled_otg_timer_bits;
219 enum otg_fsm_timer next_otg_timer;
220 struct work_struct work;
221 struct workqueue_struct *wq;
222
223 struct dma_pool *qh_pool;
224 struct dma_pool *td_pool;
225
226 struct usb_gadget gadget;
227 struct usb_gadget_driver *driver;
228 enum usb_device_state resume_state;
229 unsigned hw_ep_max;
230 struct ci_hw_ep ci_hw_ep[ENDPT_MAX];
231 u32 ep0_dir;
232 struct ci_hw_ep *ep0out, *ep0in;
233
234 struct usb_request *status;
235 bool setaddr;
236 u8 address;
237 u8 remote_wakeup;
238 u8 suspended;
239 u8 test_mode;
240
241 struct ci_hdrc_platform_data *platdata;
242 int vbus_active;
243 struct ulpi *ulpi;
244 struct ulpi_ops ulpi_ops;
245 struct phy *phy;
246
247 struct usb_phy *usb_phy;
248 struct usb_hcd *hcd;
249 struct dentry *debugfs;
250 bool id_event;
251 bool b_sess_valid_event;
252 bool imx28_write_fix;
253 bool supports_runtime_pm;
254 bool in_lpm;
255 bool wakeup_int;
256 enum ci_revision rev;
257};
258
259static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
260{
261 BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
262 return ci->roles[ci->role];
263}
264
265static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
266{
267 int ret;
268
269 if (role >= CI_ROLE_END)
270 return -EINVAL;
271
272 if (!ci->roles[role])
273 return -ENXIO;
274
275 ret = ci->roles[role]->start(ci);
276 if (!ret)
277 ci->role = role;
278 return ret;
279}
280
281static inline void ci_role_stop(struct ci_hdrc *ci)
282{
283 enum ci_role role = ci->role;
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285 if (role == CI_ROLE_END)
286 return;
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288 ci->role = CI_ROLE_END;
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290 ci->roles[role]->stop(ci);
291}
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301static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
302{
303 return ioread32(ci->hw_bank.abs + offset) & mask;
304}
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313static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
314 u32 mask, u32 data)
315{
316 if (~mask)
317 data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
318 | (data & mask);
319
320 iowrite32(data, ci->hw_bank.abs + offset);
321}
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331static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
332{
333 return ioread32(ci->hw_bank.regmap[reg]) & mask;
334}
335
336#ifdef CONFIG_SOC_IMX28
337static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
338{
339 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
340}
341#else
342static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
343{
344}
345#endif
346
347static inline void __hw_write(struct ci_hdrc *ci, u32 val,
348 void __iomem *addr)
349{
350 if (ci->imx28_write_fix)
351 imx28_ci_writel(val, addr);
352 else
353 iowrite32(val, addr);
354}
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363static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
364 u32 mask, u32 data)
365{
366 if (~mask)
367 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
368 | (data & mask);
369
370 __hw_write(ci, data, ci->hw_bank.regmap[reg]);
371}
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381static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
382 u32 mask)
383{
384 u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
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386 __hw_write(ci, val, ci->hw_bank.regmap[reg]);
387 return val;
388}
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399static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
400 u32 mask, u32 data)
401{
402 u32 val = hw_read(ci, reg, ~0);
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404 hw_write(ci, reg, mask, data);
405 return (val & mask) >> __ffs(mask);
406}
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414static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
415{
416#ifdef CONFIG_USB_OTG_FSM
417 struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
418
419 return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
420 ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
421 otg_caps->hnp_support || otg_caps->adp_support);
422#else
423 return false;
424#endif
425}
426
427int ci_ulpi_init(struct ci_hdrc *ci);
428void ci_ulpi_exit(struct ci_hdrc *ci);
429int ci_ulpi_resume(struct ci_hdrc *ci);
430
431u32 hw_read_intr_enable(struct ci_hdrc *ci);
432
433u32 hw_read_intr_status(struct ci_hdrc *ci);
434
435int hw_device_reset(struct ci_hdrc *ci);
436
437int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
438
439u8 hw_port_test_get(struct ci_hdrc *ci);
440
441void hw_phymode_configure(struct ci_hdrc *ci);
442
443void ci_platform_configure(struct ci_hdrc *ci);
444
445void dbg_create_files(struct ci_hdrc *ci);
446
447void dbg_remove_files(struct ci_hdrc *ci);
448#endif
449