1/* 2 * MFD driver for twl4030 audio submodule 3 * 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 * 6 * Copyright: (C) 2009 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 */ 23 24#ifndef __TWL4030_CODEC_H__ 25#define __TWL4030_CODEC_H__ 26 27/* Codec registers */ 28#define TWL4030_REG_CODEC_MODE 0x01 29#define TWL4030_REG_OPTION 0x02 30#define TWL4030_REG_UNKNOWN 0x03 31#define TWL4030_REG_MICBIAS_CTL 0x04 32#define TWL4030_REG_ANAMICL 0x05 33#define TWL4030_REG_ANAMICR 0x06 34#define TWL4030_REG_AVADC_CTL 0x07 35#define TWL4030_REG_ADCMICSEL 0x08 36#define TWL4030_REG_DIGMIXING 0x09 37#define TWL4030_REG_ATXL1PGA 0x0A 38#define TWL4030_REG_ATXR1PGA 0x0B 39#define TWL4030_REG_AVTXL2PGA 0x0C 40#define TWL4030_REG_AVTXR2PGA 0x0D 41#define TWL4030_REG_AUDIO_IF 0x0E 42#define TWL4030_REG_VOICE_IF 0x0F 43#define TWL4030_REG_ARXR1PGA 0x10 44#define TWL4030_REG_ARXL1PGA 0x11 45#define TWL4030_REG_ARXR2PGA 0x12 46#define TWL4030_REG_ARXL2PGA 0x13 47#define TWL4030_REG_VRXPGA 0x14 48#define TWL4030_REG_VSTPGA 0x15 49#define TWL4030_REG_VRX2ARXPGA 0x16 50#define TWL4030_REG_AVDAC_CTL 0x17 51#define TWL4030_REG_ARX2VTXPGA 0x18 52#define TWL4030_REG_ARXL1_APGA_CTL 0x19 53#define TWL4030_REG_ARXR1_APGA_CTL 0x1A 54#define TWL4030_REG_ARXL2_APGA_CTL 0x1B 55#define TWL4030_REG_ARXR2_APGA_CTL 0x1C 56#define TWL4030_REG_ATX2ARXPGA 0x1D 57#define TWL4030_REG_BT_IF 0x1E 58#define TWL4030_REG_BTPGA 0x1F 59#define TWL4030_REG_BTSTPGA 0x20 60#define TWL4030_REG_EAR_CTL 0x21 61#define TWL4030_REG_HS_SEL 0x22 62#define TWL4030_REG_HS_GAIN_SET 0x23 63#define TWL4030_REG_HS_POPN_SET 0x24 64#define TWL4030_REG_PREDL_CTL 0x25 65#define TWL4030_REG_PREDR_CTL 0x26 66#define TWL4030_REG_PRECKL_CTL 0x27 67#define TWL4030_REG_PRECKR_CTL 0x28 68#define TWL4030_REG_HFL_CTL 0x29 69#define TWL4030_REG_HFR_CTL 0x2A 70#define TWL4030_REG_ALC_CTL 0x2B 71#define TWL4030_REG_ALC_SET1 0x2C 72#define TWL4030_REG_ALC_SET2 0x2D 73#define TWL4030_REG_BOOST_CTL 0x2E 74#define TWL4030_REG_SOFTVOL_CTL 0x2F 75#define TWL4030_REG_DTMF_FREQSEL 0x30 76#define TWL4030_REG_DTMF_TONEXT1H 0x31 77#define TWL4030_REG_DTMF_TONEXT1L 0x32 78#define TWL4030_REG_DTMF_TONEXT2H 0x33 79#define TWL4030_REG_DTMF_TONEXT2L 0x34 80#define TWL4030_REG_DTMF_TONOFF 0x35 81#define TWL4030_REG_DTMF_WANONOFF 0x36 82#define TWL4030_REG_I2S_RX_SCRAMBLE_H 0x37 83#define TWL4030_REG_I2S_RX_SCRAMBLE_M 0x38 84#define TWL4030_REG_I2S_RX_SCRAMBLE_L 0x39 85#define TWL4030_REG_APLL_CTL 0x3A 86#define TWL4030_REG_DTMF_CTL 0x3B 87#define TWL4030_REG_DTMF_PGA_CTL2 0x3C 88#define TWL4030_REG_DTMF_PGA_CTL1 0x3D 89#define TWL4030_REG_MISC_SET_1 0x3E 90#define TWL4030_REG_PCMBTMUX 0x3F 91#define TWL4030_REG_RX_PATH_SEL 0x43 92#define TWL4030_REG_VDL_APGA_CTL 0x44 93#define TWL4030_REG_VIBRA_CTL 0x45 94#define TWL4030_REG_VIBRA_SET 0x46 95#define TWL4030_REG_VIBRA_PWM_SET 0x47 96#define TWL4030_REG_ANAMIC_GAIN 0x48 97#define TWL4030_REG_MISC_SET_2 0x49 98 99/* Bitfield Definitions */ 100 101/* TWL4030_CODEC_MODE (0x01) Fields */ 102#define TWL4030_APLL_RATE 0xF0 103#define TWL4030_APLL_RATE_8000 0x00 104#define TWL4030_APLL_RATE_11025 0x10 105#define TWL4030_APLL_RATE_12000 0x20 106#define TWL4030_APLL_RATE_16000 0x40 107#define TWL4030_APLL_RATE_22050 0x50 108#define TWL4030_APLL_RATE_24000 0x60 109#define TWL4030_APLL_RATE_32000 0x80 110#define TWL4030_APLL_RATE_44100 0x90 111#define TWL4030_APLL_RATE_48000 0xA0 112#define TWL4030_APLL_RATE_96000 0xE0 113#define TWL4030_SEL_16K 0x08 114#define TWL4030_CODECPDZ 0x02 115#define TWL4030_OPT_MODE 0x01 116#define TWL4030_OPTION_1 (1 << 0) 117#define TWL4030_OPTION_2 (0 << 0) 118 119/* TWL4030_OPTION (0x02) Fields */ 120#define TWL4030_ATXL1_EN (1 << 0) 121#define TWL4030_ATXR1_EN (1 << 1) 122#define TWL4030_ATXL2_VTXL_EN (1 << 2) 123#define TWL4030_ATXR2_VTXR_EN (1 << 3) 124#define TWL4030_ARXL1_VRX_EN (1 << 4) 125#define TWL4030_ARXR1_EN (1 << 5) 126#define TWL4030_ARXL2_EN (1 << 6) 127#define TWL4030_ARXR2_EN (1 << 7) 128 129/* TWL4030_REG_MICBIAS_CTL (0x04) Fields */ 130#define TWL4030_MICBIAS2_CTL 0x40 131#define TWL4030_MICBIAS1_CTL 0x20 132#define TWL4030_HSMICBIAS_EN 0x04 133#define TWL4030_MICBIAS2_EN 0x02 134#define TWL4030_MICBIAS1_EN 0x01 135 136/* ANAMICL (0x05) Fields */ 137#define TWL4030_CNCL_OFFSET_START 0x80 138#define TWL4030_OFFSET_CNCL_SEL 0x60 139#define TWL4030_OFFSET_CNCL_SEL_ARX1 0x00 140#define TWL4030_OFFSET_CNCL_SEL_ARX2 0x20 141#define TWL4030_OFFSET_CNCL_SEL_VRX 0x40 142#define TWL4030_OFFSET_CNCL_SEL_ALL 0x60 143#define TWL4030_MICAMPL_EN 0x10 144#define TWL4030_CKMIC_EN 0x08 145#define TWL4030_AUXL_EN 0x04 146#define TWL4030_HSMIC_EN 0x02 147#define TWL4030_MAINMIC_EN 0x01 148 149/* ANAMICR (0x06) Fields */ 150#define TWL4030_MICAMPR_EN 0x10 151#define TWL4030_AUXR_EN 0x04 152#define TWL4030_SUBMIC_EN 0x01 153 154/* AVADC_CTL (0x07) Fields */ 155#define TWL4030_ADCL_EN 0x08 156#define TWL4030_AVADC_CLK_PRIORITY 0x04 157#define TWL4030_ADCR_EN 0x02 158 159/* TWL4030_REG_ADCMICSEL (0x08) Fields */ 160#define TWL4030_DIGMIC1_EN 0x08 161#define TWL4030_TX2IN_SEL 0x04 162#define TWL4030_DIGMIC0_EN 0x02 163#define TWL4030_TX1IN_SEL 0x01 164 165/* AUDIO_IF (0x0E) Fields */ 166#define TWL4030_AIF_SLAVE_EN 0x80 167#define TWL4030_DATA_WIDTH 0x60 168#define TWL4030_DATA_WIDTH_16S_16W 0x00 169#define TWL4030_DATA_WIDTH_32S_16W 0x40 170#define TWL4030_DATA_WIDTH_32S_24W 0x60 171#define TWL4030_AIF_FORMAT 0x18 172#define TWL4030_AIF_FORMAT_CODEC 0x00 173#define TWL4030_AIF_FORMAT_LEFT 0x08 174#define TWL4030_AIF_FORMAT_RIGHT 0x10 175#define TWL4030_AIF_FORMAT_TDM 0x18 176#define TWL4030_AIF_TRI_EN 0x04 177#define TWL4030_CLK256FS_EN 0x02 178#define TWL4030_AIF_EN 0x01 179 180/* VOICE_IF (0x0F) Fields */ 181#define TWL4030_VIF_SLAVE_EN 0x80 182#define TWL4030_VIF_DIN_EN 0x40 183#define TWL4030_VIF_DOUT_EN 0x20 184#define TWL4030_VIF_SWAP 0x10 185#define TWL4030_VIF_FORMAT 0x08 186#define TWL4030_VIF_TRI_EN 0x04 187#define TWL4030_VIF_SUB_EN 0x02 188#define TWL4030_VIF_EN 0x01 189 190/* EAR_CTL (0x21) */ 191#define TWL4030_EAR_GAIN 0x30 192 193/* HS_GAIN_SET (0x23) Fields */ 194#define TWL4030_HSR_GAIN 0x0C 195#define TWL4030_HSR_GAIN_PWR_DOWN 0x00 196#define TWL4030_HSR_GAIN_PLUS_6DB 0x04 197#define TWL4030_HSR_GAIN_0DB 0x08 198#define TWL4030_HSR_GAIN_MINUS_6DB 0x0C 199#define TWL4030_HSL_GAIN 0x03 200#define TWL4030_HSL_GAIN_PWR_DOWN 0x00 201#define TWL4030_HSL_GAIN_PLUS_6DB 0x01 202#define TWL4030_HSL_GAIN_0DB 0x02 203#define TWL4030_HSL_GAIN_MINUS_6DB 0x03 204 205/* HS_POPN_SET (0x24) Fields */ 206#define TWL4030_VMID_EN 0x40 207#define TWL4030_EXTMUTE 0x20 208#define TWL4030_RAMP_DELAY 0x1C 209#define TWL4030_RAMP_DELAY_20MS 0x00 210#define TWL4030_RAMP_DELAY_40MS 0x04 211#define TWL4030_RAMP_DELAY_81MS 0x08 212#define TWL4030_RAMP_DELAY_161MS 0x0C 213#define TWL4030_RAMP_DELAY_323MS 0x10 214#define TWL4030_RAMP_DELAY_645MS 0x14 215#define TWL4030_RAMP_DELAY_1291MS 0x18 216#define TWL4030_RAMP_DELAY_2581MS 0x1C 217#define TWL4030_RAMP_EN 0x02 218 219/* PREDL_CTL (0x25) */ 220#define TWL4030_PREDL_GAIN 0x30 221 222/* PREDR_CTL (0x26) */ 223#define TWL4030_PREDR_GAIN 0x30 224 225/* PRECKL_CTL (0x27) */ 226#define TWL4030_PRECKL_GAIN 0x30 227 228/* PRECKR_CTL (0x28) */ 229#define TWL4030_PRECKR_GAIN 0x30 230 231/* HFL_CTL (0x29, 0x2A) Fields */ 232#define TWL4030_HF_CTL_HB_EN 0x04 233#define TWL4030_HF_CTL_LOOP_EN 0x08 234#define TWL4030_HF_CTL_RAMP_EN 0x10 235#define TWL4030_HF_CTL_REF_EN 0x20 236 237/* APLL_CTL (0x3A) Fields */ 238#define TWL4030_APLL_EN 0x10 239#define TWL4030_APLL_INFREQ 0x0F 240#define TWL4030_APLL_INFREQ_19200KHZ 0x05 241#define TWL4030_APLL_INFREQ_26000KHZ 0x06 242#define TWL4030_APLL_INFREQ_38400KHZ 0x0F 243 244/* REG_MISC_SET_1 (0x3E) Fields */ 245#define TWL4030_CLK64_EN 0x80 246#define TWL4030_SCRAMBLE_EN 0x40 247#define TWL4030_FMLOOP_EN 0x20 248#define TWL4030_SMOOTH_ANAVOL_EN 0x02 249#define TWL4030_DIGMIC_LR_SWAP_EN 0x01 250 251/* VIBRA_CTL (0x45) */ 252#define TWL4030_VIBRA_EN 0x01 253#define TWL4030_VIBRA_DIR 0x02 254#define TWL4030_VIBRA_AUDIO_SEL_L1 (0x00 << 2) 255#define TWL4030_VIBRA_AUDIO_SEL_R1 (0x01 << 2) 256#define TWL4030_VIBRA_AUDIO_SEL_L2 (0x02 << 2) 257#define TWL4030_VIBRA_AUDIO_SEL_R2 (0x03 << 2) 258#define TWL4030_VIBRA_SEL 0x10 259#define TWL4030_VIBRA_DIR_SEL 0x20 260 261/* TWL4030 codec resource IDs */ 262enum twl4030_audio_res { 263 TWL4030_AUDIO_RES_POWER = 0, 264 TWL4030_AUDIO_RES_APLL, 265 TWL4030_AUDIO_RES_MAX, 266}; 267 268int twl4030_audio_disable_resource(enum twl4030_audio_res id); 269int twl4030_audio_enable_resource(enum twl4030_audio_res id); 270unsigned int twl4030_audio_get_mclk(void); 271 272#endif /* End of __TWL4030_CODEC_H__ */ 273