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12#include <linux/delay.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/dma-mapping.h>
17#include <linux/pm_runtime.h>
18#include <sound/soc.h>
19#include "mt8173-afe-common.h"
20#include "../common/mtk-base-afe.h"
21#include "../common/mtk-afe-platform-driver.h"
22#include "../common/mtk-afe-fe-dai.h"
23
24
25
26
27#define AUDIO_TOP_CON0 0x0000
28#define AUDIO_TOP_CON1 0x0004
29#define AFE_DAC_CON0 0x0010
30#define AFE_DAC_CON1 0x0014
31#define AFE_I2S_CON1 0x0034
32#define AFE_I2S_CON2 0x0038
33#define AFE_CONN_24BIT 0x006c
34#define AFE_MEMIF_MSB 0x00cc
35
36#define AFE_CONN1 0x0024
37#define AFE_CONN2 0x0028
38#define AFE_CONN3 0x002c
39#define AFE_CONN7 0x0460
40#define AFE_CONN8 0x0464
41#define AFE_HDMI_CONN0 0x0390
42
43
44#define AFE_DL1_BASE 0x0040
45#define AFE_DL1_CUR 0x0044
46#define AFE_DL1_END 0x0048
47#define AFE_DL2_BASE 0x0050
48#define AFE_DL2_CUR 0x0054
49#define AFE_AWB_BASE 0x0070
50#define AFE_AWB_CUR 0x007c
51#define AFE_VUL_BASE 0x0080
52#define AFE_VUL_CUR 0x008c
53#define AFE_VUL_END 0x0088
54#define AFE_DAI_BASE 0x0090
55#define AFE_DAI_CUR 0x009c
56#define AFE_MOD_PCM_BASE 0x0330
57#define AFE_MOD_PCM_CUR 0x033c
58#define AFE_HDMI_OUT_BASE 0x0374
59#define AFE_HDMI_OUT_CUR 0x0378
60#define AFE_HDMI_OUT_END 0x037c
61
62#define AFE_ADDA_TOP_CON0 0x0120
63#define AFE_ADDA2_TOP_CON0 0x0600
64
65#define AFE_HDMI_OUT_CON0 0x0370
66
67#define AFE_IRQ_MCU_CON 0x03a0
68#define AFE_IRQ_STATUS 0x03a4
69#define AFE_IRQ_CLR 0x03a8
70#define AFE_IRQ_CNT1 0x03ac
71#define AFE_IRQ_CNT2 0x03b0
72#define AFE_IRQ_MCU_EN 0x03b4
73#define AFE_IRQ_CNT5 0x03bc
74#define AFE_IRQ_CNT7 0x03dc
75
76#define AFE_TDM_CON1 0x0548
77#define AFE_TDM_CON2 0x054c
78
79#define AFE_IRQ_STATUS_BITS 0xff
80
81
82#define AUD_TCON0_PDN_SPDF (0x1 << 21)
83#define AUD_TCON0_PDN_HDMI (0x1 << 20)
84#define AUD_TCON0_PDN_24M (0x1 << 9)
85#define AUD_TCON0_PDN_22M (0x1 << 8)
86#define AUD_TCON0_PDN_AFE (0x1 << 2)
87
88
89#define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12)
90#define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8)
91#define AFE_I2S_CON1_FORMAT_I2S (0x1 << 3)
92#define AFE_I2S_CON1_EN (0x1 << 0)
93
94
95#define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12)
96#define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8)
97#define AFE_I2S_CON2_FORMAT_I2S (0x1 << 3)
98#define AFE_I2S_CON2_EN (0x1 << 0)
99
100
101#define AFE_CONN_24BIT_O04 (0x1 << 4)
102#define AFE_CONN_24BIT_O03 (0x1 << 3)
103
104
105#define AFE_HDMI_CONN0_O37_I37 (0x7 << 21)
106#define AFE_HDMI_CONN0_O36_I36 (0x6 << 18)
107#define AFE_HDMI_CONN0_O35_I33 (0x3 << 15)
108#define AFE_HDMI_CONN0_O34_I32 (0x2 << 12)
109#define AFE_HDMI_CONN0_O33_I35 (0x5 << 9)
110#define AFE_HDMI_CONN0_O32_I34 (0x4 << 6)
111#define AFE_HDMI_CONN0_O31_I31 (0x1 << 3)
112#define AFE_HDMI_CONN0_O30_I30 (0x0 << 0)
113
114
115#define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24)
116#define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12)
117#define AFE_TDM_CON1_WLEN_32BIT (0x2 << 8)
118#define AFE_TDM_CON1_MSB_ALIGNED (0x1 << 4)
119#define AFE_TDM_CON1_1_BCK_DELAY (0x1 << 3)
120#define AFE_TDM_CON1_LRCK_INV (0x1 << 2)
121#define AFE_TDM_CON1_BCK_INV (0x1 << 1)
122#define AFE_TDM_CON1_EN (0x1 << 0)
123
124enum afe_tdm_ch_start {
125 AFE_TDM_CH_START_O30_O31 = 0,
126 AFE_TDM_CH_START_O32_O33,
127 AFE_TDM_CH_START_O34_O35,
128 AFE_TDM_CH_START_O36_O37,
129 AFE_TDM_CH_ZERO,
130};
131
132static const unsigned int mt8173_afe_backup_list[] = {
133 AUDIO_TOP_CON0,
134 AFE_CONN1,
135 AFE_CONN2,
136 AFE_CONN7,
137 AFE_CONN8,
138 AFE_DAC_CON1,
139 AFE_DL1_BASE,
140 AFE_DL1_END,
141 AFE_VUL_BASE,
142 AFE_VUL_END,
143 AFE_HDMI_OUT_BASE,
144 AFE_HDMI_OUT_END,
145 AFE_HDMI_CONN0,
146 AFE_DAC_CON0,
147};
148
149struct mt8173_afe_private {
150 struct clk *clocks[MT8173_CLK_NUM];
151};
152
153static const struct snd_pcm_hardware mt8173_afe_hardware = {
154 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
155 SNDRV_PCM_INFO_MMAP_VALID),
156 .buffer_bytes_max = 256 * 1024,
157 .period_bytes_min = 512,
158 .period_bytes_max = 128 * 1024,
159 .periods_min = 2,
160 .periods_max = 256,
161 .fifo_size = 0,
162};
163
164struct mt8173_afe_rate {
165 unsigned int rate;
166 unsigned int regvalue;
167};
168
169static const struct mt8173_afe_rate mt8173_afe_i2s_rates[] = {
170 { .rate = 8000, .regvalue = 0 },
171 { .rate = 11025, .regvalue = 1 },
172 { .rate = 12000, .regvalue = 2 },
173 { .rate = 16000, .regvalue = 4 },
174 { .rate = 22050, .regvalue = 5 },
175 { .rate = 24000, .regvalue = 6 },
176 { .rate = 32000, .regvalue = 8 },
177 { .rate = 44100, .regvalue = 9 },
178 { .rate = 48000, .regvalue = 10 },
179 { .rate = 88000, .regvalue = 11 },
180 { .rate = 96000, .regvalue = 12 },
181 { .rate = 174000, .regvalue = 13 },
182 { .rate = 192000, .regvalue = 14 },
183};
184
185static int mt8173_afe_i2s_fs(unsigned int sample_rate)
186{
187 int i;
188
189 for (i = 0; i < ARRAY_SIZE(mt8173_afe_i2s_rates); i++)
190 if (mt8173_afe_i2s_rates[i].rate == sample_rate)
191 return mt8173_afe_i2s_rates[i].regvalue;
192
193 return -EINVAL;
194}
195
196static int mt8173_afe_set_i2s(struct mtk_base_afe *afe, unsigned int rate)
197{
198 unsigned int val;
199 int fs = mt8173_afe_i2s_fs(rate);
200
201 if (fs < 0)
202 return -EINVAL;
203
204
205 regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x1);
206 regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1);
207
208
209 val = AFE_I2S_CON2_LOW_JITTER_CLK |
210 AFE_I2S_CON2_RATE(fs) |
211 AFE_I2S_CON2_FORMAT_I2S;
212
213 regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val);
214
215
216 val = AFE_I2S_CON1_LOW_JITTER_CLK |
217 AFE_I2S_CON1_RATE(fs) |
218 AFE_I2S_CON1_FORMAT_I2S;
219
220 regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val);
221 return 0;
222}
223
224static void mt8173_afe_set_i2s_enable(struct mtk_base_afe *afe, bool enable)
225{
226 unsigned int val;
227
228 regmap_read(afe->regmap, AFE_I2S_CON2, &val);
229 if (!!(val & AFE_I2S_CON2_EN) == enable)
230 return;
231
232
233 regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable);
234
235
236 regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable);
237}
238
239static int mt8173_afe_dais_enable_clks(struct mtk_base_afe *afe,
240 struct clk *m_ck, struct clk *b_ck)
241{
242 int ret;
243
244 if (m_ck) {
245 ret = clk_prepare_enable(m_ck);
246 if (ret) {
247 dev_err(afe->dev, "Failed to enable m_ck\n");
248 return ret;
249 }
250 }
251
252 if (b_ck) {
253 ret = clk_prepare_enable(b_ck);
254 if (ret) {
255 dev_err(afe->dev, "Failed to enable b_ck\n");
256 return ret;
257 }
258 }
259 return 0;
260}
261
262static int mt8173_afe_dais_set_clks(struct mtk_base_afe *afe,
263 struct clk *m_ck, unsigned int mck_rate,
264 struct clk *b_ck, unsigned int bck_rate)
265{
266 int ret;
267
268 if (m_ck) {
269 ret = clk_set_rate(m_ck, mck_rate);
270 if (ret) {
271 dev_err(afe->dev, "Failed to set m_ck rate\n");
272 return ret;
273 }
274 }
275
276 if (b_ck) {
277 ret = clk_set_rate(b_ck, bck_rate);
278 if (ret) {
279 dev_err(afe->dev, "Failed to set b_ck rate\n");
280 return ret;
281 }
282 }
283 return 0;
284}
285
286static void mt8173_afe_dais_disable_clks(struct mtk_base_afe *afe,
287 struct clk *m_ck, struct clk *b_ck)
288{
289 if (m_ck)
290 clk_disable_unprepare(m_ck);
291 if (b_ck)
292 clk_disable_unprepare(b_ck);
293}
294
295static int mt8173_afe_i2s_startup(struct snd_pcm_substream *substream,
296 struct snd_soc_dai *dai)
297{
298 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
299
300 if (dai->active)
301 return 0;
302
303 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
304 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);
305 return 0;
306}
307
308static void mt8173_afe_i2s_shutdown(struct snd_pcm_substream *substream,
309 struct snd_soc_dai *dai)
310{
311 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
312
313 if (dai->active)
314 return;
315
316 mt8173_afe_set_i2s_enable(afe, false);
317 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
318 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,
319 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);
320}
321
322static int mt8173_afe_i2s_prepare(struct snd_pcm_substream *substream,
323 struct snd_soc_dai *dai)
324{
325 struct snd_pcm_runtime * const runtime = substream->runtime;
326 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
327 struct mt8173_afe_private *afe_priv = afe->platform_priv;
328 int ret;
329
330 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M],
331 runtime->rate * 256, NULL, 0);
332 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M],
333 runtime->rate * 256, NULL, 0);
334
335 ret = mt8173_afe_set_i2s(afe, substream->runtime->rate);
336 if (ret)
337 return ret;
338
339 mt8173_afe_set_i2s_enable(afe, true);
340
341 return 0;
342}
343
344static int mt8173_afe_hdmi_startup(struct snd_pcm_substream *substream,
345 struct snd_soc_dai *dai)
346{
347 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
348 struct mt8173_afe_private *afe_priv = afe->platform_priv;
349
350 if (dai->active)
351 return 0;
352
353 mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
354 afe_priv->clocks[MT8173_CLK_I2S3_B]);
355 return 0;
356}
357
358static void mt8173_afe_hdmi_shutdown(struct snd_pcm_substream *substream,
359 struct snd_soc_dai *dai)
360{
361 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
362 struct mt8173_afe_private *afe_priv = afe->platform_priv;
363
364 if (dai->active)
365 return;
366
367 mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
368 afe_priv->clocks[MT8173_CLK_I2S3_B]);
369}
370
371static int mt8173_afe_hdmi_prepare(struct snd_pcm_substream *substream,
372 struct snd_soc_dai *dai)
373{
374 struct snd_pcm_runtime * const runtime = substream->runtime;
375 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
376 struct mt8173_afe_private *afe_priv = afe->platform_priv;
377
378 unsigned int val;
379
380 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
381 runtime->rate * 128,
382 afe_priv->clocks[MT8173_CLK_I2S3_B],
383 runtime->rate * runtime->channels * 32);
384
385 val = AFE_TDM_CON1_BCK_INV |
386 AFE_TDM_CON1_LRCK_INV |
387 AFE_TDM_CON1_1_BCK_DELAY |
388 AFE_TDM_CON1_MSB_ALIGNED |
389 AFE_TDM_CON1_WLEN_32BIT |
390 AFE_TDM_CON1_32_BCK_CYCLES |
391 AFE_TDM_CON1_LRCK_WIDTH(32);
392 regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val);
393
394
395 switch (runtime->channels) {
396 case 1:
397 case 2:
398 val = AFE_TDM_CH_START_O30_O31;
399 val |= (AFE_TDM_CH_ZERO << 4);
400 val |= (AFE_TDM_CH_ZERO << 8);
401 val |= (AFE_TDM_CH_ZERO << 12);
402 break;
403 case 3:
404 case 4:
405 val = AFE_TDM_CH_START_O30_O31;
406 val |= (AFE_TDM_CH_START_O32_O33 << 4);
407 val |= (AFE_TDM_CH_ZERO << 8);
408 val |= (AFE_TDM_CH_ZERO << 12);
409 break;
410 case 5:
411 case 6:
412 val = AFE_TDM_CH_START_O30_O31;
413 val |= (AFE_TDM_CH_START_O32_O33 << 4);
414 val |= (AFE_TDM_CH_START_O34_O35 << 8);
415 val |= (AFE_TDM_CH_ZERO << 12);
416 break;
417 case 7:
418 case 8:
419 val = AFE_TDM_CH_START_O30_O31;
420 val |= (AFE_TDM_CH_START_O32_O33 << 4);
421 val |= (AFE_TDM_CH_START_O34_O35 << 8);
422 val |= (AFE_TDM_CH_START_O36_O37 << 12);
423 break;
424 default:
425 val = 0;
426 }
427 regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val);
428
429 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
430 0x000000f0, runtime->channels << 4);
431 return 0;
432}
433
434static int mt8173_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd,
435 struct snd_soc_dai *dai)
436{
437 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
438
439 dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name);
440
441 switch (cmd) {
442 case SNDRV_PCM_TRIGGER_START:
443 case SNDRV_PCM_TRIGGER_RESUME:
444 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
445 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0);
446
447
448 regmap_write(afe->regmap, AFE_HDMI_CONN0,
449 AFE_HDMI_CONN0_O30_I30 |
450 AFE_HDMI_CONN0_O31_I31 |
451 AFE_HDMI_CONN0_O32_I34 |
452 AFE_HDMI_CONN0_O33_I35 |
453 AFE_HDMI_CONN0_O34_I32 |
454 AFE_HDMI_CONN0_O35_I33 |
455 AFE_HDMI_CONN0_O36_I36 |
456 AFE_HDMI_CONN0_O37_I37);
457
458
459 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1);
460
461
462 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1);
463
464 return 0;
465 case SNDRV_PCM_TRIGGER_STOP:
466 case SNDRV_PCM_TRIGGER_SUSPEND:
467
468 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0);
469
470
471 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0);
472
473 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
474 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF,
475 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF);
476 return 0;
477 default:
478 return -EINVAL;
479 }
480}
481
482static int mt8173_memif_fs(struct snd_pcm_substream *substream,
483 unsigned int rate)
484{
485 struct snd_soc_pcm_runtime *rtd = substream->private_data;
486 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
487 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
488 struct mtk_base_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
489 int fs;
490
491 if (memif->data->id == MT8173_AFE_MEMIF_DAI ||
492 memif->data->id == MT8173_AFE_MEMIF_MOD_DAI) {
493 switch (rate) {
494 case 8000:
495 fs = 0;
496 break;
497 case 16000:
498 fs = 1;
499 break;
500 case 32000:
501 fs = 2;
502 break;
503 default:
504 return -EINVAL;
505 }
506 } else {
507 fs = mt8173_afe_i2s_fs(rate);
508 }
509 return fs;
510}
511
512static int mt8173_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
513{
514 return mt8173_afe_i2s_fs(rate);
515}
516
517
518static const struct snd_soc_dai_ops mt8173_afe_i2s_ops = {
519 .startup = mt8173_afe_i2s_startup,
520 .shutdown = mt8173_afe_i2s_shutdown,
521 .prepare = mt8173_afe_i2s_prepare,
522};
523
524static const struct snd_soc_dai_ops mt8173_afe_hdmi_ops = {
525 .startup = mt8173_afe_hdmi_startup,
526 .shutdown = mt8173_afe_hdmi_shutdown,
527 .prepare = mt8173_afe_hdmi_prepare,
528 .trigger = mt8173_afe_hdmi_trigger,
529};
530
531static struct snd_soc_dai_driver mt8173_afe_pcm_dais[] = {
532
533 {
534 .name = "DL1",
535 .id = MT8173_AFE_MEMIF_DL1,
536 .suspend = mtk_afe_dai_suspend,
537 .resume = mtk_afe_dai_resume,
538 .playback = {
539 .stream_name = "DL1",
540 .channels_min = 1,
541 .channels_max = 2,
542 .rates = SNDRV_PCM_RATE_8000_48000,
543 .formats = SNDRV_PCM_FMTBIT_S16_LE,
544 },
545 .ops = &mtk_afe_fe_ops,
546 }, {
547 .name = "VUL",
548 .id = MT8173_AFE_MEMIF_VUL,
549 .suspend = mtk_afe_dai_suspend,
550 .resume = mtk_afe_dai_resume,
551 .capture = {
552 .stream_name = "VUL",
553 .channels_min = 1,
554 .channels_max = 2,
555 .rates = SNDRV_PCM_RATE_8000_48000,
556 .formats = SNDRV_PCM_FMTBIT_S16_LE,
557 },
558 .ops = &mtk_afe_fe_ops,
559 }, {
560
561 .name = "I2S",
562 .id = MT8173_AFE_IO_I2S,
563 .playback = {
564 .stream_name = "I2S Playback",
565 .channels_min = 1,
566 .channels_max = 2,
567 .rates = SNDRV_PCM_RATE_8000_48000,
568 .formats = SNDRV_PCM_FMTBIT_S16_LE,
569 },
570 .capture = {
571 .stream_name = "I2S Capture",
572 .channels_min = 1,
573 .channels_max = 2,
574 .rates = SNDRV_PCM_RATE_8000_48000,
575 .formats = SNDRV_PCM_FMTBIT_S16_LE,
576 },
577 .ops = &mt8173_afe_i2s_ops,
578 .symmetric_rates = 1,
579 },
580};
581
582static struct snd_soc_dai_driver mt8173_afe_hdmi_dais[] = {
583
584 {
585 .name = "HDMI",
586 .id = MT8173_AFE_MEMIF_HDMI,
587 .suspend = mtk_afe_dai_suspend,
588 .resume = mtk_afe_dai_resume,
589 .playback = {
590 .stream_name = "HDMI",
591 .channels_min = 2,
592 .channels_max = 8,
593 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
594 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
595 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
596 SNDRV_PCM_RATE_192000,
597 .formats = SNDRV_PCM_FMTBIT_S16_LE,
598 },
599 .ops = &mtk_afe_fe_ops,
600 }, {
601
602 .name = "HDMIO",
603 .id = MT8173_AFE_IO_HDMI,
604 .playback = {
605 .stream_name = "HDMIO Playback",
606 .channels_min = 2,
607 .channels_max = 8,
608 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
609 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
610 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
611 SNDRV_PCM_RATE_192000,
612 .formats = SNDRV_PCM_FMTBIT_S16_LE,
613 },
614 .ops = &mt8173_afe_hdmi_ops,
615 },
616};
617
618static const struct snd_kcontrol_new mt8173_afe_o03_mix[] = {
619 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0),
620};
621
622static const struct snd_kcontrol_new mt8173_afe_o04_mix[] = {
623 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0),
624};
625
626static const struct snd_kcontrol_new mt8173_afe_o09_mix[] = {
627 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 0, 1, 0),
628 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0),
629};
630
631static const struct snd_kcontrol_new mt8173_afe_o10_mix[] = {
632 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN3, 3, 1, 0),
633 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0),
634};
635
636static const struct snd_soc_dapm_widget mt8173_afe_pcm_widgets[] = {
637
638 SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
639 SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0),
640 SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
641 SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
642 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
643 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
644
645 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
646 mt8173_afe_o03_mix, ARRAY_SIZE(mt8173_afe_o03_mix)),
647 SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
648 mt8173_afe_o04_mix, ARRAY_SIZE(mt8173_afe_o04_mix)),
649 SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
650 mt8173_afe_o09_mix, ARRAY_SIZE(mt8173_afe_o09_mix)),
651 SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
652 mt8173_afe_o10_mix, ARRAY_SIZE(mt8173_afe_o10_mix)),
653};
654
655static const struct snd_soc_dapm_route mt8173_afe_pcm_routes[] = {
656 {"I05", NULL, "DL1"},
657 {"I06", NULL, "DL1"},
658 {"I2S Playback", NULL, "O03"},
659 {"I2S Playback", NULL, "O04"},
660 {"VUL", NULL, "O09"},
661 {"VUL", NULL, "O10"},
662 {"I03", NULL, "I2S Capture"},
663 {"I04", NULL, "I2S Capture"},
664 {"I17", NULL, "I2S Capture"},
665 {"I18", NULL, "I2S Capture"},
666 { "O03", "I05 Switch", "I05" },
667 { "O04", "I06 Switch", "I06" },
668 { "O09", "I17 Switch", "I17" },
669 { "O09", "I03 Switch", "I03" },
670 { "O10", "I18 Switch", "I18" },
671 { "O10", "I04 Switch", "I04" },
672};
673
674static const struct snd_soc_dapm_route mt8173_afe_hdmi_routes[] = {
675 {"HDMIO Playback", NULL, "HDMI"},
676};
677
678static const struct snd_soc_component_driver mt8173_afe_pcm_dai_component = {
679 .name = "mt8173-afe-pcm-dai",
680 .dapm_widgets = mt8173_afe_pcm_widgets,
681 .num_dapm_widgets = ARRAY_SIZE(mt8173_afe_pcm_widgets),
682 .dapm_routes = mt8173_afe_pcm_routes,
683 .num_dapm_routes = ARRAY_SIZE(mt8173_afe_pcm_routes),
684};
685
686static const struct snd_soc_component_driver mt8173_afe_hdmi_dai_component = {
687 .name = "mt8173-afe-hdmi-dai",
688 .dapm_routes = mt8173_afe_hdmi_routes,
689 .num_dapm_routes = ARRAY_SIZE(mt8173_afe_hdmi_routes),
690};
691
692static const char *aud_clks[MT8173_CLK_NUM] = {
693 [MT8173_CLK_INFRASYS_AUD] = "infra_sys_audio_clk",
694 [MT8173_CLK_TOP_PDN_AUD] = "top_pdn_audio",
695 [MT8173_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus",
696 [MT8173_CLK_I2S0_M] = "i2s0_m",
697 [MT8173_CLK_I2S1_M] = "i2s1_m",
698 [MT8173_CLK_I2S2_M] = "i2s2_m",
699 [MT8173_CLK_I2S3_M] = "i2s3_m",
700 [MT8173_CLK_I2S3_B] = "i2s3_b",
701 [MT8173_CLK_BCK0] = "bck0",
702 [MT8173_CLK_BCK1] = "bck1",
703};
704
705static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = {
706 {
707 .name = "DL1",
708 .id = MT8173_AFE_MEMIF_DL1,
709 .reg_ofs_base = AFE_DL1_BASE,
710 .reg_ofs_cur = AFE_DL1_CUR,
711 .fs_reg = AFE_DAC_CON1,
712 .fs_shift = 0,
713 .fs_maskbit = 0xf,
714 .mono_reg = AFE_DAC_CON1,
715 .mono_shift = 21,
716 .hd_reg = -1,
717 .hd_shift = -1,
718 .enable_reg = AFE_DAC_CON0,
719 .enable_shift = 1,
720 .msb_reg = AFE_MEMIF_MSB,
721 .msb_shift = 0,
722 .agent_disable_reg = -1,
723 .agent_disable_shift = -1,
724 }, {
725 .name = "DL2",
726 .id = MT8173_AFE_MEMIF_DL2,
727 .reg_ofs_base = AFE_DL2_BASE,
728 .reg_ofs_cur = AFE_DL2_CUR,
729 .fs_reg = AFE_DAC_CON1,
730 .fs_shift = 4,
731 .fs_maskbit = 0xf,
732 .mono_reg = AFE_DAC_CON1,
733 .mono_shift = 22,
734 .hd_reg = -1,
735 .hd_shift = -1,
736 .enable_reg = AFE_DAC_CON0,
737 .enable_shift = 2,
738 .msb_reg = AFE_MEMIF_MSB,
739 .msb_shift = 1,
740 .agent_disable_reg = -1,
741 .agent_disable_shift = -1,
742 }, {
743 .name = "VUL",
744 .id = MT8173_AFE_MEMIF_VUL,
745 .reg_ofs_base = AFE_VUL_BASE,
746 .reg_ofs_cur = AFE_VUL_CUR,
747 .fs_reg = AFE_DAC_CON1,
748 .fs_shift = 16,
749 .fs_maskbit = 0xf,
750 .mono_reg = AFE_DAC_CON1,
751 .mono_shift = 27,
752 .hd_reg = -1,
753 .hd_shift = -1,
754 .enable_reg = AFE_DAC_CON0,
755 .enable_shift = 3,
756 .msb_reg = AFE_MEMIF_MSB,
757 .msb_shift = 6,
758 .agent_disable_reg = -1,
759 .agent_disable_shift = -1,
760 }, {
761 .name = "DAI",
762 .id = MT8173_AFE_MEMIF_DAI,
763 .reg_ofs_base = AFE_DAI_BASE,
764 .reg_ofs_cur = AFE_DAI_CUR,
765 .fs_reg = AFE_DAC_CON0,
766 .fs_shift = 24,
767 .fs_maskbit = 0x3,
768 .mono_reg = -1,
769 .mono_shift = -1,
770 .hd_reg = -1,
771 .hd_shift = -1,
772 .enable_reg = AFE_DAC_CON0,
773 .enable_shift = 4,
774 .msb_reg = AFE_MEMIF_MSB,
775 .msb_shift = 5,
776 .agent_disable_reg = -1,
777 .agent_disable_shift = -1,
778 }, {
779 .name = "AWB",
780 .id = MT8173_AFE_MEMIF_AWB,
781 .reg_ofs_base = AFE_AWB_BASE,
782 .reg_ofs_cur = AFE_AWB_CUR,
783 .fs_reg = AFE_DAC_CON1,
784 .fs_shift = 12,
785 .fs_maskbit = 0xf,
786 .mono_reg = AFE_DAC_CON1,
787 .mono_shift = 24,
788 .hd_reg = -1,
789 .hd_shift = -1,
790 .enable_reg = AFE_DAC_CON0,
791 .enable_shift = 6,
792 .msb_reg = AFE_MEMIF_MSB,
793 .msb_shift = 3,
794 .agent_disable_reg = -1,
795 .agent_disable_shift = -1,
796 }, {
797 .name = "MOD_DAI",
798 .id = MT8173_AFE_MEMIF_MOD_DAI,
799 .reg_ofs_base = AFE_MOD_PCM_BASE,
800 .reg_ofs_cur = AFE_MOD_PCM_CUR,
801 .fs_reg = AFE_DAC_CON1,
802 .fs_shift = 30,
803 .fs_maskbit = 0x3,
804 .mono_reg = AFE_DAC_CON1,
805 .mono_shift = 30,
806 .hd_reg = -1,
807 .hd_shift = -1,
808 .enable_reg = AFE_DAC_CON0,
809 .enable_shift = 7,
810 .msb_reg = AFE_MEMIF_MSB,
811 .msb_shift = 4,
812 .agent_disable_reg = -1,
813 .agent_disable_shift = -1,
814 }, {
815 .name = "HDMI",
816 .id = MT8173_AFE_MEMIF_HDMI,
817 .reg_ofs_base = AFE_HDMI_OUT_BASE,
818 .reg_ofs_cur = AFE_HDMI_OUT_CUR,
819 .fs_reg = -1,
820 .fs_shift = -1,
821 .fs_maskbit = -1,
822 .mono_reg = -1,
823 .mono_shift = -1,
824 .hd_reg = -1,
825 .hd_shift = -1,
826 .enable_reg = -1,
827 .enable_shift = -1,
828 .msb_reg = AFE_MEMIF_MSB,
829 .msb_shift = 8,
830 .agent_disable_reg = -1,
831 .agent_disable_shift = -1,
832 },
833};
834
835static const struct mtk_base_irq_data irq_data[MT8173_AFE_IRQ_NUM] = {
836 {
837 .id = MT8173_AFE_IRQ_DL1,
838 .irq_cnt_reg = AFE_IRQ_CNT1,
839 .irq_cnt_shift = 0,
840 .irq_cnt_maskbit = 0x3ffff,
841 .irq_en_reg = AFE_IRQ_MCU_CON,
842 .irq_en_shift = 0,
843 .irq_fs_reg = AFE_IRQ_MCU_CON,
844 .irq_fs_shift = 4,
845 .irq_fs_maskbit = 0xf,
846 .irq_clr_reg = AFE_IRQ_CLR,
847 .irq_clr_shift = 0,
848 }, {
849 .id = MT8173_AFE_IRQ_DL2,
850 .irq_cnt_reg = AFE_IRQ_CNT1,
851 .irq_cnt_shift = 20,
852 .irq_cnt_maskbit = 0x3ffff,
853 .irq_en_reg = AFE_IRQ_MCU_CON,
854 .irq_en_shift = 2,
855 .irq_fs_reg = AFE_IRQ_MCU_CON,
856 .irq_fs_shift = 16,
857 .irq_fs_maskbit = 0xf,
858 .irq_clr_reg = AFE_IRQ_CLR,
859 .irq_clr_shift = 2,
860
861 }, {
862 .id = MT8173_AFE_IRQ_VUL,
863 .irq_cnt_reg = AFE_IRQ_CNT2,
864 .irq_cnt_shift = 0,
865 .irq_cnt_maskbit = 0x3ffff,
866 .irq_en_reg = AFE_IRQ_MCU_CON,
867 .irq_en_shift = 1,
868 .irq_fs_reg = AFE_IRQ_MCU_CON,
869 .irq_fs_shift = 8,
870 .irq_fs_maskbit = 0xf,
871 .irq_clr_reg = AFE_IRQ_CLR,
872 .irq_clr_shift = 1,
873 }, {
874 .id = MT8173_AFE_IRQ_DAI,
875 .irq_cnt_reg = AFE_IRQ_CNT2,
876 .irq_cnt_shift = 20,
877 .irq_cnt_maskbit = 0x3ffff,
878 .irq_en_reg = AFE_IRQ_MCU_CON,
879 .irq_en_shift = 3,
880 .irq_fs_reg = AFE_IRQ_MCU_CON,
881 .irq_fs_shift = 20,
882 .irq_fs_maskbit = 0xf,
883 .irq_clr_reg = AFE_IRQ_CLR,
884 .irq_clr_shift = 3,
885 }, {
886 .id = MT8173_AFE_IRQ_AWB,
887 .irq_cnt_reg = AFE_IRQ_CNT7,
888 .irq_cnt_shift = 0,
889 .irq_cnt_maskbit = 0x3ffff,
890 .irq_en_reg = AFE_IRQ_MCU_CON,
891 .irq_en_shift = 14,
892 .irq_fs_reg = AFE_IRQ_MCU_CON,
893 .irq_fs_shift = 24,
894 .irq_fs_maskbit = 0xf,
895 .irq_clr_reg = AFE_IRQ_CLR,
896 .irq_clr_shift = 6,
897 }, {
898 .id = MT8173_AFE_IRQ_DAI,
899 .irq_cnt_reg = AFE_IRQ_CNT2,
900 .irq_cnt_shift = 20,
901 .irq_cnt_maskbit = 0x3ffff,
902 .irq_en_reg = AFE_IRQ_MCU_CON,
903 .irq_en_shift = 3,
904 .irq_fs_reg = AFE_IRQ_MCU_CON,
905 .irq_fs_shift = 20,
906 .irq_fs_maskbit = 0xf,
907 .irq_clr_reg = AFE_IRQ_CLR,
908 .irq_clr_shift = 3,
909 }, {
910 .id = MT8173_AFE_IRQ_HDMI,
911 .irq_cnt_reg = AFE_IRQ_CNT5,
912 .irq_cnt_shift = 0,
913 .irq_cnt_maskbit = 0x3ffff,
914 .irq_en_reg = AFE_IRQ_MCU_CON,
915 .irq_en_shift = 12,
916 .irq_fs_reg = -1,
917 .irq_fs_shift = -1,
918 .irq_fs_maskbit = -1,
919 .irq_clr_reg = AFE_IRQ_CLR,
920 .irq_clr_shift = 4,
921 },
922};
923
924static const struct regmap_config mt8173_afe_regmap_config = {
925 .reg_bits = 32,
926 .reg_stride = 4,
927 .val_bits = 32,
928 .max_register = AFE_ADDA2_TOP_CON0,
929 .cache_type = REGCACHE_NONE,
930};
931
932static irqreturn_t mt8173_afe_irq_handler(int irq, void *dev_id)
933{
934 struct mtk_base_afe *afe = dev_id;
935 unsigned int reg_value;
936 int i, ret;
937
938 ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, ®_value);
939 if (ret) {
940 dev_err(afe->dev, "%s irq status err\n", __func__);
941 reg_value = AFE_IRQ_STATUS_BITS;
942 goto err_irq;
943 }
944
945 for (i = 0; i < MT8173_AFE_MEMIF_NUM; i++) {
946 struct mtk_base_afe_memif *memif = &afe->memif[i];
947 struct mtk_base_afe_irq *irq;
948
949 if (memif->irq_usage < 0)
950 continue;
951
952 irq = &afe->irqs[memif->irq_usage];
953
954 if (!(reg_value & (1 << irq->irq_data->irq_clr_shift)))
955 continue;
956
957 snd_pcm_period_elapsed(memif->substream);
958 }
959
960err_irq:
961
962 regmap_write(afe->regmap, AFE_IRQ_CLR,
963 reg_value & AFE_IRQ_STATUS_BITS);
964
965 return IRQ_HANDLED;
966}
967
968static int mt8173_afe_runtime_suspend(struct device *dev)
969{
970 struct mtk_base_afe *afe = dev_get_drvdata(dev);
971 struct mt8173_afe_private *afe_priv = afe->platform_priv;
972
973
974 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0);
975
976
977 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
978 AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE);
979
980 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
981 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
982 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
983 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK1]);
984 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
985 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
986 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
987 return 0;
988}
989
990static int mt8173_afe_runtime_resume(struct device *dev)
991{
992 struct mtk_base_afe *afe = dev_get_drvdata(dev);
993 struct mt8173_afe_private *afe_priv = afe->platform_priv;
994 int ret;
995
996 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
997 if (ret)
998 return ret;
999
1000 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
1001 if (ret)
1002 goto err_infra;
1003
1004 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
1005 if (ret)
1006 goto err_top_aud_bus;
1007
1008 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK0]);
1009 if (ret)
1010 goto err_top_aud;
1011
1012 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK1]);
1013 if (ret)
1014 goto err_bck0;
1015 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S1_M]);
1016 if (ret)
1017 goto err_i2s1_m;
1018 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S2_M]);
1019 if (ret)
1020 goto err_i2s2_m;
1021
1022
1023 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0);
1024
1025
1026 regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
1027 AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0);
1028
1029
1030 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff);
1031
1032
1033 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
1034 return 0;
1035
1036err_i2s1_m:
1037 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
1038err_i2s2_m:
1039 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
1040err_bck0:
1041 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
1042err_top_aud:
1043 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
1044err_top_aud_bus:
1045 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
1046err_infra:
1047 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
1048 return ret;
1049}
1050
1051static int mt8173_afe_init_audio_clk(struct mtk_base_afe *afe)
1052{
1053 size_t i;
1054 struct mt8173_afe_private *afe_priv = afe->platform_priv;
1055
1056 for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
1057 afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
1058 if (IS_ERR(afe_priv->clocks[i])) {
1059 dev_err(afe->dev, "%s devm_clk_get %s fail\n",
1060 __func__, aud_clks[i]);
1061 return PTR_ERR(afe_priv->clocks[i]);
1062 }
1063 }
1064 clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK0], 22579200);
1065 clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK1], 24576000);
1066 return 0;
1067}
1068
1069static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev)
1070{
1071 int ret, i;
1072 int irq_id;
1073 struct mtk_base_afe *afe;
1074 struct mt8173_afe_private *afe_priv;
1075 struct resource *res;
1076
1077 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));
1078 if (ret)
1079 return ret;
1080
1081 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1082 if (!afe)
1083 return -ENOMEM;
1084
1085 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1086 GFP_KERNEL);
1087 afe_priv = afe->platform_priv;
1088 if (!afe_priv)
1089 return -ENOMEM;
1090
1091 afe->dev = &pdev->dev;
1092
1093 irq_id = platform_get_irq(pdev, 0);
1094 if (irq_id <= 0) {
1095 dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name);
1096 return irq_id < 0 ? irq_id : -ENXIO;
1097 }
1098 ret = devm_request_irq(afe->dev, irq_id, mt8173_afe_irq_handler,
1099 0, "Afe_ISR_Handle", (void *)afe);
1100 if (ret) {
1101 dev_err(afe->dev, "could not request_irq\n");
1102 return ret;
1103 }
1104
1105 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1106 afe->base_addr = devm_ioremap_resource(&pdev->dev, res);
1107 if (IS_ERR(afe->base_addr))
1108 return PTR_ERR(afe->base_addr);
1109
1110 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
1111 &mt8173_afe_regmap_config);
1112 if (IS_ERR(afe->regmap))
1113 return PTR_ERR(afe->regmap);
1114
1115
1116 ret = mt8173_afe_init_audio_clk(afe);
1117 if (ret) {
1118 dev_err(afe->dev, "mt8173_afe_init_audio_clk fail\n");
1119 return ret;
1120 }
1121
1122
1123 afe->memif_size = MT8173_AFE_MEMIF_NUM;
1124 afe->memif = devm_kcalloc(afe->dev, afe->memif_size,
1125 sizeof(*afe->memif), GFP_KERNEL);
1126 if (!afe->memif)
1127 return -ENOMEM;
1128
1129 afe->irqs_size = MT8173_AFE_IRQ_NUM;
1130 afe->irqs = devm_kcalloc(afe->dev, afe->irqs_size,
1131 sizeof(*afe->irqs), GFP_KERNEL);
1132 if (!afe->irqs)
1133 return -ENOMEM;
1134
1135 for (i = 0; i < afe->irqs_size; i++) {
1136 afe->memif[i].data = &memif_data[i];
1137 afe->irqs[i].irq_data = &irq_data[i];
1138 afe->irqs[i].irq_occupyed = true;
1139 afe->memif[i].irq_usage = i;
1140 afe->memif[i].const_irq = 1;
1141 }
1142
1143 afe->mtk_afe_hardware = &mt8173_afe_hardware;
1144 afe->memif_fs = mt8173_memif_fs;
1145 afe->irq_fs = mt8173_irq_fs;
1146
1147 platform_set_drvdata(pdev, afe);
1148
1149 pm_runtime_enable(&pdev->dev);
1150 if (!pm_runtime_enabled(&pdev->dev)) {
1151 ret = mt8173_afe_runtime_resume(&pdev->dev);
1152 if (ret)
1153 goto err_pm_disable;
1154 }
1155
1156 afe->reg_back_up_list = mt8173_afe_backup_list;
1157 afe->reg_back_up_list_num = ARRAY_SIZE(mt8173_afe_backup_list);
1158 afe->runtime_resume = mt8173_afe_runtime_resume;
1159 afe->runtime_suspend = mt8173_afe_runtime_suspend;
1160
1161 ret = devm_snd_soc_register_component(&pdev->dev,
1162 &mtk_afe_pcm_platform,
1163 NULL, 0);
1164 if (ret)
1165 goto err_pm_disable;
1166
1167 ret = devm_snd_soc_register_component(&pdev->dev,
1168 &mt8173_afe_pcm_dai_component,
1169 mt8173_afe_pcm_dais,
1170 ARRAY_SIZE(mt8173_afe_pcm_dais));
1171 if (ret)
1172 goto err_pm_disable;
1173
1174 ret = devm_snd_soc_register_component(&pdev->dev,
1175 &mt8173_afe_hdmi_dai_component,
1176 mt8173_afe_hdmi_dais,
1177 ARRAY_SIZE(mt8173_afe_hdmi_dais));
1178 if (ret)
1179 goto err_pm_disable;
1180
1181 dev_info(&pdev->dev, "MT8173 AFE driver initialized.\n");
1182 return 0;
1183
1184err_pm_disable:
1185 pm_runtime_disable(&pdev->dev);
1186 return ret;
1187}
1188
1189static int mt8173_afe_pcm_dev_remove(struct platform_device *pdev)
1190{
1191 pm_runtime_disable(&pdev->dev);
1192 if (!pm_runtime_status_suspended(&pdev->dev))
1193 mt8173_afe_runtime_suspend(&pdev->dev);
1194 return 0;
1195}
1196
1197static const struct of_device_id mt8173_afe_pcm_dt_match[] = {
1198 { .compatible = "mediatek,mt8173-afe-pcm", },
1199 { }
1200};
1201MODULE_DEVICE_TABLE(of, mt8173_afe_pcm_dt_match);
1202
1203static const struct dev_pm_ops mt8173_afe_pm_ops = {
1204 SET_RUNTIME_PM_OPS(mt8173_afe_runtime_suspend,
1205 mt8173_afe_runtime_resume, NULL)
1206};
1207
1208static struct platform_driver mt8173_afe_pcm_driver = {
1209 .driver = {
1210 .name = "mt8173-afe-pcm",
1211 .of_match_table = mt8173_afe_pcm_dt_match,
1212 .pm = &mt8173_afe_pm_ops,
1213 },
1214 .probe = mt8173_afe_pcm_dev_probe,
1215 .remove = mt8173_afe_pcm_dev_remove,
1216};
1217
1218module_platform_driver(mt8173_afe_pcm_driver);
1219
1220MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver");
1221MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>");
1222MODULE_LICENSE("GPL v2");
1223
