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19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/platform_device.h>
24#include <linux/slab.h>
25#include <linux/dma-mapping.h>
26#include <linux/clk.h>
27#include <linux/clk-provider.h>
28#include <linux/delay.h>
29#include <linux/time.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34
35#include "mxs-saif.h"
36
37#define MXS_SET_ADDR 0x4
38#define MXS_CLR_ADDR 0x8
39
40static struct mxs_saif *mxs_saif[2];
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
61 int clk_id, unsigned int freq, int dir)
62{
63 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
64
65 switch (clk_id) {
66 case MXS_SAIF_MCLK:
67 saif->mclk = freq;
68 break;
69 default:
70 return -EINVAL;
71 }
72 return 0;
73}
74
75
76
77
78
79
80
81static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
82{
83 return mxs_saif[saif->master_id];
84}
85
86
87
88
89static int mxs_saif_set_clk(struct mxs_saif *saif,
90 unsigned int mclk,
91 unsigned int rate)
92{
93 u32 scr;
94 int ret;
95 struct mxs_saif *master_saif;
96
97 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
98
99
100 master_saif = mxs_saif_get_master(saif);
101 if (!master_saif)
102 return -EINVAL;
103
104 dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
105
106
107 if (master_saif->ongoing && rate != master_saif->cur_rate) {
108 dev_err(saif->dev,
109 "can not change clock, master saif%d(rate %d) is ongoing\n",
110 master_saif->id, master_saif->cur_rate);
111 return -EINVAL;
112 }
113
114 scr = __raw_readl(master_saif->base + SAIF_CTRL);
115 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
116 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
117
118
119
120
121
122
123
124
125
126
127
128 ret = clk_prepare_enable(master_saif->clk);
129 if (ret)
130 return ret;
131
132 if (master_saif->mclk_in_use) {
133 switch (mclk / rate) {
134 case 32:
135 case 64:
136 case 128:
137 case 256:
138 case 512:
139 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
140 ret = clk_set_rate(master_saif->clk, 512 * rate);
141 break;
142 case 48:
143 case 96:
144 case 192:
145 case 384:
146 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
147 ret = clk_set_rate(master_saif->clk, 384 * rate);
148 break;
149 default:
150
151 clk_disable_unprepare(master_saif->clk);
152 return -EINVAL;
153 }
154 } else {
155 ret = clk_set_rate(master_saif->clk, 512 * rate);
156 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
157 }
158
159 clk_disable_unprepare(master_saif->clk);
160
161 if (ret)
162 return ret;
163
164 master_saif->cur_rate = rate;
165
166 if (!master_saif->mclk_in_use) {
167 __raw_writel(scr, master_saif->base + SAIF_CTRL);
168 return 0;
169 }
170
171
172
173
174
175
176
177 switch (mclk / rate) {
178 case 32:
179 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
180 break;
181 case 64:
182 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
183 break;
184 case 128:
185 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
186 break;
187 case 256:
188 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
189 break;
190 case 512:
191 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
192 break;
193 case 48:
194 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
195 break;
196 case 96:
197 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
198 break;
199 case 192:
200 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
201 break;
202 case 384:
203 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
204 break;
205 default:
206 return -EINVAL;
207 }
208
209 __raw_writel(scr, master_saif->base + SAIF_CTRL);
210
211 return 0;
212}
213
214
215
216
217int mxs_saif_put_mclk(unsigned int saif_id)
218{
219 struct mxs_saif *saif = mxs_saif[saif_id];
220 u32 stat;
221
222 if (!saif)
223 return -EINVAL;
224
225 stat = __raw_readl(saif->base + SAIF_STAT);
226 if (stat & BM_SAIF_STAT_BUSY) {
227 dev_err(saif->dev, "error: busy\n");
228 return -EBUSY;
229 }
230
231 clk_disable_unprepare(saif->clk);
232
233
234 __raw_writel(BM_SAIF_CTRL_CLKGATE,
235 saif->base + SAIF_CTRL + MXS_SET_ADDR);
236 __raw_writel(BM_SAIF_CTRL_RUN,
237 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
238
239 saif->mclk_in_use = 0;
240 return 0;
241}
242EXPORT_SYMBOL_GPL(mxs_saif_put_mclk);
243
244
245
246
247
248
249
250int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
251 unsigned int rate)
252{
253 struct mxs_saif *saif = mxs_saif[saif_id];
254 u32 stat;
255 int ret;
256 struct mxs_saif *master_saif;
257
258 if (!saif)
259 return -EINVAL;
260
261
262 __raw_writel(BM_SAIF_CTRL_SFTRST,
263 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
264
265
266 __raw_writel(BM_SAIF_CTRL_CLKGATE,
267 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
268
269 master_saif = mxs_saif_get_master(saif);
270 if (saif != master_saif) {
271 dev_err(saif->dev, "can not get mclk from a non-master saif\n");
272 return -EINVAL;
273 }
274
275 stat = __raw_readl(saif->base + SAIF_STAT);
276 if (stat & BM_SAIF_STAT_BUSY) {
277 dev_err(saif->dev, "error: busy\n");
278 return -EBUSY;
279 }
280
281 saif->mclk_in_use = 1;
282 ret = mxs_saif_set_clk(saif, mclk, rate);
283 if (ret)
284 return ret;
285
286 ret = clk_prepare_enable(saif->clk);
287 if (ret)
288 return ret;
289
290
291 __raw_writel(BM_SAIF_CTRL_RUN,
292 saif->base + SAIF_CTRL + MXS_SET_ADDR);
293
294 return 0;
295}
296EXPORT_SYMBOL_GPL(mxs_saif_get_mclk);
297
298
299
300
301
302static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
303{
304 u32 scr, stat;
305 u32 scr0;
306 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
307
308 stat = __raw_readl(saif->base + SAIF_STAT);
309 if (stat & BM_SAIF_STAT_BUSY) {
310 dev_err(cpu_dai->dev, "error: busy\n");
311 return -EBUSY;
312 }
313
314
315
316
317 if (saif->id != saif->master_id) {
318 __raw_writel(BM_SAIF_CTRL_SFTRST,
319 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
320 __raw_writel(BM_SAIF_CTRL_CLKGATE,
321 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
322 }
323
324 scr0 = __raw_readl(saif->base + SAIF_CTRL);
325 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
326 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
327 scr = 0;
328
329
330 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
331 case SND_SOC_DAIFMT_I2S:
332
333 scr |= BM_SAIF_CTRL_DELAY;
334 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
335 break;
336 case SND_SOC_DAIFMT_LEFT_J:
337
338 scr &= ~BM_SAIF_CTRL_DELAY;
339 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
340 scr &= ~BM_SAIF_CTRL_JUSTIFY;
341 break;
342 default:
343 return -EINVAL;
344 }
345
346
347 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
348 case SND_SOC_DAIFMT_IB_IF:
349 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
350 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
351 break;
352 case SND_SOC_DAIFMT_IB_NF:
353 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
354 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
355 break;
356 case SND_SOC_DAIFMT_NB_IF:
357 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
358 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
359 break;
360 case SND_SOC_DAIFMT_NB_NF:
361 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
362 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
363 break;
364 }
365
366
367
368
369
370
371
372
373 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
374 case SND_SOC_DAIFMT_CBS_CFS:
375 if (saif->id == saif->master_id)
376 scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
377 else
378 scr |= BM_SAIF_CTRL_SLAVE_MODE;
379
380 __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
381 break;
382 default:
383 return -EINVAL;
384 }
385
386 return 0;
387}
388
389static int mxs_saif_startup(struct snd_pcm_substream *substream,
390 struct snd_soc_dai *cpu_dai)
391{
392 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
393 int ret;
394
395
396 saif->fifo_underrun = 0;
397 saif->fifo_overrun = 0;
398
399
400 __raw_writel(BM_SAIF_CTRL_SFTRST,
401 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
402
403
404 __raw_writel(BM_SAIF_CTRL_CLKGATE,
405 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
406
407 ret = clk_prepare(saif->clk);
408 if (ret)
409 return ret;
410
411 return 0;
412}
413
414static void mxs_saif_shutdown(struct snd_pcm_substream *substream,
415 struct snd_soc_dai *cpu_dai)
416{
417 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
418
419 clk_unprepare(saif->clk);
420}
421
422
423
424
425
426static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
427 struct snd_pcm_hw_params *params,
428 struct snd_soc_dai *cpu_dai)
429{
430 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
431 struct mxs_saif *master_saif;
432 u32 scr, stat;
433 int ret;
434
435 master_saif = mxs_saif_get_master(saif);
436 if (!master_saif)
437 return -EINVAL;
438
439
440 if (!saif->mclk && saif->mclk_in_use) {
441 dev_err(cpu_dai->dev, "set mclk first\n");
442 return -EINVAL;
443 }
444
445 stat = __raw_readl(saif->base + SAIF_STAT);
446 if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) {
447 dev_err(cpu_dai->dev, "error: busy\n");
448 return -EBUSY;
449 }
450
451
452
453
454
455
456 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
457 if (ret) {
458 dev_err(cpu_dai->dev, "unable to get proper clk\n");
459 return ret;
460 }
461
462 if (saif != master_saif) {
463
464
465
466
467
468
469
470 clk_enable(saif->clk);
471 ret = clk_set_rate(saif->clk, 24000000);
472 clk_disable(saif->clk);
473 if (ret)
474 return ret;
475
476 ret = clk_prepare(master_saif->clk);
477 if (ret)
478 return ret;
479 }
480
481 scr = __raw_readl(saif->base + SAIF_CTRL);
482
483 scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
484 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
485 switch (params_format(params)) {
486 case SNDRV_PCM_FORMAT_S16_LE:
487 scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
488 break;
489 case SNDRV_PCM_FORMAT_S20_3LE:
490 scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
491 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
492 break;
493 case SNDRV_PCM_FORMAT_S24_LE:
494 scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
495 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
496 break;
497 default:
498 return -EINVAL;
499 }
500
501
502 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
503
504 scr &= ~BM_SAIF_CTRL_READ_MODE;
505 } else {
506
507 scr |= BM_SAIF_CTRL_READ_MODE;
508 }
509
510 __raw_writel(scr, saif->base + SAIF_CTRL);
511 return 0;
512}
513
514static int mxs_saif_prepare(struct snd_pcm_substream *substream,
515 struct snd_soc_dai *cpu_dai)
516{
517 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
518
519
520 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
521 saif->base + SAIF_CTRL + MXS_SET_ADDR);
522
523 return 0;
524}
525
526static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
527 struct snd_soc_dai *cpu_dai)
528{
529 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
530 struct mxs_saif *master_saif;
531 u32 delay;
532 int ret;
533
534 master_saif = mxs_saif_get_master(saif);
535 if (!master_saif)
536 return -EINVAL;
537
538 switch (cmd) {
539 case SNDRV_PCM_TRIGGER_START:
540 case SNDRV_PCM_TRIGGER_RESUME:
541 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
542 if (saif->state == MXS_SAIF_STATE_RUNNING)
543 return 0;
544
545 dev_dbg(cpu_dai->dev, "start\n");
546
547 ret = clk_enable(master_saif->clk);
548 if (ret) {
549 dev_err(saif->dev, "Failed to enable master clock\n");
550 return ret;
551 }
552
553
554
555
556
557 if (saif != master_saif) {
558 ret = clk_enable(saif->clk);
559 if (ret) {
560 dev_err(saif->dev, "Failed to enable master clock\n");
561 clk_disable(master_saif->clk);
562 return ret;
563 }
564
565 __raw_writel(BM_SAIF_CTRL_RUN,
566 saif->base + SAIF_CTRL + MXS_SET_ADDR);
567 }
568
569 if (!master_saif->mclk_in_use)
570 __raw_writel(BM_SAIF_CTRL_RUN,
571 master_saif->base + SAIF_CTRL + MXS_SET_ADDR);
572
573 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
574
575
576
577
578
579
580
581 __raw_writel(0, saif->base + SAIF_DATA);
582 __raw_writel(0, saif->base + SAIF_DATA);
583 } else {
584
585
586
587
588
589
590
591 __raw_readl(saif->base + SAIF_DATA);
592 __raw_readl(saif->base + SAIF_DATA);
593 }
594
595 master_saif->ongoing = 1;
596 saif->state = MXS_SAIF_STATE_RUNNING;
597
598 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
599 __raw_readl(saif->base + SAIF_CTRL),
600 __raw_readl(saif->base + SAIF_STAT));
601
602 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n",
603 __raw_readl(master_saif->base + SAIF_CTRL),
604 __raw_readl(master_saif->base + SAIF_STAT));
605 break;
606 case SNDRV_PCM_TRIGGER_SUSPEND:
607 case SNDRV_PCM_TRIGGER_STOP:
608 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
609 if (saif->state == MXS_SAIF_STATE_STOPPED)
610 return 0;
611
612 dev_dbg(cpu_dai->dev, "stop\n");
613
614
615 delay = USEC_PER_SEC / master_saif->cur_rate;
616
617 if (!master_saif->mclk_in_use) {
618 __raw_writel(BM_SAIF_CTRL_RUN,
619 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR);
620 udelay(delay);
621 }
622 clk_disable(master_saif->clk);
623
624 if (saif != master_saif) {
625 __raw_writel(BM_SAIF_CTRL_RUN,
626 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
627 udelay(delay);
628 clk_disable(saif->clk);
629 }
630
631 master_saif->ongoing = 0;
632 saif->state = MXS_SAIF_STATE_STOPPED;
633
634 break;
635 default:
636 return -EINVAL;
637 }
638
639 return 0;
640}
641
642#define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000
643#define MXS_SAIF_FORMATS \
644 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
645 SNDRV_PCM_FMTBIT_S24_LE)
646
647static const struct snd_soc_dai_ops mxs_saif_dai_ops = {
648 .startup = mxs_saif_startup,
649 .shutdown = mxs_saif_shutdown,
650 .trigger = mxs_saif_trigger,
651 .prepare = mxs_saif_prepare,
652 .hw_params = mxs_saif_hw_params,
653 .set_sysclk = mxs_saif_set_dai_sysclk,
654 .set_fmt = mxs_saif_set_dai_fmt,
655};
656
657static int mxs_saif_dai_probe(struct snd_soc_dai *dai)
658{
659 struct mxs_saif *saif = dev_get_drvdata(dai->dev);
660
661 snd_soc_dai_set_drvdata(dai, saif);
662
663 return 0;
664}
665
666static struct snd_soc_dai_driver mxs_saif_dai = {
667 .name = "mxs-saif",
668 .probe = mxs_saif_dai_probe,
669 .playback = {
670 .channels_min = 2,
671 .channels_max = 2,
672 .rates = MXS_SAIF_RATES,
673 .formats = MXS_SAIF_FORMATS,
674 },
675 .capture = {
676 .channels_min = 2,
677 .channels_max = 2,
678 .rates = MXS_SAIF_RATES,
679 .formats = MXS_SAIF_FORMATS,
680 },
681 .ops = &mxs_saif_dai_ops,
682};
683
684static const struct snd_soc_component_driver mxs_saif_component = {
685 .name = "mxs-saif",
686};
687
688static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
689{
690 struct mxs_saif *saif = dev_id;
691 unsigned int stat;
692
693 stat = __raw_readl(saif->base + SAIF_STAT);
694 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
695 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
696 return IRQ_NONE;
697
698 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
699 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
700 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
701 saif->base + SAIF_STAT + MXS_CLR_ADDR);
702 }
703
704 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
705 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
706 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
707 saif->base + SAIF_STAT + MXS_CLR_ADDR);
708 }
709
710 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
711 __raw_readl(saif->base + SAIF_CTRL),
712 __raw_readl(saif->base + SAIF_STAT));
713
714 return IRQ_HANDLED;
715}
716
717static int mxs_saif_mclk_init(struct platform_device *pdev)
718{
719 struct mxs_saif *saif = platform_get_drvdata(pdev);
720 struct device_node *np = pdev->dev.of_node;
721 struct clk *clk;
722 int ret;
723
724 clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk",
725 __clk_get_name(saif->clk), 0,
726 saif->base + SAIF_CTRL,
727 BP_SAIF_CTRL_BITCLK_MULT_RATE, 3,
728 0, NULL);
729 if (IS_ERR(clk)) {
730 ret = PTR_ERR(clk);
731 if (ret == -EEXIST)
732 return 0;
733 dev_err(&pdev->dev, "failed to register mclk: %d\n", ret);
734 return PTR_ERR(clk);
735 }
736
737 ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
738 if (ret)
739 return ret;
740
741 return 0;
742}
743
744static int mxs_saif_probe(struct platform_device *pdev)
745{
746 struct device_node *np = pdev->dev.of_node;
747 struct resource *iores;
748 struct mxs_saif *saif;
749 int irq, ret = 0;
750 struct device_node *master;
751
752 if (!np)
753 return -EINVAL;
754
755 saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL);
756 if (!saif)
757 return -ENOMEM;
758
759 ret = of_alias_get_id(np, "saif");
760 if (ret < 0)
761 return ret;
762 else
763 saif->id = ret;
764
765 if (saif->id >= ARRAY_SIZE(mxs_saif)) {
766 dev_err(&pdev->dev, "get wrong saif id\n");
767 return -EINVAL;
768 }
769
770
771
772
773
774
775 master = of_parse_phandle(np, "fsl,saif-master", 0);
776 if (!master) {
777 saif->master_id = saif->id;
778 } else {
779 ret = of_alias_get_id(master, "saif");
780 if (ret < 0)
781 return ret;
782 else
783 saif->master_id = ret;
784
785 if (saif->master_id >= ARRAY_SIZE(mxs_saif)) {
786 dev_err(&pdev->dev, "get wrong master id\n");
787 return -EINVAL;
788 }
789 }
790
791 mxs_saif[saif->id] = saif;
792
793 saif->clk = devm_clk_get(&pdev->dev, NULL);
794 if (IS_ERR(saif->clk)) {
795 ret = PTR_ERR(saif->clk);
796 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
797 ret);
798 return ret;
799 }
800
801 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
802
803 saif->base = devm_ioremap_resource(&pdev->dev, iores);
804 if (IS_ERR(saif->base))
805 return PTR_ERR(saif->base);
806
807 irq = platform_get_irq(pdev, 0);
808 if (irq < 0) {
809 ret = irq;
810 dev_err(&pdev->dev, "failed to get irq resource: %d\n",
811 ret);
812 return ret;
813 }
814
815 saif->dev = &pdev->dev;
816 ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0,
817 dev_name(&pdev->dev), saif);
818 if (ret) {
819 dev_err(&pdev->dev, "failed to request irq\n");
820 return ret;
821 }
822
823 platform_set_drvdata(pdev, saif);
824
825
826 if (saif->id == 0) {
827 ret = mxs_saif_mclk_init(pdev);
828 if (ret)
829 dev_warn(&pdev->dev, "failed to init clocks\n");
830 }
831
832 ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component,
833 &mxs_saif_dai, 1);
834 if (ret) {
835 dev_err(&pdev->dev, "register DAI failed\n");
836 return ret;
837 }
838
839 ret = mxs_pcm_platform_register(&pdev->dev);
840 if (ret) {
841 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
842 return ret;
843 }
844
845 return 0;
846}
847
848static const struct of_device_id mxs_saif_dt_ids[] = {
849 { .compatible = "fsl,imx28-saif", },
850 { }
851};
852MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids);
853
854static struct platform_driver mxs_saif_driver = {
855 .probe = mxs_saif_probe,
856
857 .driver = {
858 .name = "mxs-saif",
859 .of_match_table = mxs_saif_dt_ids,
860 },
861};
862
863module_platform_driver(mxs_saif_driver);
864
865MODULE_AUTHOR("Freescale Semiconductor, Inc.");
866MODULE_DESCRIPTION("MXS ASoC SAIF driver");
867MODULE_LICENSE("GPL");
868MODULE_ALIAS("platform:mxs-saif");
869